ppc405 dma - vm - cache question

[Eric Valette]

gregory.menke at gsfc.nasa.gov wrote:

> The ethernet hardware and packet buffers must be non-cached, else the
> cache will interfere with reading and writing the registers as well as
> the packet buffers.

True for the registers; for buffers it depends if the transfer is via 
DMA or not (I did not read the beginning of the thread so forgive me if 
it is obvious)

-- eric