problems with MPC850 cache
Sergey Ablalimov
sa at design.morion.ru
Wed Sep 1 08:27:30 UTC 2004
Hi,
I try enable I- and D-cache on our MPC850 board. My BSP based on mbx8xx. When
I/D-cache disabled - all work.
I presume that it is mmu initialization problem, but can't find it.
Can anybody help me?
MMU_TLB_table_t MMU_TLB_table[] = {
/*
* SDRAM: Start address 0x00000000, 16M,
* ASID=0x0, APG=0x0, not guarded memory,
* R/W,X for all, no ASID comparison, not cache-inhibited.
* EPN TWC RPN
*/
{ 0x00000200, 0x0D, 0x000009FD }, /* DRAM - PS=8M */
{ 0x00800200, 0x0D, 0x008009FD }, /* DRAM - PS=8M */
/*
*
* boot_flash: Start address 0xfff00000, 512K,
* ASID=0x0, APG=0x0, not guarded memory,
* R/W,X for all, no ASID comparison, cache-inhibited.
*
* EPN TWC RPN
*/
{ 0xFFF00200, 0x05, 0xFFF009FF }, /* boot_flash - PS=512K */
/*
*
* flash_disk: Start address 0x01200000 4x2Kb
* ASID=0x0, APG=0x0, not guarded memory,
* R/W,X for all, no ASID comparison, cache-inhibited.
* EPN TWC RPN
*/
{ 0x01200200, 0x01, 0x012009F7 }, /* flash_disk - PS=4K */
{ 0x01201200, 0x01, 0x012019F7 }, /* flash_disk - PS=4K */
/*
*
* pld: Start address 0x02000000, 256K,
* ASID=0x0, APG=0x0, not guarded memory,
* R/W,X for all, no ASID comparison, cache-inhibited.
* EPN TWC RPN
*/
{ 0x02000200, 0x05, 0x020009FF }, /* pld - PS=512K */
/*
*
* (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K,
* ASID=0x0, APG=0x0, guarded memory, write-through data cache policy,
* R/W,X for all, no ASID comparison, cache-inhibited.
* EPN TWC RPN
*/
{ 0xFA200200, 0x13, 0xFA2009FF } /* IMMR - PS=16K */
};
In ...\cpukit\score\cpu\powerpc\rtems\score\ppc.h for mpc850 I add:
#define PPC_ALIGNMENT 4
#define PPC_I_CACHE 2048
#define PPC_D_CACHE 1024
#define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_FPU 0
#define PPC_HAS_DOUBLE 0
#define PPC_USE_MULTIPLE 1
--
Sergey
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