powerpc/helas403 linkcmd question

[Smith, Gene]

Joel Sherrill <joel at OARcorp.com> wrote, On 9/10/2004 6:08 PM:

> Smith, Gene wrote:
> 
>>>Just to be a little begging... it really would be nice to get the
>>>4xx PowerPCs converted over to the new interrupt model.
>>>
>>>That would only leave a few 60x BSPs left on the old exception
>>>model to deal with and then the old model could die.
>>>
>>>--joel
>>
>>
>>Joel,
>>Sorry, I have no ideal what you mean by "old" vs. "new." Would be glad 
>>to take a look at it if I knew what it was :-)
>>-gene
> 
>

Preface: My problem is that I barely understand how the ppc405 works 
after reading (some of)its 1200+ page manual. How it differs from other 
ppc versions is currently a bit beyond me. Therefore, my comments below 
should be taken as non-authoritative.

> 
> The new exception model is the one used on the most 6xx and all 5xx, 
> 8xx, 82xx, 7xx, and 7xx powerpc's.  The old exception model does not
> really account for external PICs and thus is not as flexible on
> architectures like the PowerPC which only have a single external
> interrupt.  The old model is great on CPUs with lots of vectors.

Concentrating on the ppc405 specific rtems code, it does appear to 
support the on-chip PIC-like UIC (Univeral Interrupt Controller) in the 
device. However, it does not seem to currently support the concept of 
"critical" external interrupts. With critical external interrupts (which 
all start running at memory location defined by EVPR||0x100) you can 
define a memory block using register UIC0_VCR, which specifies the base 
location of your user defined interrupt handlers (allowing up to 512 
bytes per handler) or the location of a jump table to the handlers 
(method is up to system s/w). When a critial interrupt occurs and the 
processor vectors to EVPR||0x100, in the code at that location (in rtems 
it is called _ISR_HandlerC, C for critical) you can just read the 
register UIC0_VR to obtain the location of the user's handler and go 
right to it with no looping, masking or searching.

(Note: external interrupts mean external to the ppc core, e.g., uart, 
eth, pci, and not just interrupts coming in from outside the chip such 
as IRQ-12. 32 max extern ints are possible.)

With current rtems I can't see that the _ISR_HandlerC would ever be 
called for external interrupts since I don't see anywhere that any are 
marked "critical" using the UICO_CR register. Instead, when a 
non-critcal external interrupt occurs (EVPR||0x500) _ISR_Handler is 
called which in turn (I think) calls ictrl_isr() in 
libcpu/powerpc/ppc403/ictrl/ which checks each possible bit (32) in a 
loop using the UIC0_SR and UIC0_ER and locates in its own table the 
appropriate user defined handler to call.

I can see that the setup of a non-looping method would be somewhat 
different than is presently done. Also, you have to deal with the 
concept of "priority" on the 32 external interrupts. A high priority int 
could block a lower priority one from ever being serviced, while the 
current method seems to give all extern ints equal priority (which may 
not be good).

Letting the UIC generate the handler vector (in UIC0_VR) might be better 
than the current masking/looping method, I am not sure. This appears to 
be a "new exception model" but I am not sure if this type of change is 
what you have in mind, or is it applies to other ppc archs besides ppc405.

> 
> So there is a somewhat different interrupt model from the BSPs
> perspective on the new exception model.  It is used by the
> x86 and PowerPC.

But not all PPC use the new model, as you indicate. According to what I see:

PPC bsp's using new:
	eth_comm
	mbx8xx
	motorola_powerpc
	mpc8260
PPC bsp's using old:
	dvm177
	gen405
	helas403
	ppcn_60x
	pism
	score603e

Does new vs. old apply to other archs such as m68k? I used x86 on 
rtems-4.5. Has the int model changed in x86 4.6 (sorry, haven't looked)?

> 
> Look at the difference between 
> libbsp/powerpc/support/*_exception_processing.

Still not sure of diff between old an new looking at this.

> 
> Thomas might be able to share some insight.

I would say so since he seems to have written the 40x stuff plus a lot more.

> 
> I would cc Jennifer since she has finished converting psim
> from old to new in her own tree but she is on vacation right
> now and will have enough email when she gets back. :)
> --joel