New PCI API

[Till Straumann]

A while ago there was a discussion about how
BSPs with more than one PCI bus attached to
the host bridge should be handled (i.e., there
is no 'root' bridge combining the two busses).

I believe we agreed upon letting the BSP hide
this architecture and taking care of chosing the
right 'hose' based on the bus#.

This solves access to the configuration space(s)
but not to PCI memory and IO space. Also, it
doesn't address mapping CPU memory to PCI
(for DMA and the like).

Traditionally, the BSP simply provided macros

PCI_MEM_BASE, PCI_IO_BASE, PCI_DRAM_OFFSET
etc.

This approach is not good enough when multiple
'PCI hoses' are involved.

Therefore, I'd propose to deprecate those macros
and require BSPs to provide routines e.g.,

   /* return pci busx memory space as seen from CPU */ 
void *pci_mem_base(int busx);
   /* return pci busx IO space as seen from CPU */
void *pci_io_base(int busx);
   /* board memory as seen from PCI busx */
void *pci_ram_base(int busx);

RFC
-- Till