PCI caching question related to mvme5500

gregory.menke at gsfc.nasa.gov gregory.menke at gsfc.nasa.gov
Tue Nov 1 16:29:49 UTC 2005

Chris Caudle writes:
 > On Tuesday 01 November 2005 05:06 am, Peter Dufault wrote:
 > > This has to do with accessing a PCI  
 > > card's memory through a cached region.
 > I don't think I've ever seen anyone map a PCI card into cacheable memory 
 > space.
 > How does the cache know whether the data in the cache is out of date or not?  
 > Since it is a data acquisition card, presumably data could have been acquired 
 > since the last time the cache was filled, so how do you mark the data 
 > currently in the cache as invalid?  Does the driver issue a cache flush 
 > command every time it begins to read in the new data?

PCI implementations provide cacheable memory spaces, intended for things
like video ram back when such things were put on a PCI bus.  

I agree its unlikely that setting up a dac board with cacheable memory
will achieve anything useful and might well mess up the device IO
protocol.  IIRC its the same as regular PCI access except the host
hardware can choose to preload the cache from the region.  No
performance advantage will be seen except when cache hits occur- and
that won't happen unless the memory is being fetched anyway.  I suspect
cachable space is advantageous when there are lots of small reads/writes
over the space that a cache would help consolidate and/or prevent from
turning into PCI transactions.

OTOH, maybe the board has an internal buffer that it fills w/ data and
making that part cacheable might expedite copying it off the board.  But
I think the OP would be better served by using DMA- my impression being
its plain PIO right now, which can cut throughput on the PCI bus by a
factor of 6.


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