PCI caching question related to mvme5500
chris at chriscaudle.org
Tue Nov 1 17:08:52 UTC 2005
On Tuesday 01 November 2005 10:29 am, gregory.menke at gsfc.nasa.gov wrote:
> PCI implementations provide cacheable memory spaces, intended for things
> like video ram back when such things were put on a PCI bus.
Yes, but in those cases you can snoop the bus traffic to find out whether the
data in cache is out of date or not. Presumably a data acquisition board
will not be acquiring the data across the PCI bus, so there is no way to
snoop the data to know when the cached data is no longer valid.
> OTOH, maybe the board has an internal buffer that it fills w/ data and
> making that part cacheable might expedite copying it off the board.
I suspect that what is desired is an easy way to cause back to back reads on
the PCI bus. Of course the "proper" way to do it (in the sense of best bus
efficiency) would be for the acquisition card to perform burst writes into
processor memory, but I assume the acquisition card doesn't have a DMA
engine, hence the need for these strange PCI hacks.
But that doesn't really answer my original question, which was how does the
cache know whether to return the data already in cache, or whether to fetch
new data from the PCI device. When using cache, there is typically some kind
of coherency mechanism so that you don't have to concern your software with
whether the data is in main memory or in cache, you just let the hardware
figure it out and return the data from the fastest path.
Would this type of arrangement require that the software explicitly mark the
cache as invalid before it begins reading from the acquisition card address
space? That is the only way I can think of off the top of my head to ensure
that you don't read stale data by mistake.
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