PCI caching question related to mvme5500

[Kate Feng]

Peter Dufault wrote:

> On Nov 1, 2005, at 2:50 PM, Till Straumann wrote:
>
> > No. Currently, PCI memory space is mapped through a BAT as
> > cache-inhibited/guarded. Supporting pre-fetchable memory on
> > PCI devices would require
> >   a) setting up a second mapping marked as cacheable (BAT or
> >      pagetables)
> >   b) reconfiguring all cacheable devices to use addresses
> >      mapped by a)
> >   c) resolving coherency issues [probably the hardest]
> >
> > Regarding b), note that it is potentially dangerous to
> > simply map the same physical address range twice, i.e.,
> > both, caching-inhibited and caching-allowed.
>
> I guess I'll stick with my local hack then, which is to map cacheable
> through a BAT and only access the boards sample memory there.  I
> don't get your note, though.   What can happen if you have something
> like that sample memory mapped twice?
>
> It isn't worth signing an NDA and implementing DMA for this application.

You should sign up the NDA if you want to improve the performance
of the board.  There are two aspects you can improve by programming
the registers of the system controller GT64260.  If you need to
custom design the H/W for this application, I would recommend you to
use this system controller or the GT64360 depending on your application.


I  wish you understand that NDA means "Non Disclosure Agreement".
Thus, what I can disclose is limitted.  Please remember I have to
follow the agreement that was signed.


Cheers,
Kate