Strange behavior when running RTEMS on an ERC32 chipset Tharsys board

Fabrício de Novaes Kucinskis fabricio at
Thu Sep 1 18:58:02 UTC 2005

I'm working with a Tharsys board with a ERC32 chipset (TSC691E + TSC69È +
TSC69É), and I noticed a very strange behavior when the RTEMS is being

When trying to execute the example program "rtems-task" in the board, the
RTEMS freezes for some seconds, and then the watchdog timer resets the

After many hours of debugging, I discovered that the problem occurs when the
RTEMS tries to read _ CLOCK_SPEED, stored in the address 0x020007e0.  This
address is in the trap table area of the ERC32.

At the moment where the RTEMS tries to read this value, what is written in
this position of memory is not the clock value, but the instruction "ta 0".

What I noticed was that, in the first instructions of the RTEMS, the Trap
Base Register (TBR) is configured. At this moment, some addresses of the
trap table have its routines modified, including the address of

What I don't understand is that the overlapping of trap table occurs in the
execution of the instruction that modifies the TBR, what for me doesn't make
sense. I verified the system registers, and none trap occurred at this

It is important to notice that this problem doesn't happen in the Sparc
Instruction Simulator.

I solved the problem with a small patch, rewriting the address _ CLOCK_SPEED
after the TBR configuration, but I would like to know what is triggering the
overwriting of the trap table.

Did somebody already find this problem using RTEMS with ERC32 (the real one,
not the simulator)?
Thanks in advance and best regards,

Fabrício de Novaes Kucinskis - DEA / INPE
Divisão de Eletrônica Aeroespacial
Instituto Nacional de Pesquisas Espaciais

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