Call for SPARCengine 1e BSP

[Jiri Gaisler]

Since you asked, here my view on the topic ...

The ERC32 is not very similar to the Fujitsu MB86901A
processor used in the Sparcengine 1e. The integer
pipeline implements the same SPARC V7 instruction set,
but the memory hierarchy is completely different.
MB86901A has a cache, an MMU, and DRAM main memory.
ERC32 has no cache, no MMU and executes directly
from 0-waitstate external static RAM. The peripherals
(uart, timers, irq ctrl, I/O) are completely different.
I also believe that the MB86901A has 7  register
windows while ERC32 (based on Cypress 601) has 8.

It should be possible to develop an SS 1E bsp, but
all low level code (drivers and init) will becdifferent
from ERC32. So the only RTEMS part you really can
reuse is the general SPARC support. The complete
bsp and associated drivers must be written from
scratch. This means that you need detailed
data sheets with register definitions, address
allocation and interrupt routing. Unless you
have that, it will be very difficult (impossible?).

If you really want some cheap SPARC hardware,
why not get a low-cost FPGA board (~ $500) and
put a LEON3 on it. There is a stable RTEMS bsp
for it (yes, I will soon merge it in to the main tree)
and the VHDL code and development tools are free.
OK, there is no VME but do you really need that?

An other aspect is that we have today announced
the availability of LEON3FT parts on the Actel
RTAX2000 radiation-hardened FPGA devices. There
will be various pre-programmed LEON3FT devices
with 1553, CAN-2.0 and Spacewire available, as well
as netlists if you want to make you own FPGA config.
Performance is 20 - 30 MHz, on par or better than ERC32,
but with only ~ 0.5W power consumption. For software
development, you can use cheap Xilinx/ALtera boards
or a commercial grade AX2000 device (~ $250).
Debugging is also significantly easier than ERC32,
you have a real on-chip debug support unit, with
single-stepping, tracing and memory/register access.

Jiri.


Joel Sherrill <joel at OARcorp.com> wrote:
> Ivan Galkin wrote:
> 
>> Inspired by Joel's invitation, here's a call for a BSP port to 
>> SPARCengine 1e board.
> 
> 
> Does this match any of the hardware in the list at?
> 
> http://www.netbsd.org/Ports/sparc/
> 
> If you can boot NetBSD, then you have (OK someone has) all the driver 
> information you need.  Not in the best form but there.
> 
> I updated your Wiki entry to include information on how to
> address the a.out boot loader and som eother thoughts.  See
> 
> http://www.rtems.com/wiki/index.php/SPARCengine_1e
> 
>> SPARCengine 1e is a SPARC V7 board in VME, circa 1991.
>> This CPU was used as a prototype for the ERC32 chipset.
>> The existing RTEMS ERC32 BSP does not work on SPARCengine 1e (see below).
>>
>> Motivation for BSP port:
>> An ERC32 evaluation board can be found at $15-18K from Atmel or 
>> Tharsys, whereas a used Force CPU-1CE or CPU-2CE boards are a mere 
>> $100 on ebay. The ERC32 VME boards continue to be a viable choice of 
>> radiation-hardened embedded systems for space applications.
> 
> 
> Does Force have any documentation?  How about the ESA folks who 
> originally did the ERC32?  I know it is old but Jiri.... any thoughts?
> 
>> Known problems with Rtems ERC32 on SPARCEngine 1e:
>> ERC32 BSP is in ELF format, whereas SPARCengine bootloader supports 
>> a.out-sunos-big only.
>> Very little expert help can be found, the board is too old.
>> Original SUN libraries for this board are hard to find.
>>
>> Potential problems:
>> MMU got redesigned in ERC32.
>> VME support looks board-specific.
>>
>> Hope to hear from someone interested.
>> Ivan
>>
> 
>