RTEMS for NIOS2 update; new BSP for NIOS II simulator

[Waschk,Kolja]

Hi,

Some updates to my adaptation of RTEMS for use with Altera's NIOS2 softcore CPU:

BSP: now named nios2_iss, adapted to run in the NIOS II instruction set
simulator (using default ISS configuration with 1x JTAG UART, 1x Timer for
clock, plus 1x additional timer for the tmtests).

SCORE: Instruction cache is properly initialized and can be used if
available in target.

BSP and SCORE: Removed all header files that I previously just copied from
Altera sources. What remains is a very minimal set of definitions that
probably have to be extended in the future as required.

TOOLS: Initial (not yet finished) version of nios2gen, a tool to derive a
custom BSP setup from a SOPC Builder system description *.PTF file.

A single tar.gz archive contains my patches to newlib-1.14, rtems-cvs, and
a small script that I'm using to build it all. The archive is available as
the first in the list of downloads listed on

  http://www.ixo.de/info/rtems_nios2/

I hope the archive is complete and I didn't exclude anything important.
Don't hesitate to mail me if you find something missing.

I'm still using a wrapped Altera's nios2-elf toolchain and not a proper
nios2-rtems one. However, I finally managed to create a quite clean set of
patches to make a source tree (from GNU original sources) compilable for
nios2-elf, and Joel already offered to help with the creation of a
nios2-rtems configuration. Therefore, there's hope that someday we'll get a
real nios2-rtems-gcc. Those patches are available on request only because
they're quite large and the www.ixo.de server isn't made for big traffic.

Kolja

-- 
Mr. Kolja Waschk, waschk/telos.de - +49(40) 450173-0; Fax -99
telos EDV Systementwicklung GmbH - Schlueterstrasse 16 - D-20146 Hamburg