erc32 fpu rev.B/rev.C bug

[Aleix Conchillo Flaqué]

Hi,

may be this is an RTEMS offtopic, but I've seen that in SPARC RTEMS  
interrupt manager (_ISR_Handler, cpu_asm.S), there is a fix for FPU  
rev.B or rev.C.

Does anyone know where to find information about this bug? I've been  
looking in my ERC32 chip manuals and errata, but haven't seen  
anything related to this. I think is something related to the  
interrupt priority level.

Thanks in advance.

aleix