erc32 fpu rev.B/rev.C bug

[Jiri Gaisler]

The FPU bug only applies to the old 3-chip version of ERC32
(which is controlling the Space Station ..!). If you use the newer
single-chip version of ERC32 (TSC695), then the FPU bug is fixed.

Jiri.

Aleix Conchillo Flaqué wrote:
> Hi,
> 
> may be this is an RTEMS offtopic, but I've seen that in SPARC RTEMS  
> interrupt manager (_ISR_Handler, cpu_asm.S), there is a fix for FPU  
> rev.B or rev.C.
> 
> Does anyone know where to find information about this bug? I've been  
> looking in my ERC32 chip manuals and errata, but haven't seen  anything 
> related to this. I think is something related to the  interrupt priority 
> level.
> 
> Thanks in advance.
> 
> aleix
> 
> .
>