Why do the ARM920 based BSPs enable the MMU ?
Thomas Doerfler (nt)
Thomas.Doerfler at imd-systems.de
Thu Mar 15 19:30:20 UTC 2007
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I am no ARM expert, but when I look into the arm/csb337/startup/memmap.c
file, it seems the MMU also controls, which memory ranges are cachable.
This is similar to the PowerPC architecture.
Although RTEMS uses a common memory for all threads and there is
normally no memory protection, disabling the cache for some areas is
Simon Clubley schrieb:
> Given the single address space nature of RTEMS, why do the ARM920
> based BSPs such as the CSB337 bother enabling the MMU instead of
> just leaving it disabled ?
> Is there some subtle aspect of ARM MMU operations that I am missing ?
> The only thing that I have found is that there's a double address
> space mapping of the SRAM and I'm not even sure if that's really
> If that (or the ability to map separate SDRAM areas into one
> contiguous memory area) is not required, then is there any point in
> enabling the MMU on ARM processors ?
> Thanks for any information,
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