Why do the ARM920 based BSPs enable the MMU ?

[Pavel Pisa]

On Thursday 15 March 2007 20:30, Thomas Doerfler (nt) wrote:
> Simon,
>
> I am no ARM expert, but when I look into the arm/csb337/startup/memmap.c
> file, it seems the MMU also controls, which memory ranges are cachable.
> This is similar to the PowerPC architecture.
>
> Although RTEMS uses a common memory for all threads and there is
> normally no memory protection, disabling the cache for some areas is
> quite important.
>
> wkr,
> Thomas.

Hello All,

Thomas is right, that D-CACHE has to to be controlled by MMU
to allow peripherals direct access in some areas.
I-CACHE doesnot require that, because instruction should
be fetched from areas, which do not change on the fly.
The I-CACHE has to be explicitly flushed for regions
where code is replaced at runtime on ARM (on PowerPC too),
for example, if some module is loaded at runtime.

There is other reason for ARM920 BSPs to enable MMU.
I-CACHE can be enabled by ARM CR register independently
of MMU, but D-CACHE has no direct independent control bit.
It could be enabled only if pagetables are configured
and MMU is switched on. So if you want D-CACHE on ARM9,
you have to enable MMU.

Best wishes

              Pavel Pisa


> Simon Clubley schrieb:
> > Given the single address space nature of RTEMS, why do the ARM920
> > based BSPs such as the CSB337 bother enabling the MMU instead of
> > just leaving it disabled ?
> >
> > Is there some subtle aspect of ARM MMU operations that I am missing ?
> >
> > The only thing that I have found is that there's a double address
> > space mapping of the SRAM and I'm not even sure if that's really
> > required.
> >
> > If that (or the ability to map separate SDRAM areas into one
> > contiguous memory area) is not required, then is there any point in
> > enabling the MMU on ARM processors ?
> >
> > Thanks for any information,
> >
> > Simon.
> >
> >
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