Caches on G2 PowerPC/network problem

Leon Pollak leonp at
Sun Dec 14 16:42:32 UTC 2008


Gurus in PPC and networking, please, help!

G2 manual states that usage of dcbi instruction (cache invalidate) is 
forbidden. And they suggest to use dcbf (cache flush) instead.

This raises the following possible problem.
Consider the network driver which is going to receive some buffer at address 
X. For this, when the DMA reported that data has arrived, the driver should 
execute FLUSH instruction as they recommend.
But flush, before invalidating, will check if the corresponding cache line was 
not updated. And if yes, it will flush cache content back to the memory!

This means, that if one 32byte (CACHE_ALIGNMENT) cache line contains data from 
2 buffers, the arrived data will be spoiled.

I do not understand how to solve this, except by guarantying that each buffer 
returned by MGETHDR(...) and MCLGET(...) is cache aligned.

And how to do this, in turn?

Many thanks ahead for a help.

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