PowerPC BSPs

[Thomas Doerfler (nt)]

Leon,

AFAIK, currently no exception handler in RTEMS checks the RI bit. Teh
machine check might inspect it to find out, whether it is allowed to
return to the interrupted program, but since the current machine check
excpetion handler does not return at all, it makes no sense to do this.

wkr,
Thomas.

Leon Pollak schrieb:
> Till, really thank you for the detailed explanation.
> 
> If I understand what you say, the only exceptions which can interfer in this 
> place are such as critical and machine check, yes? 
> But I did not find any other place where this is used...
> 
> Just, please, can you point me to the "exception handler which sees 'RI' 
> cleared in SRR1" as you say?
> 
> Many thanks.
> 
> On Saturday December 13 2008, Till Straumann wrote:
>> Leon Pollak wrote:
>>> On Friday December 12 2008, Till Straumann wrote:
>>>> Leon Pollak wrote:
>>>>> Hello, all.
>>>>> A simple questions to who knows the answer...:-)
>>>>> All PPC BSPs contain in all interrupt vectors processing the following:
>>>>> before executing the RFI instruction they restore the MSR value back
>>>>> from the saved SRR1 value.
>>>>> Why?
>>>>> The PPC manual states that this is done by the CPU in the RFI
>>>>> instruction.
>>>>> What do I miss?
>>>>> Thanks.
>>>> There are various flavors of that stuff - could you please
>>>> quote the lines and the file you're looking at?
>>>> Till
>>> With pleasure. In rtems 4.8.0:
>>> BSP gen5200/vectors.S, lines about 183;
>>> BSP mpc8260ads/vectors.S, lines about 125;
>>> 	file irq_asm.S lines about 281 & 353;
>>> BSP psim/irq_asm.S, lines about 287 & 338;
>>> BSP mbx8xx/vectors.S, lines about 131;
>>> 	file irq_asm.S, lines about 320 & 392.
>> This fragment of code clears the RI bit in MSR and marks
>> the beginning of a section of code that is 'non-recoverable'.
>>
>> An exception handler which sees 'RI' cleared in SRR1 may
>> thus detect that an exception has occurred somewhere between
>> clearing RI and the RFI instruction. Here's the scenario
>> that the code is trying to guard against (psim/irq_asm.S)
>>
>>     /*
>>      * Disable data and instruction translation. Make path non
>> recoverable...
>>      */
>>     mfmsr   r3
>>     xori    r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
>>     mtmsr   r3
>>     SYNC
>>     /*
>>      * Restore rfi related settings
>>      */
>>
>>     lwz r3, SRR1_FRAME_OFFSET(r1)
>>     mtsrr1  r3
>>     lwz r3, SRR0_FRAME_OFFSET(r1)
>>     mtsrr0  r3
>>
>> ########### if an exception occurs e.g., right here then
>> ########### it is 'non-recoverable' since the contents
>> ########### of SRR0/SRR1 are lost; overwritten with the
>> ########### values of the new exception, e.g.,
>> ########### by 'this' address so the RFI below wouldn't
>> ########### jump where it should.
>> ########### However, by inspecting MSR_RI the exception
>> ########### handler could detect that situation and panic.
>>
>>     lwz r3, GPR3_OFFSET(r1)
>>     addi    r1,r1, EXCEPTION_FRAME_END
>>     SYNC
>>     rfi
>>
>>> As the code looks like, it seems that it is simple copy/paste from one
>>> source.
>> Yes. That's why we have overhauled this stuff and are encouraging
>> new BSP writers to use the code under
>> libcpu/powerpc/new-exceptions/bspsupport
>>
>> HTH
>> -- Till
>>
>>> Thanks.
> 
> 
> 


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