about SPARC V8 Bit Scan Instruction ?

Joel Sherrill joel.sherrill at OARcorp.com
Wed Dec 17 17:39:22 UTC 2008

阎淼 wrote:
> Hi,
>   I see there is a SPARC V8 Bit Scan Instruction Project on the wiki page,
>   but I did not find any specification about SPARC V8 Bit Scan
> Instruction in the manual:
>   http://www.sparc.org/standards/V8.pdf  and in  The LEON Processor
> User's Manual.
>   Could any one give me some directions ?

I have apparently misread something, somewhere long ago. According
to gcc/config/sparc/sparc.md and the binutils opcode table, it is only
the old SPARCLite and Let variants. This code fragment from gcc does
look like it could be better than what we have now.

The goal is to provide the most efficient SPARC implementation of
finding either the first bit set in a word. RTEMS is very flexible.
This is used for priority bit map management and you can have a
port search for the LSB or MSB zero or one set.

So the project should be to implement a SPARC optimized
version of the bitscan functionality.

FWIW the ARM is another place where this optimization is
needed as well. It is also using the generic bitfield code.

score/cpu/*/rtems/score/cpu.h files.


;; The scan instruction searches from the most significant bit while ffs
;; searches from the least significant bit. The bit index and treatment of
;; zero also differ. It takes at least 7 instructions to get the proper
;; result. Here is an obvious 8 instruction sequence.

;; XXX
(define_insn "ffssi2"
[(set (match_operand:SI 0 "register_operand" "=&r")
(ffs:SI (match_operand:SI 1 "register_operand" "r")))
(clobber (match_scratch:SI 2 "=&r"))]
return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32,
%2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0";
[(set_attr "type" "multi")
(set_attr "length" "8")])

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Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
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