about fault tolerance

[gh1983]

hi.how can i get the documents about the fault tolerrance utility(eg EDAC)in rtems?

2008-06-04 



best wishes



发件人： Teng Chee Wan Philip 
发送时间： 2008-06-03  13:00:18 
收件人： rtems-users at rtems.org; Nicolas Horro 
抄送： 
主题： RE: ERC32 EDAC Driver 
 
Hi Nicolas,

Why are you modifying the checkbits for the EDAC test (ie, instead of
0xC, you use 0xD)?  By doing so, the processor may detect that there are
more than 1 bit of error in the data word.  You should be loading 0xC as
the checkbits, and write 0x0000 0002 as the data word (which means 1 bit
error in the data word, since 0xC is the correct checkbits pattern for
0x0000 0001).

If there are more than 1 bit of error, the processor will generate a
non-correctable error in the memory, which is 0x9 Data Access trap.
That is probably what you are observing.

Regards,
Philip

========================================================================
====
Date: Mon, 2 Jun 2008 16:13:16 -0300
From: "Nicolas Horro"  <nhorro at gmail.com >
Subject: ERC32 EDAC Driver
To: rtems-users at rtems.org
Message-ID:
<48cfa58b0806021213n5d6b1f30jfba9d1afba14b1ff at mail.gmail.com >
Content-Type: text/plain; charset="iso-8859-1"

Hi,

I'm working on a simple EDAC driver for ERC32. Tests running on SIS do
nothing and tests running on real hardware produce trap 0x9 (not 0x16,
as it
would be expected).

Driver (basically) does the following:

1. Ensure EDAC is turned on in MEMCFR:

ERC32_MEC.Memory_Configuration |= 0x00004000;

2. Install ISR handler:

/* EDAC_Correction_Handler */
rtems_isr EDAC_Correction_Handler( rtems_vector_number vector ) {
    ++_Sram_Edac.errorCount;
    *( (uint32_t*)ERC32_MEC.First_Failing_Address) =
        *( (uint32_t*)ERC32_MEC.First_Failing_Address);
}

(...)

/* install handler */
rtems_interrupt_catch( EDAC_Correction_Handler,

ERC32_TRAP_TYPE(ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR),
                       &old );

For testing, I'm using a function to write a value with checkbits and
another to read it and produce EDAC trap if checkbits are wrong:

--- file: EDACTest.c --

(...)

uint32_t a;

/* Intentionally write value with wrong CheckBits (Correct CB: 0x2C) */
writeValueWithCheckBits(&a, 0x01, 0x2D):

/* Attempt to read so Trap 0x16 occurs */
readAddress(&a);

(...)

/***********************************************************************
******/
void writeValueWithCheckBits(uint32_t* address,
                             uint32_t value,
                             uint32_t checkbits )
/***********************************************************************
******/
{
    // Enable EDAC Test Mode in TESTCTR
    printf("EDAC Test$ Enabling EDAC Test Mode in Test Control
Register.\n");
    ERC32_MEC.Test_Control = 0x20000;

    // Setting check bits
    printf("EDAC Test$ Writing check bits.\n");
    ERC32_MEC.Test_Control |= checkbits;

    // Write value affected by check bits
    printf("EDAC Test$ Writing '0x%08x' at address '0x%08x'.\n", value,
address);
    *address = value;

    // Disable EDAC Test Mode in TESTCTR
    printf("EDAC Test$ Disabling EDAC Test Mode in Test Control
Register.\n");
    ERC32_MEC.Test_Control &= ~0x20000;
}


/***********************************************************************
******/
void readAddress(uint32_t* address)
/***********************************************************************
******/
{
    uint32_t tmp;

    // Read address
    printf("EDAC Test$ Reading address '0x%08x'. If wrong checkbits,
EDAC
trap should occur.\n", address);
    tmp = address;

    printf("EDAC Test$ Address content is: '0x%08x'.\n", tmp);
}

(...)

Any suggestion? Obviously I'm doing something wrong, but I can't figure
out
what it is.

Greetings and thanks!

Nicol?s Eduardo Horro
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