Caches on MPC8260-like CPUs

Till Straumann strauman at
Wed Oct 8 22:25:48 UTC 2008

Leon Pollak wrote:
> On Wednesday, 8 בOctober 2008, Thomas Doerfler wrote:
>> Leon,
>> the MPC5200 and the MPC83xx are also based on a 603le core (which is
>> only slightly different). We use the caches there properly. What aspects
>> are you interested in?
>> wkr,
>> Thomas.
> Thank you Thomas.
> I have a general question.
> In MPC860 I had a lot of different ways to fill TLBs so, that I had 1:1 
> virtual memory mapping and still was able to define rather good separation 
> between different cache strategies for my RAM. This was provided by the 
> ability to define rather large pages in TLBs (up to 256MB).
> Thus, I never had the page miss interrupt.
> The MPC8260 TLBs have pages fixed to 4KB, as I was able to understand. And 
> there is 64 of them. This means that I need to use the page miss interrupt to 
> redefine the TLB with still the same 1:1 memory mapping?
I don't know the 8260 specifically but if the MMU is like
on other PPCs then you are correct. You'll have to implement
TLB replacement in software. IMO this is not an option on
a hard RTOS.

I had implemented routines (libcpu/powerpc/mpc6xx/mmu/pte121.c)
to program the TLBs and the
hash table for PPCs with hardware TLB replacement
(604+) and I use this when running short on BATs or
when I want more fine-grained control.

But as I said - doing TLB replacement in software
is IMHO not worthwhile.

There are 64 TLBs but you cannot use them arbitrarily;
they are organized in a two-way, 32-entry set which means
that if you want to cover arbitrary virtual addresses then
you really only have 2 (!) freely programmable TLBs.

If you cover contiguous areas then you could cover two
4k*32 = 128k areas.

The bad news is that you'll have to live with BATs
and maybe you can use some of the TLBs (statically
programmed) to cover small, special areas.
> I do not understand something here....
> I thought to use BATs, but there is only 8 of them, which seems to be a bit 
> tight...
IIRC there are only 4 for data access (and 4 for instruction access).

-- Till
> Thank again.

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