Caches on MPC8260-like CPUs
Thomas.Doerfler at embedded-brains.de
Thu Oct 9 05:51:15 UTC 2008
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Leon Pollak wrote:
> On Wednesday, 8 בOctober 2008, Thomas Doerfler wrote:
>> the MPC5200 and the MPC83xx are also based on a 603le core (which is
>> only slightly different). We use the caches there properly. What aspects
>> are you interested in?
> Thank you Thomas.
> I have a general question.
> In MPC860 I had a lot of different ways to fill TLBs so, that I had 1:1
> virtual memory mapping and still was able to define rather good separation
> between different cache strategies for my RAM. This was provided by the
> ability to define rather large pages in TLBs (up to 256MB).
> Thus, I never had the page miss interrupt.
> The MPC8260 TLBs have pages fixed to 4KB, as I was able to understand. And
> there is 64 of them. This means that I need to use the page miss interrupt to
> redefine the TLB with still the same 1:1 memory mapping?
> I do not understand something here....
> I thought to use BATs, but there is only 8 of them, which seems to be a bit
> Thank again.
as Till already has pointed out, you are stuck with the 8 BAT register
pairs. The good news is that you have eight of them, the original 603
only has 4 (!).
You may use some TLBs additionally for small 4k pages of special stuff.
Keep in mind that AFAIK the BATs have a higher priority than the TLBs if
they are programmed to the same (or an overlapping) address range.
If you collect similar address spaces to a common address range, you may
find a way to live with this limitation.
Embedded Brains GmbH
Thomas Doerfler Obere Lagerstrasse 30
D-82178 Puchheim Germany
email: Thomas.Doerfler at embedded-brains.de
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