ARM SAM9 BSP Question

Enrico Lüdecke enrico.luedecke at
Mon Feb 2 10:46:00 UTC 2009

Hi all,

I am working on a BSP for an ARM SAM9 board. At the moment I try to
understand the interrupt handling of the board itself and the RTEMS part
of it. There is a macro in arm/rtems/score/cpu.h called _CPU_ISR_Enable
I don't fully understand:

#define _CPU_ISR_Enable( _level )               \
  {                                             \
    asm volatile ("MSR  cpsr, %0 \n"            \
                  : : "r" (_level));            \

(Just write the content of %0 to the current program status register)

If I leave it in that way, the interrupts aren't enabled as it seems. If
I change it to:

#define _CPU_ISR_Enable( _level )               \
  {                                                \
    int reg;                                    \
    asm volatile ("MRS  %0, cpsr \n"            \
                  "BIC    %1, %0, #0xc0\n"        \
                  "MSR  cpsr, %1 \n"            \
                  : "=&r" (_level), "=&r" (reg));\
(save the cpsr, clear the IRQ and FIQ mask bit, write it back to cpsr)

the interrupts are enabled and all seems to work well. I use a copy of
RTEMS 4.8. In older versions, the code looked more like mine, but now it
doesn't anymore. My question is: Where do I put my working code? Since
I'm writing a BSP, cpu.h seems to be the wrong place.

Please excuse me, if my question is kind of dumb, but I just started
looking over this whole stuff.



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