ARM SAM9 BSP Question

Joel Sherrill joel.sherrill at
Mon Feb 2 14:11:31 UTC 2009

Enrico Lüdecke wrote:
> Thanks for you answers,
> indeed, I misunderstood the purpose of _CPU_ISR_Enable, but if I read
> the RTEMS documentation correctly, all interrupts have to be disabled
> after the initialization of the bsp (is this right?). So somewhere the
> interrupts have to be enabled in the ARM core, by unmasking the FIQ and
> IRQ flags in the CPSR. For now I put this part at the end of bsp_start
> in bspstart.c.
NO! NO! NO!  Interrupts are enabled as part of the
context switch to the first task.  _Thread_Start_multitasking.
> That way all exceptions are enabled at the end of bsp_start. Only IRQ
> and FIQ are disabled by unmasking them in the Interrupt Controller.
> Would that be ok or did I miss something again?
You can do that but they must be off in whatever register
in the CPU that the ISR Enable/Disable pair and context
switch code touch.
> Greetings
> Enrico
> _______________________________________________
> rtems-users mailing list
> rtems-users at

More information about the users mailing list