Potential GsoC candidate: Proof Submission

[Aanjhan R]

Dear All,


I am a potential GSoC candidate and am interested in working with
RTEMS, interest that I developed a few weeks back when I badly wanted
to port for custom developed OpenRISC multiprocessor system (RTL will
be GPLd soonish) in my univ lab (http://lap.epfl.ch). I see the Google
SOC as a nice opportunity for me to get accustomed to the RTEMS
developer culture and environment, and keep contributing to RTEMS.

My portfolio is as follows:
I am Aanjhan doing my Masters in Electronics at EPFL, Lausanne,
Switzerland. A short introduction about me is present in the page
https://wiki.ubuntu.com/Aanjhan

I am part of the Fedora Electronics Laboratory team and also help in
keeping in sync with the packages in Ubuntu as part of the MOTU
Science team. I have experience working on NIOSII processors
(http://fpga4u.epfl.ch) and a few Computer Architecture simulator
tools (e.g. SimpleScalar). I have my own website at
http://www.tuxmaniac.com and blog at http://blog.tuxmaniac.com

Interested Projects: (Will be selecting one for the final proposal
after discussions on IRC)
* Merge BSP for Simplescalar simulator
* Add cache manager support for architectures not having it.  (My
research work is on Cache Coherency protocols for Multiprocessor
systems. So this would help me broaden my knowledge too)
* Page based memory management system (again comes under my research
interest of memories and caches)
* BSPs for CPU Simulators (would like to get more info on the status
and whats needed now. From Wiki I see requirements for ARM PXA models.
Is it still the same status?)

Proof that I can work with RTEMS:
Screenshot: http://tuxmaniac.com/work/screenshots/rtems_gsoc_getting_started.png
Diff : http://tuxmaniac.com/work/rtems_hello.diff

Regards,
Aanjhan