Per CPU Patch -- SMP Step #1

[Joel Sherrill]

Hi

I have been working on SMP support for RTEMS as a background task.
Now that 4.10 has branched, I wanted to get some of the code merged.
PR1573 contains a patch which is the first chunk and it needs as
many eyes on it as possible.

https://www.rtems.org/bugzilla/show_bug.cgi?id=1573

I have an SMP Exploration test which builds upon this and can boot
multi-core systems.  I am testing on the SPARC/LEON3 (quad-core)
and x86/pc386 (qemu with up to 32 cores). I have tried to trim this
patch down to just the Per CPU data structure portion of the work.
This patch ...

+ Adds percpu data structure which contains
     - thread idle, executing, heir
     - isr nest level
     - context switch needed
+ It eliminates two variables about signal sent requiring a dispatch.
     - _ISR_Signals_to_thread_executing
     - _Thread_Do_post_task_switch_extension

That part is good.  The bad part is that it touches EVERY IRQ vectoring
implementation.  I have fully tested this on SPARC and i386.  I have
compiled it for most, if not all, architectures along the way.  I
also have modified the sparc64 .S code that is impacted.

Thanks to Ralf's autoconf suggestion, the sizeof(void *) issues is
dealt with.  I checked that the number was 2 on the avr.

I also had a number of style changes along the way and have tried to
filter them out and went ahead and committed them.  If you see those still
in here, we can commit those separately.

The next steps are to merge the --enable-smp autoconf logic, current
SMP data structure initialization code, and BSP support required
for SMP.  I will try to keep the pieces as small as possible.

Please review and comment.  I really would like to make more progress
on RTEMS SMP and have the work be public.

-- 
Joel Sherrill, Ph.D.             Director of Research&  Development
joel.sherrill at OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
    Support Available             (256) 722-9985