Debugging basic BSP tasking functionality

[Matthew J Fletcher]

All,

Thanks for all your help, with suggestions and advice i now have both error
trapping exceptions, interrupts and task switching running without any
detectable stack corruption.

Sebastian in particular, if your ever in the UK around Birmingham i owe you
a beer.

In case anyone looks at this thread in the future this is how i got it
working on the NXP LPC2292.

1) Make sure you poke the MEMMAP register to move the vector address's from
0x0 (if thats flash), the on chip SRAM. If your ARM chip does not support
this type of extension (its not a core ARM7TDMI feature), then you would
need to use a trampoline in flash to redirect to another address.
2) Your start.s needs to move a pre configured vector_block into this
address, most BSP's do this.
3) Your linkerscript needs to reserve address space at this address, again
most BSP's do this.
4) You need to ensure that you have stacks allocated and assigned for each
exception type. It looks like the IRQ one needs at least 4k.





On 19 April 2013 09:54, Sebastian Huber
<sebastian.huber at embedded-brains.de>wrote:

> On 04/19/2013 10:44 AM, Matthew J Fletcher wrote:
>
>>  >What do you mean with basic interrupt handlers?
>> Not using the IRQ exception handler at 0x18, but like so.
>>
>> --------------------
>>
>> #define VICVectAddr0    REG32(0xFFFFF100)    /* Vector Address 0 Register
>> */
>> #define VICIntEnable    REG32(0xFFFFF010)    /* Interrupt Enable Register
>> */
>> #define VICIntEnClear    REG32(0xFFFFF014)    /* Interrupt Enable Clear
>> Register */
>> #define VICIntSelect    REG32(0xFFFFF00C)    /* Interrupt Select Register
>> */
>>
>> VICIntEnClear = VIC_BIT(VIC_TIMER0);        // Ensure the interrupt is
>> disabled
>> ...
>> VICVectAddr0 = (ULONG)tick_handler;        // Address of the ISR
>> VICIntSelect &= ~VIC_BIT(VIC_TIMER0);        // Timer0 selected as IRQ
>> VICIntEnable = VIC_BIT(VIC_TIMER0);        // Timer0 interrupt enabled
>> VICVectCntl0 = VIC_ENABLE | VIC_TIMER0;
>>
>> ---------------------------
>>
>
> This will not work.
>
>
>
>>  >If you want to keep your exception vectors in the flash, then simply use
>> arm_exc_interrupt >(on 4.10) or _ARMV4_Exception_interrupt (on 4.11) as
>> the
>> entry point for the interrupt >exception.
>>
>> Do you mean passing arm_exc_interrupt as the handler into
>> rtems_interrupt_handler_**install()  ? that still gives an unhandled IRQ
>> exception, probably because there is no handler installed in 0x18.
>>
>
> No, the normal sequence is this:
>
> 1. Interrupt event
> 2. CPU calls _ARMV4_Exception_interrupt via exception table
> 3. This calls bsp_interrupt_dispatch (defined in the BSP)
> 4. This calls the handler installed via rtems_interrupt_handler_**
> install()
>
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-**brains.de<sebastian.huber at embedded-brains.de>
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>



-- 

regards
---
Matthew J Fletcher
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