Debugging basic BSP tasking functionality

[Sebastian Huber]

On 04/19/2013 10:44 AM, Matthew J Fletcher wrote:
>  >What do you mean with basic interrupt handlers?
> Not using the IRQ exception handler at 0x18, but like so.
>
> --------------------
>
> #define VICVectAddr0    REG32(0xFFFFF100)    /* Vector Address 0 Register */
> #define VICIntEnable    REG32(0xFFFFF010)    /* Interrupt Enable Register */
> #define VICIntEnClear    REG32(0xFFFFF014)    /* Interrupt Enable Clear Register */
> #define VICIntSelect    REG32(0xFFFFF00C)    /* Interrupt Select Register */
>
> VICIntEnClear = VIC_BIT(VIC_TIMER0);        // Ensure the interrupt is disabled
> ...
> VICVectAddr0 = (ULONG)tick_handler;        // Address of the ISR
> VICIntSelect &= ~VIC_BIT(VIC_TIMER0);        // Timer0 selected as IRQ
> VICIntEnable = VIC_BIT(VIC_TIMER0);        // Timer0 interrupt enabled
> VICVectCntl0 = VIC_ENABLE | VIC_TIMER0;
>
> ---------------------------

This will not work.

>
>  >If you want to keep your exception vectors in the flash, then simply use
> arm_exc_interrupt >(on 4.10) or _ARMV4_Exception_interrupt (on 4.11) as the
> entry point for the interrupt >exception.
>
> Do you mean passing arm_exc_interrupt as the handler into
> rtems_interrupt_handler_install()  ? that still gives an unhandled IRQ
> exception, probably because there is no handler installed in 0x18.

No, the normal sequence is this:

1. Interrupt event
2. CPU calls _ARMV4_Exception_interrupt via exception table
3. This calls bsp_interrupt_dispatch (defined in the BSP)
4. This calls the handler installed via rtems_interrupt_handler_install()

-- 
Sebastian Huber, embedded brains GmbH

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