PowerPC BSP mvme5500 and hardfloat.

[Greg Menke]

If in hard-float gcc is free to use fpu registers as general pupose, if 
soft-float then no fp registers are used.  Many functions in newlib etc 
(particularly the printf family) use fp registers, or even initialize 
local fp vars and so have a floating point "presence".  If you really 
need soft-float (eg no fpu) then you have to build the entire toolchain; 
cross-compiler, newlib and rtems all with soft-float.  Essentially, its 
tricky to have a mix of floating point and integer only tasks on the 
ppc, so its easies to make all tasks FP or everything soft-float.

Greg



On 12/12/2013 10:44 AM, Kate Feng wrote:
> Hi Joel,
>
>      I understood what you tried to point out about the surprise from the
> compiler.  The ISR is supposed to be written as short as possible
> to the point that only a few hardware registers are needed to be
> programmed. All the non-essential stuff (e.g. a = b; where a, b are
> struct timespec) can be done via the rtems_event_send(), which is
> implemented outside the ISR.  Look at the BSP code in GT64260eth_isr() of
> network/if_100MHz/GT64260eth.c and i82544EI_isr() of
> network/if_1GHz/if_wm.c.  Did you see that any surprise could be
> triggered by the modern compiler ?   If it does, then either the code
> should be rewritten or there is a bug in the compiler.
> BTW, which version of gcc compiler do you mean ?
>
> Cheers,
> Kate Feng
>

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