PowerPC BSP mvme5500 and hardfloat.

[Till Straumann]

I see. We should bite the bullet and save/restore volatile FP registers
across exceptions. Honestly, I thought we had added this but apparently
we didn't. Hadn't looked at this code in a while.

OTOH, I'm pretty sure that the FPU is disabled during PPC exception handling
so you should be alerted to the compiler playing tricks.

-T.

On 12/12/2013 10:53 AM, Matt Wette wrote:
>
> On Dec 12, 2013, at 9:18 AM, Till Straumann 
> <strauman at slac.stanford.edu <mailto:strauman at slac.stanford.edu>> wrote:
>
>> BTW: I have not, with recent gcc, seen implicit use of the FPU.
>>
>> - Till
>
> on ppc stfd = store float double
>
> mwette$ cat isr.c
> struct ts { int s, f; };
>
> extern struct ts clktim;
>
> extern volatile int *sec, *frac;
>
> void isr() {
> struct ts a, b;
> a.s = -1;
> do {
>   b = a;
>   a.s = *sec;
>   a.f = *frac;
> } while (a.s != b.s);
> /* oops move a to clktim */
> }
>
> mwette$ powerpc-rtems4.11-gcc -S isr.c
>
> mwette$ cat isr.s
>         .file   "isr.c"
>         .section        ".text"
>         .align 2
>         .globl isr
>         .type   isr, @function
> isr:
>         stwu 1,-32(1)
>         stw 31,28(1)
>         mr 31,1
>         li 9,-1
>         stw 9,8(31)
> .L2:
>         lfd 0,8(31)
>         stfd 0,16(31)
>         lis 9,sec at ha
>         lwz 9,sec at l(9)
>         lwz 9,0(9)
>         stw 9,8(31)
>         lis 9,frac at ha
>         lwz 9,frac at l(9)
>         lwz 9,0(9)
>         stw 9,12(31)
> lwz 10,8(31)
> lwz 9,16(31)
> cmpw 7,10,9
> bne 7,.L2
> addi 11,31,32
> lwz 31,-4(11)
> mr 1,11
> blr
> .sizeisr, .-isr
> .ident"GCC: (GNU) 4.8.2 20131016 (RTEMS 
> gcc-4.8.2-3.el6/newlib-1.20.0-29.el6)"
>

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/users/attachments/20131212/28252ff7/attachment-0001.html>