ARM (Thumb Mode) _CPU_Context_switch_arm

[Matthew J Fletcher]

Hi,

r2 is 0x13 before the msr, so I guess new_level must have been 0.
On 25 Feb 2013 15:02, "Sebastian Huber" <sebastian.huber at embedded-brains.de>
wrote:

> On 02/25/2013 03:15 PM, Matthew J Fletcher wrote:
>
>> Sebastian,
>>
>> The _Thread_Heir->Registers are ok into the _Context_Switch() call, sp
>> and lr
>> both sensible.
>>
>> At the 'mrs r2, cpsr' line sp is 0x40001b2c (rubbish) and pc sensible.
>>
>> In _restore, after the 'ldmia r1, ...' instruction the sp and lr are
>> loaded
>> with the correct values from _Thread_Heir->Registers.
>>
>> Its the 'msr cpsr, r2' messes up the sp and lr
>>
>
> Ok, if you load undefined values into the CPSR, then a lot of things may
> happen.  What is the value of r2 before the msr?  It should be 0x13.
>
> I think there is a bug in
>
> void _CPU_Context_Initialize(
>   Context_Control *the_context,
>   void *stack_area_begin,
>   size_t stack_area_size,
>   uint32_t new_level,
>   void (*entry_point)( void ),
>   bool is_fp
> )
> {
>   the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
>   the_context->register_lr = (uint32_t) entry_point;
>   the_context->register_cpsr = new_level | arm_cpu_mode;
> }
>
> if new_level != 0.  Is this the case here?
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-**brains.de<sebastian.huber at embedded-brains.de>
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>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
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