ARM (Thumb Mode) _CPU_Context_switch_arm
sebastian.huber at embedded-brains.de
Mon Feb 25 16:52:45 UTC 2013
On 02/25/2013 05:47 PM, Matthew J Fletcher wrote:
> r2 is 0x13 before the msr, so I guess new_level must have been 0.
> On 25 Feb 2013 15:02, "Sebastian Huber" <sebastian.huber at embedded-brains.de
> <mailto:sebastian.huber at embedded-brains.de>> wrote:
> On 02/25/2013 03:15 PM, Matthew J Fletcher wrote:
> The _Thread_Heir->Registers are ok into the _Context_Switch() call, sp
> and lr
> both sensible.
> At the 'mrs r2, cpsr' line sp is 0x40001b2c (rubbish) and pc sensible.
> In _restore, after the 'ldmia r1, ...' instruction the sp and lr are loaded
> with the correct values from _Thread_Heir->Registers.
> Its the 'msr cpsr, r2' messes up the sp and lr
> Ok, if you load undefined values into the CPSR, then a lot of things may
> happen. What is the value of r2 before the msr? It should be 0x13.
Ok, then maybe the mode in the BSP execution context is wrong. During
_Context_Switch() no mode change must happen. What is the CPSR before the msr?
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