Why RTEMS timeslice is not as configured.

[Fernando Nicodemos]

See answers bellow, in the text body.

*Fernando G. Nicodemos*
*Diretor de Pesquisa e Desenvolvimento

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2013/7/9 Joel Sherrill <joel.sherrill at oarcorp.com>

>  On 7/8/2013 2:59 PM, Fernando Nicodemos wrote:
>
>  Dears,
>
>  I configured 4 equal Tasks in RTEMS and the table as follows:
>
> rtems_task_create(
> Task_name[ 0 ],
> 2,
> RTEMS_MINIMUM_STACK_SIZE * 2,
> RTEMS_PREEMPT | RTEMS_TIMESLICE | RTEMS_ASR | RTEMS_INTERRUPT_LEVEL(0),
> RTEMS_GLOBAL,
> &Task_id[ 0 ]
> );
>
>  They will operate in round-robin.
>
>  #define CONFIGURE_MICROSECONDS_PER_TICK 10000
>  #define CONFIGURE_TICKS_PER_TIME_SLICE 50
>
>  The result should show a timeslice of 500 milisseconds, but what i see
> in osciloscope is more then 500ms, exactly 834ms. This code is running in a
> ERC32 development kit from Atmel.
>
>   Where are the pins being written in the code to measure this?
>

FER-> ERC32 GPIO pins are written. Each GPIO pin 4-7 is alocated to one
task. See task code bellow (this code is the same for the 4 tasks, except
for the respective GPIO):
/**********************
 * RTEMS TASK 1
 */
rtems_task Task1(
  rtems_task_argument unused
)
{
  volatile uint32_t task1_wait_count = 2;
  /**********************
   * Generate a square output on GPIO4
   * Manual loop-striping was applied for optimization
   */
  for(;;)
  {
    SET(GPIO4);
    WAIT(task1_wait_count);
    CLR(GPIO4_7);
    WAIT(task1_wait_count);
  }
}
Macros are:
#define SET(gpio) ( *((volatile uint32_t *)ERC32_GPIDATR_ADDR) |= gpio )
#define CLR(gpio) ( *((volatile uint32_t *)ERC32_GPIDATR_ADDR) &= ~gpio )
#define WAIT(count) \
    { \
      volatile uint32_t i; \
      for (i = 1; i == count; i++) { }; \
    }

#else


>   Any ideas what is missing for this extra time?
>
>   What speed is the erc32?
>
> I am curious if the assumed CPU speed is different from your actual
> board.
>

FER-> I did not change the default board values. I did not make any
register configuration on core or system clocks. CPU is TSC695F wich leads
a maximum 25MHz frequency. The board has two oscilators. One is 3.6864MHz
and the other is 24MHz. So the CPU is running at 24MHz and sysclk is 12MHz
(i measured in the sysclk pin and it is really 12MHz - remember that in
ERC32 sysclk is automatically divided by 2).



>   Thanks,
>
>  *Fernando G. Nicodemos*
>
>
>
> --
> Joel Sherrill, Ph.D.             Director of Research & Development joel.sherrill at OARcorp.com        On-Line Applications Research
> Ask me about RTEMS: a free RTOS  Huntsville AL 35805
> Support Available                (256) 722-9985
>
>
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