PC386 Clock Tick Driver

[SAeeD]

> There are buggy implementations of this but in this case, my guess is
> that the clock interrupts are occurring faster than they can be effectively
> cleared. Could be nesting interrupts, not clearing before another one, etc.
>
So if I understand correctly, this bug relates to implementation of pc386
BSP, right? Because on a 3.3 GHz Pentium PC we have enough time to clear
the tick interrupt even with 10 us for each tick. I may recall that we had
no problem with 10 us tick on LPC3250.
And another question: does pc386 use TSC (when available) in order to
generate tick interrupts at each MICROSECONDS_PER_TICK?
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