NIOS2 ISR Handler with shadow registers

[Kirspel, Kevin]

I have been trying to get RTEMS up and running with a Altera NIOS II processor with external VIC and shadows registers (non preemptive mode).  I see that the current head has ISR support for the NIOS external interrupt controller but I think it is broken.  There is a reference to a variable called "_Nios2_ISR_Status_interrupts_disabled" but I can't find its declaration.   It doesn't seemed to exist.

I took a stab at writing my own based off the ISR routines in score/cpu/nios2 but it fails sometimes when processing interrupts from the console.  After booting up, I can leave the system running without issue.  I can press enter periodically within the shell and the system is always alive.  If a repeatedly type "help" in the shell, I will eventually crash with the system stuck in bsp fatal error (However, nothing is printed on the console).  I think this may have to do with the call to _Thread_Dispatch within the ISR routine.  I have tried various means of calling _Thread_Dispatch from the ISR code (within the ISR itself to outside the ISR like ISR_Dispatch) but I always get the same result.  Has anyone succeeded in getting the NIOS2 working with the external interrupt controller for the latest head?  If so, could you share the ISR and BSP code with me?

Kevin Kirspel
Senior Research Engineer
Opti Medical
235 Hembree Park Drive
Roswell GA 30076
Tel: (770)-510-4444 ext. 81642
Direct: (770)-688-1642
Fax: (770)-510-4445

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