NIOS2 ISR Handler with shadow registers

[Sebastian Huber]

Hello Kevin,

On 2013-11-25 22:05, Kirspel, Kevin wrote:
> I have been trying to get RTEMS up and running with a Altera NIOS II processor
> with external VIC and shadows registers (non preemptive mode).  I see that the
> current head has ISR support for the NIOS external interrupt controller but I
> think it is broken.  There is a reference to a variable called
> “_Nios2_ISR_Status_interrupts_disabled” but I can’t find its declaration.   It
> doesn’t seemed to exist.

the support for external VIC works well.  You have to provide something like 
this in your BSP:

static void set_isr_status_symbols(void)
{
   __asm__ volatile (
     ".globl _Nios2_ISR_Status_mask\n"
     ".globl _Nios2_ISR_Status_bits\n"
     ".globl _Nios2_ISR_Status_interrupts_disabled\n"
     ".set _Nios2_ISR_Status_mask, "
       __XSTRING(NIOS2_ISR_STATUS_MASK_EIC_IL) "\n"
     ".set _Nios2_ISR_Status_bits, "
       __XSTRING(INTERRUPT_DISABLE_IL_BITS) "\n"
     ".set _Nios2_ISR_Status_interrupts_disabled, "
       __XSTRING(INTERRUPT_DISABLE_IL_BITS | NIOS2_STATUS_PIE) "\n"
   );
}

Our BSPs are currently not in the tree since it they are automatically 
generated from the design files.

-- 
Sebastian Huber, embedded brains GmbH

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