RTEMS & Altera QSYS

[saro]

Hi 2 all,
Anyone had experience with RTEMS & NIOS on Altera devices ?
My question is: there is the way to integrate the design flow of an application development in RTEMS environment in the Altera design flow that provide QSys for generate the BSP for the generated system? or I have to generate every time the same hardware (as in the current BSP provided in the RTEMS release), write the application and then create the image for the FPGA?
thank you for your consideration,

regards,

RC