Access PL within Zynq through rtems

[Chris Johns]

On 17/05/2016 22:44, xuelin.tian at qkmtech.com wrote:
> Dear all,
> I encountered an issue recently, about controlling and reading
> from/writing to PL within Zynq via rtems application. I've built up an
> IP core, and programmed FPGA, it all went well. The address assigned to
> this IP core starts from, for example, 0x43c0_0000 to 0x43c0_ffff. If I
> wanted to control this, I just wrote some value to the above address,
> like 0x43c0_0000, 0x43c0_0004 and so on. Unfortunatelly, it did not
> work. By the way, it all went well in bare metal application.

If you mean the Xilinx SDK, that tool opens the whole address space up 
and I do not know if any of the caches are enabled.

> First, it generates an Abort exception. I figured out that I need to
> modify the comfiguration in *.../xilinx-zynq/startup/bspstartmmu.c*, to
> assign a new section in *zynq_mmu_config_table[]*.
> After that, it does not generate Abort exception, but I still can not
> control the PL.

I add a file to my applications that override the default build with the 
BSP. The contents is:

#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION

#include <bsp.h>
#include <bsp/start.h>
#include <bsp/arm-gic-irq.h>
#include <bsp/arm-cp15-start.h>
#include <bsp/arm-a9mpcore-start.h>

#ifdef ARMV7_CP15_START_DEFAULT_SECTIONS

BSP_START_DATA_SECTION static const arm_cp15_start_section_config
zynq_mmu_config_table[] = {
   ARMV7_CP15_START_DEFAULT_SECTIONS,
   {
     .begin = 0xe0000000U,
     .end   = 0xe0200000U,
     .flags = ARMV7_MMU_DEVICE
   }, {
     .begin = 0xf8000000U,
     .end   = 0xf9000000U,
     .flags = ARMV7_MMU_DEVICE
   }, {
     .begin = 0x40000000U,
     .end   = 0xc0000000U,
     .flags = ARMV7_MMU_DEVICE
   }, {
     .begin = 0x00100000U,
     .end   = 0x00400000U,
     .flags = ARMV7_MMU_DEVICE
   }, {
     .begin = 0xfffc0000u,
     .end   = 0xffffffffu,
     .flags = ARMV7_MMU_DEVICE
   }
};

BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void)
{
   uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
     ARM_CP15_CTRL_A,
     ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
   );

   arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
     ctrl,
     (uint32_t *) bsp_translation_table_base,
     ARM_MMU_DEFAULT_CLIENT_DOMAIN,
     &zynq_mmu_config_table[0],
     RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
   );
}

Chris