Simple question about RTL

Chris Johns chrisj at
Tue Sep 6 05:12:53 UTC 2016

Hi Tim and Pavel,

Thank you for the patches and testing. I will have a chat to Joel 
tomorrow about the patches and what we will do. If Joel agrees I may 
test and push the patches.

FYI I am currently looking at #2767 which is reported against 4.11 and a 
zynq so there is real interest on these patches ending up on 4.11.


On 06/09/2016 13:48, xuelin.tian at wrote:
> Hi Pavel,
> it works on my Zynq platform. Thankyou. I will go through the patches
> you posted.
> ------------------------------------------------------------------------
> Best wishes,
> Tim Tian
> xuelin.tian at
>     *From:* Pavel Pisa <mailto:ppisa4lists at>
>     *Date:* 2016-09-06 08:52
>     *To:* Chris Johns <mailto:chrisj at>
>     *CC:* xuelin.tian at <mailto:xuelin.tian at>;
>     users at <mailto:users at>
>     *Subject:* Re: Simple question about RTL
>     Hello Chris,
>     On Tuesday 06 of September 2016 01:52:05 Chris Johns wrote:
>      > On 05/09/2016 23:52, Pavel Pisa wrote:
>      > > I can prepare 4.11 branch on my GitHub account and if it is
>     confirmed,
>      > > that it works, then discussion about inclusion to yet
>     unreleased 4.11
>      > > should start. Other option is to release 4.11 and correct these for
>      > > 4.11.1.
>      >
>      > Please post the patches to devel for review. If they are fixing
>     issues
>      > in libdl I am ok with pushing to 4.11 before 4.11.0 is released.
>     I have spent huge amount today on shuffling patches but I have
>     not 4.11 booting on RPi2 yet. Problem is that code before branching
>     cannot run with actual firmware and U-boot versions. Hypervisor
>     boot is required.
>     Fixing RTL on Zynq requires to at least these patches which I have
>     listed in previous e-mails. Problem is, that there are dependencies
>     on my previous generic cache management patches. The case of Zynq
>     and Altera is not so bad, cache manager has included specific support
>     for them. But there is significant problem that almost all other
>     ARM BSPs (including Raspberry Pi) with cache have not selected
>     any cache operations in the past due to the condition in generic
>     cache support. To do that functional requires backport another
>     patches.
>     So I have ended with something like 25 patches
>     and debugging still why RPi2 does not boot.
>     I consider patches marked by "Z" as critical for RTL on Zynq.
>     Patches marked by "O" as optional/may be required by dependencies
>     or Zynq boot. The rest is mostly RPi stuff and fix for rest of ARMs
>        ae58402 bsps/arm: CP15 support for flush prefetch buffer and
>     table base control.
>        bbfee81 arm/raspberrypi: ensure that RTEMS application image can
>     be started by U-boot.
>        211ff5f arm/score and shared: define ARM hypervisor mode and
>     alternate vector table base access.
>     Z 1d640b1 score/arm: Ensure that copile time alignment is 64 bytes
>     for Cortex-A multilib.
>     Z 52d170a rtems+bsps/cache: Define cache manager operations for code
>     synchronization and maximal alignment.
>     Z ada6141 bsp/arm: Report correct maximal cache line length for ARM
>     Cortex-A + L2C-310.
>        24b045a bsps/arm: Change code to explicit selection of cache
>     implementation for ARM BSPs.
>        303a314 bsps/arm: basic on core cache support changed to use l1
>     functions.
>     Z 07ed33e libdl/rtl-obj.c: synchronize cache after code relocation.
>        12b2428 bsps/arm: do not disable MMU during translation table
>     management operations.
>        65739ba arm/bsps: CP15 and basic cache support entire cache clean
>     for more architecture variants now.
>        1b7c3cc arm/raspberrypi: use cache manager operations to
>     flush/invalidate all cache levels.
>     O c9fb885 arm/xilinx_zynq: ensure that cache is cleaned and MMU
>     disabled when initialization starts.
>        0504357 bsps/arm: use defines for cache type register format field.
>     O 531ac9b bsps/arm: remove lock in
>     arm_cp15_set_translation_table_entries().
>        6519972 bsps/arm: reorganize CP15 code to allow clean and
>     invalidate ARMv7 cache by level.
>        8904d09 bsps/arm: Fix basic cache support for SMP
>        4192010 libbsp/arm: Add the TTB table to the default MMU set up
>     as read/write.
>        22f5808 libbsp/arm: Fix ARM BSPs missing the
>     bsp_translation_table_end symbol.
>        7d143ff bsps/arm: Support recent bootloaders starting kernel in
>     HYP mode
>        e94cc10 arm/raspberrypi: Enable HYP to SVC switch for this BSP.
>        fe85ebd arm/raspberrypi: reorder and update MMU config table to
>     nor force RW section later to RO.
>        08374dc arm/raspberrypi: ensure that correct RPI_PERIPHERAL_BASE
>     is provided by raspberrypi.h
>        cc6e7ae arm/raspberrypi: remove duplicate setup of IRQ handler in
>     the main ARM exception table.
>        4f362eb arm/raspberrypi: change interrupt dispatch and enable to
>     generic vector id based approach.
>     I am not sure if that growing has chance to be acceptable for 4.11.
>     I have not even tested Zynq build. I do not have board there at home.
>     Incremental testing on Zynq has advantage that it runs and change
>     breaking
>     code is immediately seen.
>     All patches are backports from mainline, some RPi ones have removed
>     touching
>     these files and subsystems which are not present on 4.11. So generally,
>     they should be OK. But ....
>     Best wishes,
>                      Pavel

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