Porting RTEMS on Arm Cortex-M1

[Pavel Pisa]

Hello all,

Sebastian Huber would/could answer in more details.
I try to shed some light

On Saturday 22 of April 2017 13:47:49 Daniel Jones wrote:
> Hello Sir
>
> Thank you for your response. Memory is no problem. I am starting with
> armv7-m bsp. But still have some question left and I hope someone could
> help. What about the rtems start code, context switch, exception handle and
> other similar files which I have found for armv4 and armv7-m? Do I have to
> write these supports for armv6-m? As armv6-m and armv7-m are not that much
> different, in which files I have to make some changes? Any sort of help is
> appreciated.

The Cortex-M1 is the ARM IP core targetting FPGA where Soft Core is used.
Cortex-M0 is matching design for the on silicon implementation.

Main difference of Cortex-M0/1 when compared to Cortex-M3/4 is that
the instruction set is really limited subset (armv6-m) of full featured
THUMB2 (armv7-m).

If you use some Cortex-M3/4 BSP as the reference (stm32f4 for example)

  rtems/c/src/lib/libbsp/arm/stm32f4/make/custom/stm32f4.cfg

then for C code the reduction of used set is a matter of C compiler
flags

  rtems/c/src/lib/libbsp/arm/newbspM1/make/custom/newbspM1.cfg

RTEMS_CPU = arm

CPU_CFLAGS = -march=armv6-m -mthumb

Bigger problem is that startup code in

rtems/c/src/lib/libbsp/arm/shared/start/start.S

is implemented only for ARM_MULTILIB_ARCH_V4 and ARM_MULTILIB_ARCH_V7M

The armv6-m instruction set support same memory barrier instructions
as armv7-m (DMB, DSB, ISB) but does not include conditional instructions
for compare and swap and restartable/preemptible[*] atomic operations
constructions (load and reserve, conditional store).
* Nice oxymoron 

 CLREX, LDREX, LDREXB, LDREXH, STREX, STREXB, STREXH 

So I am not sure if regular newlib and RTEMS library atomic support
would work or require changes. These has to be solved by interrupt
disable, then operation and finally interrupt enable.
For sure, that does not work on SMP, so Cortex-M0/1 cannot be used
for regular SMP.

The Cortex-M3/4 is equipped by NVIC usually. But M0/1 can be used
without it, so interrupt processing requires to check and dispatch 
interrupt/exception source from single handler under software control.

So there are more places which has to be analyzed and extended
for Cortex-M0/1 variant.

Best wishes,

Pavel