Cache routines working with a processor set?

[Matthew J Fletcher]

Hi Sebastian,

It was a tricky bit of code that dealt with the transition from XIP
operation, to running from RAM to write to the same NOR flash chip we where
XIP on previously.

On Wed, 14 Nov 2018 at 08:10, Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:

> Hello Matthew,
>
> On 14/11/2018 09:05, Matthew J Fletcher wrote:
> > None of the above, but we used to
> > use rtems_cache_invalidate_entire_instruction
> > / rtems_cache_invalidate_multiple_data_lines but now use arch specific
> > methods instead.
>
> these functions are fine. I only want to get rid of the functions which
> operate on a processor set.
>
> Why do you use custom functions now instead of the one provided by RTEMS?
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-brains.de
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
>

-- 

regards
---
Matthew J Fletcher
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