device-tree example for altera-cyclone-v bsp

[Christian Spindeldreier]

Hello Sebastian,

your changes work for us as well, now we are able to run a clean version 
of the altcycv_devkit bsp on our DE10 board.

Extending the BSP documentation helps a lot, but maybe you can add the 
definition of the u-boot 'loadfdt' variable, does not seem to be defined 
in any socfpga configuration (e.g. socfpga_cyclone5_socdk) in the 
upstream u-boot repo, but some other board configurations:

http://git.denx.de/?p=u-boot.git;a=blob;f=include/configs/socfpga_cyclone5_socdk.h

http://git.denx.de/?p=u-boot.git;a=blob;f=include/configs/socfpga_common.h

Kind regards,

Christian


On 18.02.19 09:17, Sebastian Huber wrote:
> Hello Christian,
>
> I added some basic BSP documentation:
>
> https://docs.rtems.org/branches/master/user/bsps/bsps-arm.html#altera-cyclone-v 
>
>
> On 14/02/2019 13:54, Christian Spindeldreier wrote:
>>
>> we had to change the BSP_ARM_A9MPCORE_PERIPHCLK frequency to 100 MHz 
>> as this is the frequency the L4 MP clock is set by Qsys or the SPL, 
>> respectively. This meant adding a second board to the 
>> altera-cyclone-v bsp differing only by this configuration option. 
>> Adapting the configuration as described enabled the upstream RTEMS-5 
>> version to boot on the Terasic-DE10 Standard Board 
>> (http://de10-standard.terasic.com).
>
> I changed the BSP initialization to use the device tree for this clock:
>
> https://git.rtems.org/rtems/commit/?id=af80b0a3406bef73dc6550421947a981c939da27 
>
>
> It would be nice if you could test this. Please remove the 
> "BSP_ARM_A9MPCORE_PERIPHCLK=100000000" from the configure command line.
>
>>
>> U-Boot itself contains a device-tree of the board it is running on, 
>> but i missed the u-boot command handing over the u-boot device-tree 
>> to rtems which expects the device-tree address in R6 on startup. If 
>> there is anything like this i am pleased on any information on it.
>
> The device tree provided by U-Boot is in r2.
>
-- 
Dipl.-Ing. Christian Spindeldreier
Leibniz University Hannover (LUH)
Institute of Microelectronic Systems
Architectures and Systems Group
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