Corrupted test marker with u-boot and zynq
chrisj at rtems.org
Thu Aug 20 03:43:28 UTC 2020
On 19/8/20 5:30 pm, Jan.Sommer at dlr.de wrote:
>> -----Original Message-----
>> From: Chris Johns [mailto:chrisj at rtems.org]
>> Sent: Wednesday, August 19, 2020 1:25 AM
>> To: Sommer, Jan; joel at rtems.org
>> I assume you are using the default baudrate of 115200?
>> Is this custom hardware?
> It's a SoM from Trenz (e.g. here: https://shop.trenz-electronic.de/en/TE0715-04-15-1I-SoC-Module-with-Xilinx-Zynq-XC7Z015-1CLG485I-1-GByte-DDR3L-4-x-5-cm) which sits on the 0706 Carrier-board.
> I compiled rtems with the following to set the clock values in line with vivado:
> ../rtems-5.0.0-m2006-2/configure --target=arm-rtems5 --prefix=~/rtems/bsps/5/arm --disable-networking --enable-rtemsbsp=xilinx_zynq_zedboard --enable-cxx --enable-posix ZYNQ_CLOCK_UART=100000000 BSP_ARM_A9MPCORE_PERIPHCLK=333333333U ZYNQ_CLOCK_CPU_1X=111111111U BSP_CONSOLE_MINOR=0 --enable-tests
I use weak functions to handle the clocks.
>>> Would this be a solution which could be accepted as a patch?
>> I do not see any harm in the change however I would like to know what the
>> difference between your set up and mine is. Your output is missing ...
>> ## Transferring control to RTEMS (at address 00104000) ...
> Ah, yes.
> I just tried with a bare metal hello_world from Xilinx and there this line appears, but not when I load rtems applications.
> That's weird.
> We have u-boot compiled from the Xilinx repositories: U-Boot 2019.01 (Jul 16 2020 - 14:44:10 +0000) Xilinx Zynq ZC702
I use the u-boot repo and not the vendors.
I check the TRM and the string is about 60 characters and the FIFO is 64 bytes
so it is possible the whole string is in the buffer.
Please create a patch and send to devel at rtems.org.
More information about the users