Sebastian Huber sebastian.huber at embedded-brains.de
Tue Jun 2 08:20:04 UTC 2020

On 02/06/2020 10:06, Schweikhardt, Jens (TSPCE3-TL4) wrote:

> we are using a customized RV32IMAF CPU with RTEMS and need to handle interrupts.
> I'm new to configuring low level things such as this and need a bit of guidance where goes what.
> I build using the RTEMS source builder.
> It appears that for RISC-V a value for CPU_SIMPLE_VECTORED_INTERRUPTS is not defined, and thus treated as FALSE.
> Other CPUs, such as sparc, define it in cpukit/score/cpu/sparc/include/rtems/score/cpu.h.
This CPU option is only defined to TRUE on legacy architectures.
> Q: Should I simply add a macro definition to cpukit/score/cpu/riscv/include/rtems/score/cpu.h or is there
> a better (proper) way, say, passing it as an argument to sb-set-builder or sb-bootstrap or the configure script building the bsps?
No, please keep this value as is (FALSE). Use 
rtems_interrupt_handler_install() to install interrupts on RISC-V. For 
the interrupt controller support code see the existing BSPs.

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