change log for rtems (2010-05-10)
rtems-vc at rtems.org
rtems-vc at rtems.org
Mon May 10 17:11:06 UTC 2010
*joel*:
2010-05-10 Joel Sherrill <joel.sherrilL at OARcorp.com>
* Makefile.am, cpu_asm.S, avr/boot.h, avr/common.h, avr/crc16.h,
avr/delay.h, avr/eeprom.h, avr/fuse.h, avr/interrupt.h, avr/io.h,
avr/io1200.h, avr/io2313.h, avr/io2323.h, avr/io2333.h, avr/io2343.h,
avr/io43u32x.h, avr/io43u35x.h, avr/io4414.h, avr/io4433.h,
avr/io4434.h, avr/io76c711.h, avr/io8515.h, avr/io8534.h,
avr/io8535.h, avr/io86r401.h, avr/io90pwm1.h, avr/io90pwm216.h,
avr/io90pwm2b.h, avr/io90pwm316.h, avr/io90pwm3b.h, avr/io90pwm81.h,
avr/io90pwmx.h, avr/io90scr100.h, avr/ioa6289.h, avr/ioat94k.h,
avr/iocan128.h, avr/iocan32.h, avr/iocan64.h, avr/iocanxx.h,
avr/iom103.h, avr/iom128.h, avr/iom1280.h, avr/iom1281.h,
avr/iom1284p.h, avr/iom128rfa1.h, avr/iom16.h, avr/iom161.h,
avr/iom162.h, avr/iom163.h, avr/iom164.h, avr/iom165.h,
avr/iom165p.h, avr/iom168.h, avr/iom168p.h, avr/iom169.h,
avr/iom169p.h, avr/iom16hva.h, avr/iom16m1.h, avr/iom16u4.h,
avr/iom2560.h, avr/iom2561.h, avr/iom32.h, avr/iom323.h,
avr/iom324.h, avr/iom325.h, avr/iom3250.h, avr/iom328p.h,
avr/iom329.h, avr/iom3290.h, avr/iom32c1.h, avr/iom32hvb.h,
avr/iom32m1.h, avr/iom32u4.h, avr/iom32u6.h, avr/iom406.h,
avr/iom48.h, avr/iom48p.h, avr/iom64.h, avr/iom640.h, avr/iom644.h,
avr/iom645.h, avr/iom6450.h, avr/iom649.h, avr/iom6490.h,
avr/iom64c1.h, avr/iom64m1.h, avr/iom8.h, avr/iom8515.h,
avr/iom8535.h, avr/iom88.h, avr/iom88p.h, avr/iom8hva.h, avr/iomx8.h,
avr/iomxx0_1.h, avr/iomxx4.h, avr/iomxxhva.h, avr/iotn11.h,
avr/iotn12.h, avr/iotn13.h, avr/iotn13a.h, avr/iotn15.h,
avr/iotn167.h, avr/iotn22.h, avr/iotn2313.h, avr/iotn24.h,
avr/iotn25.h, avr/iotn26.h, avr/iotn261.h, avr/iotn28.h,
avr/iotn43u.h, avr/iotn44.h, avr/iotn45.h, avr/iotn461.h,
avr/iotn48.h, avr/iotn84.h, avr/iotn85.h, avr/iotn861.h,
avr/iotn87.h, avr/iotn88.h, avr/iotnx4.h, avr/iotnx5.h,
avr/iotnx61.h, avr/iousb1286.h, avr/iousb1287.h, avr/iousb162.h,
avr/iousb646.h, avr/iousb647.h, avr/iousb82.h, avr/iousbxx2.h,
avr/iousbxx6_7.h, avr/iox128a1.h, avr/iox128a3.h, avr/iox16a4.h,
avr/iox16d4.h, avr/iox256a3.h, avr/iox256a3b.h, avr/iox32a4.h,
avr/iox32d4.h, avr/iox64a1.h, avr/iox64a3.h, avr/lock.h,
avr/parity.h, avr/pgmspace.h, avr/portpins.h, avr/power.h,
avr/sfr_defs.h, avr/signal.h, avr/sleep.h, avr/version.h, avr/wdt.h,
rtems/asm.h, rtems/score/cpu.h: Update to avr .h files from avr-libc
1.6.8. Tinker with code and includes to eliminate warnings. Now
builds multilib.
* avr/iom169pa.h, avr/iom16a.h, avr/iom16hva2.h, avr/iom16hvb.h,
avr/iom16u2.h, avr/iom324pa.h, avr/iom32u2.h, avr/iom644p.h,
avr/iom644pa.h, avr/iom649p.h, avr/iom64hve.h, avr/iom88pa.h,
avr/iom8u2.h, avr/iotn2313a.h, avr/iotn24a.h, avr/iotn261a.h,
avr/iotn4313.h, avr/iotn44a.h, avr/iotn461a.h, avr/iotn861a.h,
avr/iox128d3.h, avr/iox192a3.h, avr/iox192d3.h, avr/iox256d3.h,
avr/iox64d3.h, avr/signature.h: New files.
M 1.47 cpukit/score/cpu/avr/ChangeLog
M 1.10 cpukit/score/cpu/avr/Makefile.am
M 1.3 cpukit/score/cpu/avr/avr/boot.h
M 1.3 cpukit/score/cpu/avr/avr/common.h
M 1.2 cpukit/score/cpu/avr/avr/crc16.h
M 1.2 cpukit/score/cpu/avr/avr/delay.h
M 1.3 cpukit/score/cpu/avr/avr/eeprom.h
M 1.3 cpukit/score/cpu/avr/avr/fuse.h
M 1.3 cpukit/score/cpu/avr/avr/interrupt.h
M 1.3 cpukit/score/cpu/avr/avr/io.h
M 1.3 cpukit/score/cpu/avr/avr/io1200.h
M 1.3 cpukit/score/cpu/avr/avr/io2313.h
M 1.3 cpukit/score/cpu/avr/avr/io2323.h
M 1.3 cpukit/score/cpu/avr/avr/io2333.h
M 1.3 cpukit/score/cpu/avr/avr/io2343.h
M 1.3 cpukit/score/cpu/avr/avr/io43u32x.h
M 1.3 cpukit/score/cpu/avr/avr/io43u35x.h
M 1.3 cpukit/score/cpu/avr/avr/io4414.h
M 1.3 cpukit/score/cpu/avr/avr/io4433.h
M 1.3 cpukit/score/cpu/avr/avr/io4434.h
M 1.3 cpukit/score/cpu/avr/avr/io76c711.h
M 1.3 cpukit/score/cpu/avr/avr/io8515.h
M 1.3 cpukit/score/cpu/avr/avr/io8534.h
M 1.3 cpukit/score/cpu/avr/avr/io8535.h
M 1.3 cpukit/score/cpu/avr/avr/io86r401.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwm1.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwm216.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwm2b.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwm316.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwm3b.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwm81.h
M 1.3 cpukit/score/cpu/avr/avr/io90pwmx.h
M 1.3 cpukit/score/cpu/avr/avr/io90scr100.h
M 1.3 cpukit/score/cpu/avr/avr/ioa6289.h
M 1.3 cpukit/score/cpu/avr/avr/ioat94k.h
M 1.3 cpukit/score/cpu/avr/avr/iocan128.h
M 1.3 cpukit/score/cpu/avr/avr/iocan32.h
M 1.3 cpukit/score/cpu/avr/avr/iocan64.h
M 1.3 cpukit/score/cpu/avr/avr/iocanxx.h
M 1.3 cpukit/score/cpu/avr/avr/iom103.h
M 1.3 cpukit/score/cpu/avr/avr/iom128.h
M 1.3 cpukit/score/cpu/avr/avr/iom1280.h
M 1.3 cpukit/score/cpu/avr/avr/iom1281.h
M 1.2 cpukit/score/cpu/avr/avr/iom1284p.h
M 1.3 cpukit/score/cpu/avr/avr/iom128rfa1.h
M 1.3 cpukit/score/cpu/avr/avr/iom16.h
M 1.3 cpukit/score/cpu/avr/avr/iom161.h
M 1.3 cpukit/score/cpu/avr/avr/iom162.h
M 1.3 cpukit/score/cpu/avr/avr/iom163.h
M 1.3 cpukit/score/cpu/avr/avr/iom164.h
M 1.3 cpukit/score/cpu/avr/avr/iom165.h
M 1.3 cpukit/score/cpu/avr/avr/iom165p.h
M 1.3 cpukit/score/cpu/avr/avr/iom168.h
M 1.3 cpukit/score/cpu/avr/avr/iom168p.h
M 1.3 cpukit/score/cpu/avr/avr/iom169.h
M 1.3 cpukit/score/cpu/avr/avr/iom169p.h
A 1.1 cpukit/score/cpu/avr/avr/iom169pa.h
A 1.1 cpukit/score/cpu/avr/avr/iom16a.h
M 1.3 cpukit/score/cpu/avr/avr/iom16hva.h
A 1.1 cpukit/score/cpu/avr/avr/iom16hva2.h
A 1.1 cpukit/score/cpu/avr/avr/iom16hvb.h
M 1.3 cpukit/score/cpu/avr/avr/iom16m1.h
A 1.1 cpukit/score/cpu/avr/avr/iom16u2.h
M 1.3 cpukit/score/cpu/avr/avr/iom16u4.h
M 1.3 cpukit/score/cpu/avr/avr/iom2560.h
M 1.3 cpukit/score/cpu/avr/avr/iom2561.h
M 1.3 cpukit/score/cpu/avr/avr/iom32.h
M 1.3 cpukit/score/cpu/avr/avr/iom323.h
M 1.3 cpukit/score/cpu/avr/avr/iom324.h
A 1.1 cpukit/score/cpu/avr/avr/iom324pa.h
M 1.3 cpukit/score/cpu/avr/avr/iom325.h
M 1.3 cpukit/score/cpu/avr/avr/iom3250.h
M 1.3 cpukit/score/cpu/avr/avr/iom328p.h
M 1.3 cpukit/score/cpu/avr/avr/iom329.h
M 1.3 cpukit/score/cpu/avr/avr/iom3290.h
M 1.3 cpukit/score/cpu/avr/avr/iom32c1.h
M 1.3 cpukit/score/cpu/avr/avr/iom32hvb.h
M 1.3 cpukit/score/cpu/avr/avr/iom32m1.h
A 1.1 cpukit/score/cpu/avr/avr/iom32u2.h
M 1.3 cpukit/score/cpu/avr/avr/iom32u4.h
M 1.3 cpukit/score/cpu/avr/avr/iom32u6.h
M 1.3 cpukit/score/cpu/avr/avr/iom406.h
M 1.2 cpukit/score/cpu/avr/avr/iom48.h
M 1.3 cpukit/score/cpu/avr/avr/iom48p.h
M 1.3 cpukit/score/cpu/avr/avr/iom64.h
M 1.3 cpukit/score/cpu/avr/avr/iom640.h
M 1.3 cpukit/score/cpu/avr/avr/iom644.h
A 1.1 cpukit/score/cpu/avr/avr/iom644p.h
A 1.1 cpukit/score/cpu/avr/avr/iom644pa.h
M 1.3 cpukit/score/cpu/avr/avr/iom645.h
M 1.3 cpukit/score/cpu/avr/avr/iom6450.h
M 1.3 cpukit/score/cpu/avr/avr/iom649.h
M 1.3 cpukit/score/cpu/avr/avr/iom6490.h
A 1.1 cpukit/score/cpu/avr/avr/iom649p.h
M 1.3 cpukit/score/cpu/avr/avr/iom64c1.h
A 1.1 cpukit/score/cpu/avr/avr/iom64hve.h
M 1.3 cpukit/score/cpu/avr/avr/iom64m1.h
M 1.3 cpukit/score/cpu/avr/avr/iom8.h
M 1.3 cpukit/score/cpu/avr/avr/iom8515.h
M 1.3 cpukit/score/cpu/avr/avr/iom8535.h
M 1.3 cpukit/score/cpu/avr/avr/iom88.h
M 1.3 cpukit/score/cpu/avr/avr/iom88p.h
A 1.1 cpukit/score/cpu/avr/avr/iom88pa.h
M 1.3 cpukit/score/cpu/avr/avr/iom8hva.h
A 1.1 cpukit/score/cpu/avr/avr/iom8u2.h
M 1.3 cpukit/score/cpu/avr/avr/iomx8.h
M 1.3 cpukit/score/cpu/avr/avr/iomxx0_1.h
M 1.2 cpukit/score/cpu/avr/avr/iomxx4.h
M 1.3 cpukit/score/cpu/avr/avr/iomxxhva.h
M 1.3 cpukit/score/cpu/avr/avr/iotn11.h
M 1.3 cpukit/score/cpu/avr/avr/iotn12.h
M 1.3 cpukit/score/cpu/avr/avr/iotn13.h
M 1.3 cpukit/score/cpu/avr/avr/iotn13a.h
M 1.3 cpukit/score/cpu/avr/avr/iotn15.h
M 1.3 cpukit/score/cpu/avr/avr/iotn167.h
M 1.3 cpukit/score/cpu/avr/avr/iotn22.h
M 1.2 cpukit/score/cpu/avr/avr/iotn2313.h
A 1.1 cpukit/score/cpu/avr/avr/iotn2313a.h
M 1.2 cpukit/score/cpu/avr/avr/iotn24.h
A 1.1 cpukit/score/cpu/avr/avr/iotn24a.h
M 1.2 cpukit/score/cpu/avr/avr/iotn25.h
M 1.3 cpukit/score/cpu/avr/avr/iotn26.h
M 1.2 cpukit/score/cpu/avr/avr/iotn261.h
A 1.1 cpukit/score/cpu/avr/avr/iotn261a.h
M 1.3 cpukit/score/cpu/avr/avr/iotn28.h
A 1.1 cpukit/score/cpu/avr/avr/iotn4313.h
M 1.3 cpukit/score/cpu/avr/avr/iotn43u.h
M 1.2 cpukit/score/cpu/avr/avr/iotn44.h
A 1.1 cpukit/score/cpu/avr/avr/iotn44a.h
M 1.2 cpukit/score/cpu/avr/avr/iotn45.h
M 1.2 cpukit/score/cpu/avr/avr/iotn461.h
A 1.1 cpukit/score/cpu/avr/avr/iotn461a.h
M 1.3 cpukit/score/cpu/avr/avr/iotn48.h
M 1.2 cpukit/score/cpu/avr/avr/iotn84.h
M 1.2 cpukit/score/cpu/avr/avr/iotn85.h
M 1.2 cpukit/score/cpu/avr/avr/iotn861.h
A 1.1 cpukit/score/cpu/avr/avr/iotn861a.h
M 1.3 cpukit/score/cpu/avr/avr/iotn87.h
M 1.3 cpukit/score/cpu/avr/avr/iotn88.h
M 1.3 cpukit/score/cpu/avr/avr/iotnx4.h
M 1.3 cpukit/score/cpu/avr/avr/iotnx5.h
M 1.3 cpukit/score/cpu/avr/avr/iotnx61.h
M 1.3 cpukit/score/cpu/avr/avr/iousb1286.h
M 1.3 cpukit/score/cpu/avr/avr/iousb1287.h
M 1.3 cpukit/score/cpu/avr/avr/iousb162.h
M 1.3 cpukit/score/cpu/avr/avr/iousb646.h
M 1.3 cpukit/score/cpu/avr/avr/iousb647.h
M 1.3 cpukit/score/cpu/avr/avr/iousb82.h
M 1.3 cpukit/score/cpu/avr/avr/iousbxx2.h
M 1.3 cpukit/score/cpu/avr/avr/iousbxx6_7.h
M 1.3 cpukit/score/cpu/avr/avr/iox128a1.h
M 1.3 cpukit/score/cpu/avr/avr/iox128a3.h
A 1.1 cpukit/score/cpu/avr/avr/iox128d3.h
M 1.3 cpukit/score/cpu/avr/avr/iox16a4.h
M 1.3 cpukit/score/cpu/avr/avr/iox16d4.h
A 1.1 cpukit/score/cpu/avr/avr/iox192a3.h
A 1.1 cpukit/score/cpu/avr/avr/iox192d3.h
M 1.3 cpukit/score/cpu/avr/avr/iox256a3.h
M 1.3 cpukit/score/cpu/avr/avr/iox256a3b.h
A 1.1 cpukit/score/cpu/avr/avr/iox256d3.h
M 1.3 cpukit/score/cpu/avr/avr/iox32a4.h
M 1.3 cpukit/score/cpu/avr/avr/iox32d4.h
M 1.3 cpukit/score/cpu/avr/avr/iox64a1.h
M 1.3 cpukit/score/cpu/avr/avr/iox64a3.h
A 1.1 cpukit/score/cpu/avr/avr/iox64d3.h
M 1.3 cpukit/score/cpu/avr/avr/lock.h
M 1.2 cpukit/score/cpu/avr/avr/parity.h
M 1.3 cpukit/score/cpu/avr/avr/pgmspace.h
M 1.2 cpukit/score/cpu/avr/avr/portpins.h
M 1.3 cpukit/score/cpu/avr/avr/power.h
M 1.3 cpukit/score/cpu/avr/avr/sfr_defs.h
M 1.2 cpukit/score/cpu/avr/avr/signal.h
A 1.1 cpukit/score/cpu/avr/avr/signature.h
M 1.3 cpukit/score/cpu/avr/avr/sleep.h
M 1.2 cpukit/score/cpu/avr/avr/version.h
M 1.3 cpukit/score/cpu/avr/avr/wdt.h
M 1.9 cpukit/score/cpu/avr/cpu_asm.S
M 1.8 cpukit/score/cpu/avr/rtems/asm.h
M 1.25 cpukit/score/cpu/avr/rtems/score/cpu.h
diff -u rtems/cpukit/score/cpu/avr/ChangeLog:1.46 rtems/cpukit/score/cpu/avr/ChangeLog:1.47
--- rtems/cpukit/score/cpu/avr/ChangeLog:1.46 Sat Mar 27 10:01:24 2010
+++ rtems/cpukit/score/cpu/avr/ChangeLog Mon May 10 11:31:15 2010
@@ -1,3 +1,52 @@
+2010-05-10 Joel Sherrill <joel.sherrilL at OARcorp.com>
+
+ * Makefile.am, cpu_asm.S, avr/boot.h, avr/common.h, avr/crc16.h,
+ avr/delay.h, avr/eeprom.h, avr/fuse.h, avr/interrupt.h, avr/io.h,
+ avr/io1200.h, avr/io2313.h, avr/io2323.h, avr/io2333.h, avr/io2343.h,
+ avr/io43u32x.h, avr/io43u35x.h, avr/io4414.h, avr/io4433.h,
+ avr/io4434.h, avr/io76c711.h, avr/io8515.h, avr/io8534.h,
+ avr/io8535.h, avr/io86r401.h, avr/io90pwm1.h, avr/io90pwm216.h,
+ avr/io90pwm2b.h, avr/io90pwm316.h, avr/io90pwm3b.h, avr/io90pwm81.h,
+ avr/io90pwmx.h, avr/io90scr100.h, avr/ioa6289.h, avr/ioat94k.h,
+ avr/iocan128.h, avr/iocan32.h, avr/iocan64.h, avr/iocanxx.h,
+ avr/iom103.h, avr/iom128.h, avr/iom1280.h, avr/iom1281.h,
+ avr/iom1284p.h, avr/iom128rfa1.h, avr/iom16.h, avr/iom161.h,
+ avr/iom162.h, avr/iom163.h, avr/iom164.h, avr/iom165.h,
+ avr/iom165p.h, avr/iom168.h, avr/iom168p.h, avr/iom169.h,
+ avr/iom169p.h, avr/iom16hva.h, avr/iom16m1.h, avr/iom16u4.h,
+ avr/iom2560.h, avr/iom2561.h, avr/iom32.h, avr/iom323.h,
+ avr/iom324.h, avr/iom325.h, avr/iom3250.h, avr/iom328p.h,
+ avr/iom329.h, avr/iom3290.h, avr/iom32c1.h, avr/iom32hvb.h,
+ avr/iom32m1.h, avr/iom32u4.h, avr/iom32u6.h, avr/iom406.h,
+ avr/iom48.h, avr/iom48p.h, avr/iom64.h, avr/iom640.h, avr/iom644.h,
+ avr/iom645.h, avr/iom6450.h, avr/iom649.h, avr/iom6490.h,
+ avr/iom64c1.h, avr/iom64m1.h, avr/iom8.h, avr/iom8515.h,
+ avr/iom8535.h, avr/iom88.h, avr/iom88p.h, avr/iom8hva.h, avr/iomx8.h,
+ avr/iomxx0_1.h, avr/iomxx4.h, avr/iomxxhva.h, avr/iotn11.h,
+ avr/iotn12.h, avr/iotn13.h, avr/iotn13a.h, avr/iotn15.h,
+ avr/iotn167.h, avr/iotn22.h, avr/iotn2313.h, avr/iotn24.h,
+ avr/iotn25.h, avr/iotn26.h, avr/iotn261.h, avr/iotn28.h,
+ avr/iotn43u.h, avr/iotn44.h, avr/iotn45.h, avr/iotn461.h,
+ avr/iotn48.h, avr/iotn84.h, avr/iotn85.h, avr/iotn861.h,
+ avr/iotn87.h, avr/iotn88.h, avr/iotnx4.h, avr/iotnx5.h,
+ avr/iotnx61.h, avr/iousb1286.h, avr/iousb1287.h, avr/iousb162.h,
+ avr/iousb646.h, avr/iousb647.h, avr/iousb82.h, avr/iousbxx2.h,
+ avr/iousbxx6_7.h, avr/iox128a1.h, avr/iox128a3.h, avr/iox16a4.h,
+ avr/iox16d4.h, avr/iox256a3.h, avr/iox256a3b.h, avr/iox32a4.h,
+ avr/iox32d4.h, avr/iox64a1.h, avr/iox64a3.h, avr/lock.h,
+ avr/parity.h, avr/pgmspace.h, avr/portpins.h, avr/power.h,
+ avr/sfr_defs.h, avr/signal.h, avr/sleep.h, avr/version.h, avr/wdt.h,
+ rtems/asm.h, rtems/score/cpu.h: Update to avr .h files from avr-libc
+ 1.6.8. Tinker with code and includes to eliminate warnings. Now
+ builds multilib.
+ * avr/iom169pa.h, avr/iom16a.h, avr/iom16hva2.h, avr/iom16hvb.h,
+ avr/iom16u2.h, avr/iom324pa.h, avr/iom32u2.h, avr/iom644p.h,
+ avr/iom644pa.h, avr/iom649p.h, avr/iom64hve.h, avr/iom88pa.h,
+ avr/iom8u2.h, avr/iotn2313a.h, avr/iotn24a.h, avr/iotn261a.h,
+ avr/iotn4313.h, avr/iotn44a.h, avr/iotn461a.h, avr/iotn861a.h,
+ avr/iox128d3.h, avr/iox192a3.h, avr/iox192d3.h, avr/iox256d3.h,
+ avr/iox64d3.h, avr/signature.h: New files.
+
2010-03-27 Joel Sherrill <joel.sherrill at oarcorp.com>
* cpu.c, cpu_asm.S: Add include of config.h
diff -u rtems/cpukit/score/cpu/avr/Makefile.am:1.9 rtems/cpukit/score/cpu/avr/Makefile.am:1.10
--- rtems/cpukit/score/cpu/avr/Makefile.am:1.9 Thu Aug 6 09:52:04 2009
+++ rtems/cpukit/score/cpu/avr/Makefile.am Mon May 10 11:31:18 2010
@@ -14,35 +14,40 @@
include_rtems_avrdir = $(includedir)/avr
include_rtems_avr_HEADERS = \
avr/boot.h avr/common.h avr/crc16.h avr/delay.h avr/eeprom.h \
- avr/fuse.h avr/interrupt.h avr/io1200.h avr/io2313.h avr/io2323.h \
- avr/io2333.h avr/io2343.h avr/io43u32x.h avr/io43u35x.h avr/io4414.h \
- avr/io4433.h avr/io4434.h avr/io76c711.h avr/io8515.h avr/io8534.h \
- avr/io8535.h avr/io86r401.h avr/io90pwm1.h avr/io90pwm216.h \
- avr/io90pwm2b.h avr/io90pwm316.h avr/io90pwm3b.h avr/io90pwm81.h \
- avr/io90pwmx.h avr/io90scr100.h avr/ioa6289.h avr/ioat94k.h \
- avr/iocan128.h avr/iocan32.h avr/iocan64.h avr/iocanxx.h avr/io.h \
- avr/iom103.h avr/iom1280.h avr/iom1281.h avr/iom1284p.h avr/iom128.h \
- avr/iom128rfa1.h avr/iom161.h avr/iom162.h avr/iom163.h avr/iom164.h \
- avr/iom165.h avr/iom165p.h avr/iom168.h avr/iom168p.h avr/iom169.h \
- avr/iom169p.h avr/iom16.h avr/iom16hva.h avr/iom16m1.h avr/iom16u4.h \
- avr/iom2560.h avr/iom2561.h avr/iom323.h avr/iom324.h avr/iom3250.h \
- avr/iom325.h avr/iom328p.h avr/iom3290.h avr/iom329.h avr/iom32c1.h \
- avr/iom32.h avr/iom32hvb.h avr/iom32m1.h avr/iom32u4.h avr/iom32u6.h \
- avr/iom406.h avr/iom48.h avr/iom48p.h avr/iom640.h avr/iom644.h \
- avr/iom6450.h avr/iom645.h avr/iom6490.h avr/iom649.h avr/iom64c1.h \
- avr/iom64.h avr/iom64m1.h avr/iom8515.h avr/iom8535.h avr/iom88.h \
- avr/iom88p.h avr/iom8.h avr/iom8hva.h avr/iomx8.h avr/iomxx0_1.h \
- avr/iomxx4.h avr/iomxxhva.h avr/iotn11.h avr/iotn12.h avr/iotn13a.h \
- avr/iotn13.h avr/iotn15.h avr/iotn167.h avr/iotn22.h avr/iotn2313.h \
- avr/iotn24.h avr/iotn25.h avr/iotn261.h avr/iotn26.h avr/iotn28.h \
- avr/iotn43u.h avr/iotn44.h avr/iotn45.h avr/iotn461.h avr/iotn48.h \
- avr/iotn84.h avr/iotn85.h avr/iotn861.h avr/iotn87.h avr/iotn88.h \
- avr/iotnx4.h avr/iotnx5.h avr/iotnx61.h avr/iousb1286.h \
- avr/iousb1287.h avr/iousb162.h avr/iousb646.h avr/iousb647.h \
- avr/iousb82.h avr/iousbxx2.h avr/iousbxx6_7.h avr/iox128a1.h \
- avr/iox128a3.h avr/iox16a4.h avr/iox16d4.h avr/iox256a3b.h \
- avr/iox256a3.h avr/iox32a4.h avr/iox32d4.h avr/iox64a1.h avr/iox64a3.h \
- avr/lock.h avr/parity.h avr/pgmspace.h avr/portpins.h avr/power.h \
+ avr/fuse.h avr/interrupt.h avr/io1200.h avr/io2313.h \
+ avr/io2323.h avr/io2333.h avr/io2343.h avr/io43u32x.h \
+ avr/io43u35x.h avr/io4414.h avr/io4433.h avr/io4434.h \
+ avr/io76c711.h avr/io8515.h avr/io8534.h avr/io8535.h \
+ avr/io86r401.h avr/io90pwm1.h avr/io90pwm216.h avr/io90pwm2b.h \
+ avr/io90pwm316.h avr/io90pwm3b.h avr/io90pwm81.h avr/io90pwmx.h \
+ avr/io90scr100.h avr/ioa6289.h avr/ioat94k.h avr/iocan128.h \
+ avr/iocan32.h avr/iocan64.h avr/iocanxx.h avr/io.h avr/iom103.h \
+ avr/iom1280.h avr/iom1281.h avr/iom1284p.h avr/iom128.h \
+ avr/iom128rfa1.h avr/iom161.h avr/iom162.h avr/iom163.h \
+ avr/iom164.h avr/iom165.h avr/iom165p.h avr/iom168.h \
+ avr/iom168p.h avr/iom169.h avr/iom169p.h avr/iom16.h \
+ avr/iom16hva.h avr/iom16m1.h avr/iom16u4.h avr/iom2560.h \
+ avr/iom2561.h avr/iom323.h avr/iom324.h avr/iom3250.h \
+ avr/iom325.h avr/iom328p.h avr/iom3290.h avr/iom329.h \
+ avr/iom32c1.h avr/iom32.h avr/iom32hvb.h avr/iom32m1.h \
+ avr/iom32u4.h avr/iom32u6.h avr/iom406.h avr/iom48.h \
+ avr/iom48p.h avr/iom640.h avr/iom644.h avr/iom6450.h \
+ avr/iom645.h avr/iom6490.h avr/iom649.h avr/iom64c1.h \
+ avr/iom64.h avr/iom64m1.h avr/iom8515.h avr/iom8535.h \
+ avr/iom88.h avr/iom88p.h avr/iom8.h avr/iom8hva.h avr/iomx8.h \
+ avr/iomxx0_1.h avr/iomxx4.h avr/iomxxhva.h avr/iotn11.h \
+ avr/iotn12.h avr/iotn13a.h avr/iotn13.h avr/iotn15.h \
+ avr/iotn167.h avr/iotn22.h avr/iotn2313.h avr/iotn24.h \
+ avr/iotn25.h avr/iotn261.h avr/iotn26.h avr/iotn28.h \
+ avr/iotn43u.h avr/iotn44.h avr/iotn45.h avr/iotn461.h \
+ avr/iotn48.h avr/iotn84.h avr/iotn85.h avr/iotn861.h \
+ avr/iotn87.h avr/iotn88.h avr/iotnx4.h avr/iotnx5.h \
+ avr/iotnx61.h avr/iousb1286.h avr/iousb1287.h avr/iousb162.h \
+ avr/iousb646.h avr/iousb647.h avr/iousb82.h avr/iousbxx2.h \
+ avr/iousbxx6_7.h avr/iox128a1.h avr/iox128a3.h avr/iox16a4.h \
+ avr/iox16d4.h avr/iox256a3b.h avr/iox256a3.h avr/iox32a4.h \
+ avr/iox32d4.h avr/iox64a1.h avr/iox64a3.h avr/lock.h \
+ avr/parity.h avr/pgmspace.h avr/portpins.h avr/power.h \
avr/sfr_defs.h avr/signal.h avr/sleep.h avr/version.h avr/wdt.h
noinst_LIBRARIES = libscorecpu.a
diff -u rtems/cpukit/score/cpu/avr/avr/boot.h:1.2 rtems/cpukit/score/cpu/avr/avr/boot.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/boot.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/boot.h Mon May 10 11:31:19 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007 Eric B. Weddington
+/* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009 Eric B. Weddington
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -43,8 +43,8 @@
macros are designed to work with all sizes of flash memory.
Global interrupts are not automatically disabled for these macros. It
- is left up to the programmer to do this. See the code example below.
- Also see the processor datasheet for caveats on having global interrupts
+ is left up to the programmer to do this. See the code example below.
+ Also see the processor datasheet for caveats on having global interrupts
enabled during writing of the Flash.
\note Not all AVR processors provide bootloader support. See your
@@ -62,7 +62,7 @@
#include <inttypes.h>
#include <avr/interrupt.h>
#include <avr/pgmspace.h>
-
+
void boot_program_page (uint32_t page, uint8_t *buf)
{
uint16_t i;
@@ -72,7 +72,7 @@
sreg = SREG;
cli();
-
+
eeprom_busy_wait ();
boot_page_erase (page);
@@ -84,7 +84,7 @@
uint16_t w = *buf++;
w += (*buf++) << 8;
-
+
boot_page_fill (page + i, w);
}
@@ -195,7 +195,11 @@
#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
+#if defined(BLBSET)
#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
+#elif defined(RFLB) /* Some devices have RFLB defined instead of BLBSET. */
+#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB))
+#endif
#define __boot_page_fill_normal(address, data) \
(__extension__({ \
@@ -207,9 +211,9 @@
"clr r1\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_PAGE_FILL), \
- "z" ((uint16_t)address), \
- "r" ((uint16_t)data) \
+ "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
+ "z" ((uint16_t)(address)), \
+ "r" ((uint16_t)(data)) \
: "r0" \
); \
}))
@@ -226,9 +230,9 @@
"clr r1\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_PAGE_FILL), \
- "z" ((uint16_t)address), \
- "r" ((uint16_t)data) \
+ "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
+ "z" ((uint16_t)(address)), \
+ "r" ((uint16_t)(data)) \
: "r0" \
); \
}))
@@ -246,9 +250,9 @@
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"i" (_SFR_MEM_ADDR(RAMPZ)), \
- "r" ((uint8_t)__BOOT_PAGE_FILL), \
- "r" ((uint32_t)address), \
- "r" ((uint16_t)data) \
+ "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
+ "r" ((uint32_t)(address)), \
+ "r" ((uint16_t)(data)) \
: "r0", "r30", "r31" \
); \
}))
@@ -261,8 +265,8 @@
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_PAGE_ERASE), \
- "z" ((uint16_t)address) \
+ "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
+ "z" ((uint16_t)(address)) \
); \
}))
@@ -276,8 +280,8 @@
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_PAGE_ERASE), \
- "z" ((uint16_t)address) \
+ "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
+ "z" ((uint16_t)(address)) \
); \
}))
@@ -292,8 +296,8 @@
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"i" (_SFR_MEM_ADDR(RAMPZ)), \
- "r" ((uint8_t)__BOOT_PAGE_ERASE), \
- "r" ((uint32_t)address) \
+ "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
+ "r" ((uint32_t)(address)) \
: "r30", "r31" \
); \
}))
@@ -306,8 +310,8 @@
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_PAGE_WRITE), \
- "z" ((uint16_t)address) \
+ "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
+ "z" ((uint16_t)(address)) \
); \
}))
@@ -321,8 +325,8 @@
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_PAGE_WRITE), \
- "z" ((uint16_t)address) \
+ "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
+ "z" ((uint16_t)(address)) \
); \
}))
@@ -337,8 +341,8 @@
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
"i" (_SFR_MEM_ADDR(RAMPZ)), \
- "r" ((uint8_t)__BOOT_PAGE_WRITE), \
- "r" ((uint32_t)address) \
+ "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
+ "r" ((uint32_t)(address)) \
: "r30", "r31" \
); \
}))
@@ -351,7 +355,7 @@
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_RWW_ENABLE) \
+ "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
); \
}))
@@ -365,7 +369,7 @@
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_RWW_ENABLE) \
+ "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
); \
}))
@@ -379,11 +383,11 @@
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
will be programmed if an SPM instruction is executed within four cycles
- after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
- don't care during this operation, but for future compatibility it is
- recommended to load the Z-pointer with $0001 (same as used for reading the
- Lock bits). For future compatibility It is also recommended to set bits 7,
- 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
+ after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
+ don't care during this operation, but for future compatibility it is
+ recommended to load the Z-pointer with $0001 (same as used for reading the
+ Lock bits). For future compatibility It is also recommended to set bits 7,
+ 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
Lock bits the entire Flash can be read during the operation. */
#define __boot_lock_bits_set(lock_bits) \
@@ -398,7 +402,7 @@
"spm\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
+ "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
"r" (value) \
: "r0", "r30", "r31" \
); \
@@ -418,7 +422,7 @@
"nop\n\t" \
: \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
+ "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
"r" (value) \
: "r0", "r30", "r31" \
); \
@@ -427,8 +431,8 @@
/*
Reading lock and fuse bits:
- Similarly to writing the lock bits above, set BLBSET and SPMEN (or
- SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
+ Similarly to writing the lock bits above, set BLBSET and SPMEN (or
+ SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
LPM instruction.
Z address: contents:
@@ -481,15 +485,12 @@
uint8_t __result; \
__asm__ __volatile__ \
( \
- "ldi r30, %3\n\t" \
- "ldi r31, 0\n\t" \
"sts %1, %2\n\t" \
"lpm %0, Z\n\t" \
: "=r" (__result) \
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
- "M" (address) \
- : "r0", "r30", "r31" \
+ "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
+ "z" ((uint16_t)(address)) \
); \
__result; \
}))
@@ -508,31 +509,30 @@
#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
#define boot_signature_byte_get(addr) \
-(__extension__({ \
- uint16_t __addr16 = (uint16_t)(addr); \
- uint8_t __result; \
- __asm__ __volatile__ \
- ( \
- "sts %1, %2\n\t" \
- "lpm %0, Z" "\n\t" \
- : "=r" (__result) \
- : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
- "r" ((uint8_t) __BOOT_SIGROW_READ), \
- "z" (__addr16) \
- ); \
- __result; \
+(__extension__({ \
+ uint8_t __result; \
+ __asm__ __volatile__ \
+ ( \
+ "sts %1, %2\n\t" \
+ "lpm %0, Z" "\n\t" \
+ : "=r" (__result) \
+ : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
+ "r" ((uint8_t)(__BOOT_SIGROW_READ)), \
+ "z" ((uint16_t)(addr)) \
+ ); \
+ __result; \
}))
/** \ingroup avr_boot
\def boot_page_fill(address, data)
- Fill the bootloader temporary page buffer for flash
- address with data word.
+ Fill the bootloader temporary page buffer for flash
+ address with data word.
- \note The address is a byte address. The data is a word. The AVR
+ \note The address is a byte address. The data is a word. The AVR
writes data to the buffer a word at a time, but addresses the buffer
per byte! So, increment your address by 2 between calls, and send 2
- data bytes in a word format! The LSB of the data is written to the lower
+ data bytes in a word format! The LSB of the data is written to the lower
address; the MSB of the data is written to the higher address.*/
/** \ingroup avr_boot
@@ -545,9 +545,9 @@
/** \ingroup avr_boot
\def boot_page_write(address)
- Write the bootloader temporary page buffer
+ Write the bootloader temporary page buffer
to flash page that contains address.
-
+
\note address is a byte address in flash, not a word address. */
/** \ingroup avr_boot
@@ -582,7 +582,7 @@
instruction sequences after LPM.
FLASHEND is defined in the ioXXXX.h file.
- USHRT_MAX is defined in <limits.h>. */
+ USHRT_MAX is defined in <limits.h>. */
#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
|| defined(__AVR_ATmega323__)
diff -u rtems/cpukit/score/cpu/avr/avr/common.h:1.2 rtems/cpukit/score/cpu/avr/avr/common.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/common.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/common.h Mon May 10 11:31:19 2010
@@ -36,9 +36,9 @@
#include <avr/sfr_defs.h>
-/*
-This purpose of this header is to define registers that have not been
-previously defined in the individual device IO header files, and to define
+/*
+This purpose of this header is to define registers that have not been
+previously defined in the individual device IO header files, and to define
other symbols that are common across AVR device families.
This file is designed to be included in <avr/io.h> after the individual
@@ -48,7 +48,7 @@
/*------------ Registers Not Previously Defined ------------*/
-/*
+/*
These are registers that are not previously defined in the individual
IO header files, OR they are defined here because they are used in parts of
avr-libc even if a device is not selected but a general architecture has
@@ -59,7 +59,7 @@
/*
Stack pointer register.
-AVR architecture 1 has no RAM, thus no stack pointer.
+AVR architecture 1 has no RAM, thus no stack pointer.
All other architectures do have a stack pointer. Some devices have only
less than 256 bytes of possible RAM locations (128 Bytes of SRAM
@@ -76,7 +76,7 @@
# ifndef SP
# define SP _SFR_MEM16(0x3D)
# endif
-#elif __AVR_ARCH__ != 1
+#elif __AVR_ARCH__ != 1
# ifndef SPL
# define SPL _SFR_IO8(0x3D)
# endif
@@ -193,7 +193,7 @@
/*------------ Common Symbols ------------*/
-/*
+/*
Generic definitions for registers that are common across multiple AVR devices
and families.
*/
diff -u rtems/cpukit/score/cpu/avr/avr/eeprom.h:1.2 rtems/cpukit/score/cpu/avr/avr/eeprom.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/eeprom.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/eeprom.h Mon May 10 11:31:20 2010
@@ -2,6 +2,7 @@
Copyright (c) 2005, 2006 Bjoern Haase
Copyright (c) 2008 Atmel Corporation
Copyright (c) 2008 Wouter van Gulik
+ Copyright (c) 2009 Dmitry Xmelkov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -35,40 +36,379 @@
#define _AVR_EEPROM_H_ 1
#include <avr/io.h>
-#include <stddef.h> /* size_t */
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
+#if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__)
+# warning "Device does not have EEPROM available."
+#else
-#ifndef __ATTR_PURE__
-# ifdef __DOXYGEN__
-# define __ATTR_PURE__
-# else
-# define __ATTR_PURE__ __attribute__((__pure__))
-# endif
+#ifndef __DOXYGEN__
+
+#if defined (__AVR_AT94K__)
+# define _EEPROM_SUFFIX _at94k
+#elif defined (__AVR_AT43USB320__)
+# define _EEPROM_SUFFIX _43u320
+#elif defined (__AVR_AT43USB355__)
+# define _EEPROM_SUFFIX _43u355
+#elif defined (__AVR_AT76C711__)
+# define _EEPROM_SUFFIX _76c711
+#elif defined (__AVR_AT86RF401__)
+# define _EEPROM_SUFFIX _86r401
+#elif defined (__AVR_AT90PWM1__)
+# define _EEPROM_SUFFIX _90pwm1
+#elif defined (__AVR_AT90PWM2__)
+# define _EEPROM_SUFFIX _90pwm2
+#elif defined (__AVR_AT90PWM2B__)
+# define _EEPROM_SUFFIX _90pwm2b
+#elif defined (__AVR_AT90PWM3__)
+# define _EEPROM_SUFFIX _90pwm3
+#elif defined (__AVR_AT90PWM3B__)
+# define _EEPROM_SUFFIX _90pwm3b
+#elif defined (__AVR_AT90PWM216__)
+# define _EEPROM_SUFFIX _90pwm216
+#elif defined (__AVR_AT90PWM316__)
+# define _EEPROM_SUFFIX _90pwm316
+#elif defined (__AVR_AT90PWM81__)
+# define _EEPROM_SUFFIX _90pwm81
+#elif defined (__AVR_ATmega16M1__)
+# define _EEPROM_SUFFIX _m16m1
+#elif defined (__AVR_ATmega8U2__)
+# define _EEPROM_SUFFIX _m8u2
+#elif defined (__AVR_ATmega16U2__)
+# define _EEPROM_SUFFIX _m16u2
+#elif defined (__AVR_ATmega16U4__)
+# define _EEPROM_SUFFIX _m16u4
+#elif defined (__AVR_ATmega32C1__)
+# define _EEPROM_SUFFIX _m32c1
+#elif defined (__AVR_ATmega32M1__)
+# define _EEPROM_SUFFIX _m32m1
+#elif defined (__AVR_ATmega32U2__)
+# define _EEPROM_SUFFIX _m32u2
+#elif defined (__AVR_ATmega32U4__)
+# define _EEPROM_SUFFIX _m32u4
+#elif defined (__AVR_ATmega32U6__)
+# define _EEPROM_SUFFIX _m32u6
+#elif defined (__AVR_ATmega64C1__)
+# define _EEPROM_SUFFIX _m64c1
+#elif defined (__AVR_ATmega64M1__)
+# define _EEPROM_SUFFIX _m64m1
+#elif defined (__AVR_ATmega128__)
+# define _EEPROM_SUFFIX _m128
+#elif defined (__AVR_ATmega1280__)
+# define _EEPROM_SUFFIX _m1280
+#elif defined (__AVR_ATmega1281__)
+# define _EEPROM_SUFFIX _m1281
+#elif defined (__AVR_ATmega1284P__)
+# define _EEPROM_SUFFIX _m1284p
+#elif defined (__AVR_ATmega128RFA1__)
+# define _EEPROM_SUFFIX _m128rfa1
+#elif defined (__AVR_ATmega2560__)
+# define _EEPROM_SUFFIX _m2560
+#elif defined (__AVR_ATmega2561__)
+# define _EEPROM_SUFFIX _m2561
+#elif defined (__AVR_AT90CAN32__)
+# define _EEPROM_SUFFIX _can32
+#elif defined (__AVR_AT90CAN64__)
+# define _EEPROM_SUFFIX _can64
+#elif defined (__AVR_AT90CAN128__)
+# define _EEPROM_SUFFIX _can128
+#elif defined (__AVR_AT90USB82__)
+# define _EEPROM_SUFFIX _usb82
+#elif defined (__AVR_AT90USB162__)
+# define _EEPROM_SUFFIX _usb162
+#elif defined (__AVR_AT90USB646__)
+# define _EEPROM_SUFFIX _usb646
+#elif defined (__AVR_AT90USB647__)
+# define _EEPROM_SUFFIX _usb647
+#elif defined (__AVR_AT90USB1286__)
+# define _EEPROM_SUFFIX _usb1286
+#elif defined (__AVR_AT90USB1287__)
+# define _EEPROM_SUFFIX _usb1287
+#elif defined (__AVR_ATmega64__)
+# define _EEPROM_SUFFIX _m64
+#elif defined (__AVR_ATmega640__)
+# define _EEPROM_SUFFIX _m640
+#elif defined (__AVR_ATmega644__)
+# define _EEPROM_SUFFIX _m644
+#elif defined (__AVR_ATmega644A__)
+# define _EEPROM_SUFFIX _m644a
+#elif defined (__AVR_ATmega644P__)
+# define _EEPROM_SUFFIX _m644p
+#elif defined (__AVR_ATmega644PA__)
+# define _EEPROM_SUFFIX _m644pa
+#elif defined (__AVR_ATmega645__)
+# define _EEPROM_SUFFIX _m645
+#elif defined (__AVR_ATmega645A__)
+# define _EEPROM_SUFFIX _m645a
+#elif defined (__AVR_ATmega645P__)
+# define _EEPROM_SUFFIX _m645p
+#elif defined (__AVR_ATmega6450__)
+# define _EEPROM_SUFFIX _m6450
+#elif defined (__AVR_ATmega6450A__)
+# define _EEPROM_SUFFIX _m6450a
+#elif defined (__AVR_ATmega6450P__)
+# define _EEPROM_SUFFIX _m6450p
+#elif defined (__AVR_ATmega649__)
+# define _EEPROM_SUFFIX _m649
+#elif defined (__AVR_ATmega649A__)
+# define _EEPROM_SUFFIX _m649a
+#elif defined (__AVR_ATmega649P__)
+# define _EEPROM_SUFFIX _m649p
+#elif defined (__AVR_ATmega6490__)
+# define _EEPROM_SUFFIX _m6490
+#elif defined (__AVR_ATmega6490A__)
+# define _EEPROM_SUFFIX _m6490a
+#elif defined (__AVR_ATmega6490P__)
+# define _EEPROM_SUFFIX _m6490p
+#elif defined (__AVR_ATmega103__)
+# define _EEPROM_SUFFIX _m103
+#elif defined (__AVR_ATmega32__)
+# define _EEPROM_SUFFIX _m32
+#elif defined (__AVR_ATmega323__)
+# define _EEPROM_SUFFIX _m323
+#elif defined (__AVR_ATmega324A__)
+# define _EEPROM_SUFFIX _m324a
+#elif defined (__AVR_ATmega324P__)
+# define _EEPROM_SUFFIX _m324p
+#elif defined (__AVR_ATmega324PA__)
+# define _EEPROM_SUFFIX _m324pa
+#elif defined (__AVR_ATmega325__)
+# define _EEPROM_SUFFIX _m325
+#elif defined (__AVR_ATmega325P__)
+# define _EEPROM_SUFFIX _m325p
+#elif defined (__AVR_ATmega3250__)
+# define _EEPROM_SUFFIX _m3250
+#elif defined (__AVR_ATmega3250P__)
+# define _EEPROM_SUFFIX _m3250p
+#elif defined (__AVR_ATmega328__)
+# define _EEPROM_SUFFIX _m328
+#elif defined (__AVR_ATmega328P__)
+# define _EEPROM_SUFFIX _m328p
+#elif defined (__AVR_ATmega329__)
+# define _EEPROM_SUFFIX _m329
+#elif defined (__AVR_ATmega329P__)
+# define _EEPROM_SUFFIX _m329p
+#elif defined (__AVR_ATmega329PA__)
+# define _EEPROM_SUFFIX _m329pa
+#elif defined (__AVR_ATmega3290__)
+# define _EEPROM_SUFFIX _m3290
+#elif defined (__AVR_ATmega3290P__)
+# define _EEPROM_SUFFIX _m3290p
+#elif defined (__AVR_ATmega32HVB__)
+# define _EEPROM_SUFFIX _m32hvb
+#elif defined (__AVR_ATmega64HVE__)
+# define _EEPROM_SUFFIX _m64hve
+#elif defined (__AVR_ATmega406__)
+# define _EEPROM_SUFFIX _m406
+#elif defined (__AVR_ATmega16__)
+# define _EEPROM_SUFFIX _m16
+#elif defined (__AVR_ATmega16A__)
+# define _EEPROM_SUFFIX _m16a
+#elif defined (__AVR_ATmega161__)
+# define _EEPROM_SUFFIX _m161
+#elif defined (__AVR_ATmega162__)
+# define _EEPROM_SUFFIX _m162
+#elif defined (__AVR_ATmega163__)
+# define _EEPROM_SUFFIX _m163
+#elif defined (__AVR_ATmega164__)
+# define _EEPROM_SUFFIX _m164
+#elif defined (__AVR_ATmega164P__)
+# define _EEPROM_SUFFIX _m164p
+#elif defined (__AVR_ATmega165__)
+# define _EEPROM_SUFFIX _m165
+#elif defined (__AVR_ATmega165A__)
+# define _EEPROM_SUFFIX _m165a
+#elif defined (__AVR_ATmega165P__)
+# define _EEPROM_SUFFIX _m165p
+#elif defined (__AVR_ATmega168__)
+# define _EEPROM_SUFFIX _m168
+#elif defined (__AVR_ATmega168A__)
+# define _EEPROM_SUFFIX _m168a
+#elif defined (__AVR_ATmega168P__)
+# define _EEPROM_SUFFIX _m168p
+#elif defined (__AVR_ATmega169__)
+# define _EEPROM_SUFFIX _m169
+#elif defined (__AVR_ATmega169A__)
+# define _EEPROM_SUFFIX _m169a
+#elif defined (__AVR_ATmega169P__)
+# define _EEPROM_SUFFIX _m169p
+#elif defined (__AVR_ATmega169PA__)
+# define _EEPROM_SUFFIX _m169pa
+#elif defined (__AVR_ATmega8HVA__)
+# define _EEPROM_SUFFIX _m8hva
+#elif defined (__AVR_ATmega16HVA__)
+# define _EEPROM_SUFFIX _m16hva
+#elif defined (__AVR_ATmega16HVA2__)
+# define _EEPROM_SUFFIX _m16hva2
+#elif defined (__AVR_ATmega16HVB__)
+# define _EEPROM_SUFFIX _m16hvb
+#elif defined (__AVR_ATmega8__)
+# define _EEPROM_SUFFIX _m8
+#elif defined (__AVR_ATmega48__)
+# define _EEPROM_SUFFIX _m48
+#elif defined (__AVR_ATmega48A__)
+# define _EEPROM_SUFFIX _m48a
+#elif defined (__AVR_ATmega48P__)
+# define _EEPROM_SUFFIX _m48p
+#elif defined (__AVR_ATmega88__)
+# define _EEPROM_SUFFIX _m88
+#elif defined (__AVR_ATmega88A__)
+# define _EEPROM_SUFFIX _m88a
+#elif defined (__AVR_ATmega88P__)
+# define _EEPROM_SUFFIX _m88p
+#elif defined (__AVR_ATmega88PA__)
+# define _EEPROM_SUFFIX _m88pa
+#elif defined (__AVR_ATmega8515__)
+# define _EEPROM_SUFFIX _m8515
+#elif defined (__AVR_ATmega8535__)
+# define _EEPROM_SUFFIX _m8535
+#elif defined (__AVR_AT90S8535__)
+# define _EEPROM_SUFFIX _8535
+#elif defined (__AVR_AT90C8534__)
+# define _EEPROM_SUFFIX _8534
+#elif defined (__AVR_AT90S8515__)
+# define _EEPROM_SUFFIX _8515
+#elif defined (__AVR_AT90S4434__)
+# define _EEPROM_SUFFIX _4434
+#elif defined (__AVR_AT90S4433__)
+# define _EEPROM_SUFFIX _4433
+#elif defined (__AVR_AT90S4414__)
+# define _EEPROM_SUFFIX _4414
+#elif defined (__AVR_ATtiny22__)
+# define _EEPROM_SUFFIX _tn22
+#elif defined (__AVR_ATtiny26__)
+# define _EEPROM_SUFFIX _tn26
+#elif defined (__AVR_AT90S2343__)
+# define _EEPROM_SUFFIX _2343
+#elif defined (__AVR_AT90S2333__)
+# define _EEPROM_SUFFIX _2333
+#elif defined (__AVR_AT90S2323__)
+# define _EEPROM_SUFFIX _2323
+#elif defined (__AVR_AT90S2313__)
+# define _EEPROM_SUFFIX _2313
+#elif defined (__AVR_ATtiny2313__)
+# define _EEPROM_SUFFIX _tn2313
+#elif defined (__AVR_ATtiny2313A__)
+# define _EEPROM_SUFFIX _tn2313a
+#elif defined (__AVR_ATtiny4313__)
+# define _EEPROM_SUFFIX _tn4313
+#elif defined (__AVR_ATtiny13__)
+# define _EEPROM_SUFFIX _tn13
+#elif defined (__AVR_ATtiny13A__)
+# define _EEPROM_SUFFIX _tn13a
+#elif defined (__AVR_ATtiny25__)
+# define _EEPROM_SUFFIX _tn25
+#elif defined (__AVR_ATtiny45__)
+# define _EEPROM_SUFFIX _tn45
+#elif defined (__AVR_ATtiny85__)
+# define _EEPROM_SUFFIX _tn85
+#elif defined (__AVR_ATtiny24__)
+# define _EEPROM_SUFFIX _tn24
+#elif defined (__AVR_ATtiny24A__)
+# define _EEPROM_SUFFIX _tn24a
+#elif defined (__AVR_ATtiny44__)
+# define _EEPROM_SUFFIX _tn44
+#elif defined (__AVR_ATtiny44A__)
+# define _EEPROM_SUFFIX _tn44a
+#elif defined (__AVR_ATtiny84__)
+# define _EEPROM_SUFFIX _tn84
+#elif defined (__AVR_ATtiny261__)
+# define _EEPROM_SUFFIX _tn261
+#elif defined (__AVR_ATtiny261A__)
+# define _EEPROM_SUFFIX _tn261a
+#elif defined (__AVR_ATtiny461__)
+# define _EEPROM_SUFFIX _tn461
+#elif defined (__AVR_ATtiny461A__)
+# define _EEPROM_SUFFIX _tn461a
+#elif defined (__AVR_ATtiny861__)
+# define _EEPROM_SUFFIX _tn861
+#elif defined (__AVR_ATtiny861A__)
+# define _EEPROM_SUFFIX _tn861a
+#elif defined (__AVR_ATtiny43U__)
+# define _EEPROM_SUFFIX _tn43u
+#elif defined (__AVR_ATtiny48__)
+# define _EEPROM_SUFFIX _tn48
+#elif defined (__AVR_ATtiny88__)
+# define _EEPROM_SUFFIX _tn88
+#elif defined (__AVR_ATtiny87__)
+# define _EEPROM_SUFFIX _tn87
+#elif defined (__AVR_ATtiny167__)
+# define _EEPROM_SUFFIX _tn167
+#elif defined (__AVR_AT90SCR100__)
+# define _EEPROM_SUFFIX _90scr100
+#elif defined (__AVR_ATxmega16A4__)
+# define _EEPROM_SUFFIX _x16a4
+#elif defined (__AVR_ATxmega16D4__)
+# define _EEPROM_SUFFIX _x16d4
+#elif defined (__AVR_ATxmega32A4__)
+# define _EEPROM_SUFFIX _x32a4
+#elif defined (__AVR_ATxmega32D4__)
+# define _EEPROM_SUFFIX _x32d4
+#elif defined (__AVR_ATxmega64A1__)
+# define _EEPROM_SUFFIX _x64a1
+#elif defined (__AVR_ATxmega64A3__)
+# define _EEPROM_SUFFIX _x64a3
+#elif defined (__AVR_ATxmega64D3__)
+# define _EEPROM_SUFFIX _x64d3
+#elif defined (__AVR_ATxmega128A1__)
+# define _EEPROM_SUFFIX _x128a1
+#elif defined (__AVR_ATxmega128A3__)
+# define _EEPROM_SUFFIX _x128a3
+#elif defined (__AVR_ATxmega128D3__)
+# define _EEPROM_SUFFIX _x128d3
+#elif defined (__AVR_ATxmega192A3__)
+# define _EEPROM_SUFFIX _x192a3
+#elif defined (__AVR_ATxmega192D3__)
+# define _EEPROM_SUFFIX _x192d3
+#elif defined (__AVR_ATxmega256A3__)
+# define _EEPROM_SUFFIX _x256a3
+#elif defined (__AVR_ATxmega256A3B__)
+# define _EEPROM_SUFFIX _x256a3b
+#elif defined (__AVR_ATxmega256D3__)
+# define _EEPROM_SUFFIX _x256d3
+#elif defined (__AVR_ATA6289__)
+# define _EEPROM_SUFFIX _a6289
+/* avr1: the following only supported for assembler programs */
+#elif defined (__AVR_ATtiny28__)
+# define _EEPROM_SUFFIX _tn28
+#elif defined (__AVR_AT90S1200__)
+# define _EEPROM_SUFFIX _1200
+#elif defined (__AVR_ATtiny15__)
+# define _EEPROM_SUFFIX _tn15
+#elif defined (__AVR_ATtiny12__)
+# define _EEPROM_SUFFIX _tn12
+#elif defined (__AVR_ATtiny11__)
+# define _EEPROM_SUFFIX _tn11
+#else
+# define _EEPROM_SUFFIX _UNKNOWN
#endif
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
-uint16_t __eerd_word (const uint16_t *, uint8_t (*)(const uint8_t *))
- __ATTR_PURE__;
-uint32_t __eerd_dword (const uint32_t *, uint8_t (*)(const uint8_t *))
- __ATTR_PURE__;
-void __eerd_block (void *, const void *, size_t, uint8_t (*)(const uint8_t *));
-
-void __eewr_word (uint16_t *, uint16_t, void (*)(uint8_t *, uint8_t));
-void __eewr_dword (uint32_t *, uint32_t, void (*)(uint8_t *, uint8_t));
-void __eewr_block (void *, const void *, size_t, void (*)(uint8_t *, uint8_t));
-#endif /* (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) ) */
-
-#if !E2END && !defined(__DOXYGEN__)
-# ifndef __COMPILING_AVR_LIBC__
-# warning "Device does not have EEPROM available."
-# endif
- /* Omit below for chips without EEPROM. */
+#define _EEPROM_CONCAT1(s1, s2) s1 ## s2
+#define _EEPROM_CONCAT2(s1, s2) _EEPROM_CONCAT1 (s1, s2)
-#else
+#define eeprom_read_byte _EEPROM_CONCAT2 (__eerd_byte, _EEPROM_SUFFIX)
+#define eeprom_read_word _EEPROM_CONCAT2 (__eerd_word, _EEPROM_SUFFIX)
+#define eeprom_read_dword _EEPROM_CONCAT2 (__eerd_dword, _EEPROM_SUFFIX)
+#define eeprom_read_float _EEPROM_CONCAT2 (__eerd_float, _EEPROM_SUFFIX)
+#define eeprom_read_block _EEPROM_CONCAT2 (__eerd_block, _EEPROM_SUFFIX)
+
+#define eeprom_write_byte _EEPROM_CONCAT2 (__eewr_byte, _EEPROM_SUFFIX)
+#define eeprom_write_word _EEPROM_CONCAT2 (__eewr_word, _EEPROM_SUFFIX)
+#define eeprom_write_dword _EEPROM_CONCAT2 (__eewr_dword, _EEPROM_SUFFIX)
+#define eeprom_write_float _EEPROM_CONCAT2 (__eewr_float, _EEPROM_SUFFIX)
+#define eeprom_write_block _EEPROM_CONCAT2 (__eewr_block, _EEPROM_SUFFIX)
+
+#define eeprom_update_byte _EEPROM_CONCAT2 (__eeupd_byte, _EEPROM_SUFFIX)
+#define eeprom_update_word _EEPROM_CONCAT2 (__eeupd_word, _EEPROM_SUFFIX)
+#define eeprom_update_dword _EEPROM_CONCAT2 (__eeupd_dword, _EEPROM_SUFFIX)
+#define eeprom_update_float _EEPROM_CONCAT2 (__eeupd_float, _EEPROM_SUFFIX)
+#define eeprom_update_block _EEPROM_CONCAT2 (__eeupd_block, _EEPROM_SUFFIX)
+
+#endif /* !__DOXYGEN__ */
+
+#ifndef __ASSEMBLER__
+
+#include <stddef.h> /* size_t */
+#include <stdint.h>
/** \defgroup avr_eeprom <avr/eeprom.h>: EEPROM handling
\code #include <avr/eeprom.h> \endcode
@@ -80,104 +420,66 @@
EEPROM access to ensure that no time will be wasted in spinloops
will have to deploy their own implementation.
- \note All of the read/write functions first make sure the EEPROM
- is ready to be accessed. Since this may cause long delays if a
+ \par Notes:
+
+ - In addition to the write functions there is a set of update ones.
+ This functions read each byte first and skip the burning if the
+ old value is the same with new. The scaning direction is from
+ high address to low, to obtain quick return in common cases.
+
+ - All of the read/write functions first make sure the EEPROM is
+ ready to be accessed. Since this may cause long delays if a
write operation is still pending, time-critical applications
should first poll the EEPROM e. g. using eeprom_is_ready() before
attempting any actual I/O. But this functions are not wait until
SELFPRGEN in SPMCSR becomes zero. Do this manually, if your
softwate contains the Flash burning.
- \note As these functions modify IO registers, they are known to be
+ - As these functions modify IO registers, they are known to be
non-reentrant. If any of these functions are used from both,
standard and interrupt context, the applications must ensure
proper protection (e.g. by disabling interrupts before accessing
them).
- \note All write functions force erase_and_write programming mode.
+ - All write functions force erase_and_write programming mode.
+
+ - For Xmega the EEPROM start address is 0, like other architectures.
+ The reading functions add the 0x2000 value to use EEPROM mapping into
+ data space.
*/
-/** \def EEMEM
- \ingroup avr_eeprom
- Attribute expression causing a variable to be allocated within the
- .eeprom section. */
-#define EEMEM __attribute__((section(".eeprom")))
-
-
-/* Register definitions */
-
-/* Check for aliases. */
-#if !defined(EEWE) && defined(EEPE)
-# define EEWE EEPE
-#endif
-
-#if !defined(EEMWE) && defined(EEMPE)
-# define EEMWE EEMPE
-#endif
-
-#if !defined(EECR) && defined(DEECR)
-/* AT86RF401 */
-# define EECR DEECR
-# define EEAR DEEAR
-# define EEARL DEEAR
-# define EEDR DEEDR
-# define EERE EER
-# define EEWE EEL
-# define EEMWE EEU
+#ifdef __cplusplus
+extern "C" {
#endif
-
-#if !defined(EECR) || !defined(EEDR) || !defined(EEARL)
-
-# if !defined(__EEPROM_REG_LOCATIONS__) \
- && !defined(EEPROM_REG_LOCATIONS_OVERRIDE)
- /* 6-byte string denoting where to find the EEPROM registers in memory
- space. Adresses denoted in hex syntax with uppercase letters. Used
- by the EEPROM subroutines.
- First two letters: EECR address.
- Second two letters: EEDR address.
- Last two letters: EEAR address.
- */
-# error "Unknown EEPROM register(s) location."
-# endif
-
-/* If needed, override the locations defined in the IO headers. */
-# ifdef EEPROM_REG_LOCATIONS_OVERRIDE
-# undef __EEPROM_REG_LOCATIONS__
-# define __EEPROM_REG_LOCATIONS__ EEPROM_REG_LOCATIONS_OVERRIDE
+#ifndef __ATTR_PURE__
+# ifdef __DOXYGEN__
+# define __ATTR_PURE__
+# else
+# define __ATTR_PURE__ __attribute__((__pure__))
# endif
-
-# define CONCAT1(a, b) CONCAT2(a, b)
-# define CONCAT2(a, b) a ## b
-# define HEXNR CONCAT1(0x, __EEPROM_REG_LOCATIONS__)
-
-# undef EECR
-# define EECR _SFR_IO8((HEXNR >> 16) & 0xFF)
-
-# undef EEDR
-# define EEDR _SFR_IO8((HEXNR >> 8) & 0xFF)
-
-# undef EEAR
-# define EEAR _SFR_IO8(HEXNR & 0xFF)
-
-# undef EEARH
-
-# undef EEARL
-# define EEARL EEAR
-
#endif
+/** \def EEMEM
+ \ingroup avr_eeprom
+ Attribute expression causing a variable to be allocated within the
+ .eeprom section. */
+#define EEMEM __attribute__((section(".eeprom")))
/** \def eeprom_is_ready
\ingroup avr_eeprom
\returns 1 if EEPROM is ready for a new read/write operation, 0 if not.
*/
-#if defined(__DOXYGEN__)
+#if defined (__DOXYGEN__)
# define eeprom_is_ready()
-#elif defined(DEECR)
-# define eeprom_is_ready() bit_is_clear(DEECR, BSY)
+#elif defined (__AVR_XMEGA__) && __AVR_XMEGA__
+# define eeprom_is_ready() bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp)
+#elif defined (DEECR)
+# define eeprom_is_ready() bit_is_clear (DEECR, BSY)
+#elif defined (EEPE)
+# define eeprom_is_ready() bit_is_clear (EECR, EEPE)
#else
-# define eeprom_is_ready() bit_is_clear(EECR, EEWE)
+# define eeprom_is_ready() bit_is_clear (EECR, EEWE)
#endif
@@ -185,219 +487,90 @@
\ingroup avr_eeprom
Loops until the eeprom is no longer busy.
\returns Nothing.
- */
+ */
#define eeprom_busy_wait() do {} while (!eeprom_is_ready())
/** \ingroup avr_eeprom
Read one byte from EEPROM address \a __p.
*/
-__ATTR_PURE__ static __inline__ uint8_t eeprom_read_byte (const uint8_t *__p)
-{
- do {} while (!eeprom_is_ready ());
-#if E2END <= 0xFF
- EEARL = (size_t)__p;
-#else
- EEAR = (size_t)__p;
-#endif
- /* Use inline assembly below as some AVRs have problems with accessing
- EECR with STS instructions. For example, see errata for ATmega64.
- The code below also assumes that EECR and EEDR are in the I/O space.
- */
- uint8_t __result;
- __asm__ __volatile__
- (
- "/* START EEPROM READ CRITICAL SECTION */ \n\t"
- "sbi %1, %2 \n\t"
- "in %0, %3 \n\t"
- "/* END EEPROM READ CRITICAL SECTION */ \n\t"
- : "=r" (__result)
- : "i" (_SFR_IO_ADDR(EECR)),
- "i" (EERE),
- "i" (_SFR_IO_ADDR(EEDR))
- );
- return __result;
-}
+uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read one 16-bit word (little endian) from EEPROM address \a __p.
*/
-__ATTR_PURE__ static __inline__ uint16_t eeprom_read_word (const uint16_t *__p)
-{
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
- return __eerd_word (__p, eeprom_read_byte);
-#else
- /* If ATmega256x device, do not call function. */
- union
- {
- uint16_t word;
- struct
- {
- uint8_t lo;
- uint8_t hi;
- } byte;
- } x;
-
- x.byte.lo = eeprom_read_byte ((const uint8_t *)__p);
- x.byte.hi = eeprom_read_byte ((const uint8_t *)__p + 1);
- return x.word;
-#endif
-}
+uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read one 32-bit double word (little endian) from EEPROM address \a __p.
*/
-__ATTR_PURE__ static __inline__
-uint32_t eeprom_read_dword (const uint32_t *__p)
-{
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
- return __eerd_dword (__p, eeprom_read_byte);
-#else
- /* If ATmega256x device, do not call function. */
- union
- {
- uint32_t dword;
- struct
- {
- uint8_t byte0;
- uint8_t byte1;
- uint8_t byte2;
- uint8_t byte3;
- } byte;
- } x;
-
- x.byte.byte0 = eeprom_read_byte ((const uint8_t *)__p);
- x.byte.byte1 = eeprom_read_byte ((const uint8_t *)__p + 1);
- x.byte.byte2 = eeprom_read_byte ((const uint8_t *)__p + 2);
- x.byte.byte3 = eeprom_read_byte ((const uint8_t *)__p + 3);
- return x.dword;
-#endif
-}
+uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__;
+
+/** \ingroup avr_eeprom
+ Read one float value (little endian) from EEPROM address \a __p.
+ */
+float eeprom_read_float (const float *__p) __ATTR_PURE__;
/** \ingroup avr_eeprom
Read a block of \a __n bytes from EEPROM address \a __src to SRAM
\a __dst.
*/
-static __inline__ void
-eeprom_read_block (void *__dst, const void *__src, size_t __n)
-{
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
- __eerd_block (__dst, __src, __n, eeprom_read_byte);
-#else
- /* If ATmega256x device, do not call function. */
- while (__n--)
- {
- *(char *)__dst++ = eeprom_read_byte(__src++);
- }
-#endif
-}
+void eeprom_read_block (void *__dst, const void *__src, size_t __n);
+
/** \ingroup avr_eeprom
Write a byte \a __value to EEPROM address \a __p.
*/
-static __inline__ void eeprom_write_byte (uint8_t *__p, uint8_t __value)
-{
- do {} while (!eeprom_is_ready ());
-
-#if defined(EEPM0) && defined(EEPM1)
- EECR = 0; /* Set programming mode: erase and write. */
-#elif defined(EEPM0) || defined(EEPM1)
-# warning "Unknown EECR register, eeprom_write_byte() has become outdated."
-#endif
-
-#if E2END <= 0xFF
- EEARL = (size_t)__p;
-#else
- EEAR = (size_t)__p;
-#endif
- EEDR = __value;
-
- __asm__ __volatile__ (
- "/* START EEPROM WRITE CRITICAL SECTION */\n\t"
- "in r0, %[__sreg] \n\t"
- "cli \n\t"
- "sbi %[__eecr], %[__eemwe] \n\t"
- "sbi %[__eecr], %[__eewe] \n\t"
- "out %[__sreg], r0 \n\t"
- "/* END EEPROM WRITE CRITICAL SECTION */"
- :
- : [__eecr] "i" (_SFR_IO_ADDR(EECR)),
- [__sreg] "i" (_SFR_IO_ADDR(SREG)),
- [__eemwe] "i" (EEMWE),
- [__eewe] "i" (EEWE)
- : "r0"
- );
-}
+void eeprom_write_byte (uint8_t *__p, uint8_t __value);
/** \ingroup avr_eeprom
Write a word \a __value to EEPROM address \a __p.
*/
-static __inline__ void eeprom_write_word (uint16_t *__p, uint16_t __value)
-{
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
- __eewr_word (__p, __value, eeprom_write_byte);
-#else
- /* If ATmega256x device, do not call function. */
- union
- {
- uint16_t word;
- struct
- {
- uint8_t lo;
- uint8_t hi;
- } byte;
- } x;
-
- x.word = __value;
- eeprom_write_byte ((uint8_t *)__p, x.byte.lo);
- eeprom_write_byte ((uint8_t *)__p + 1, x.byte.hi);
-#endif
-}
+void eeprom_write_word (uint16_t *__p, uint16_t __value);
/** \ingroup avr_eeprom
Write a 32-bit double word \a __value to EEPROM address \a __p.
*/
-static __inline__ void eeprom_write_dword (uint32_t *__p, uint32_t __value)
-{
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
- __eewr_dword (__p, __value, eeprom_write_byte);
-#else
- /* If ATmega256x device, do not call function. */
- union
- {
- uint32_t dword;
- struct
- {
- uint8_t byte0;
- uint8_t byte1;
- uint8_t byte2;
- uint8_t byte3;
- } byte;
- } x;
-
- x.dword = __value;
- eeprom_write_byte ((uint8_t *)__p, x.byte.byte0);
- eeprom_write_byte ((uint8_t *)__p + 1, x.byte.byte1);
- eeprom_write_byte ((uint8_t *)__p + 2, x.byte.byte2);
- eeprom_write_byte ((uint8_t *)__p + 3, x.byte.byte3);
-#endif
-}
+void eeprom_write_dword (uint32_t *__p, uint32_t __value);
+
+/** \ingroup avr_eeprom
+ Write a float \a __value to EEPROM address \a __p.
+ */
+void eeprom_write_float (float *__p, float __value);
/** \ingroup avr_eeprom
Write a block of \a __n bytes to EEPROM address \a __dst from \a __src.
\note The argument order is mismatch with common functions like strcpy().
*/
-static __inline__ void
-eeprom_write_block (const void *__src, void *__dst, size_t __n)
-{
-#if (! (defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)) )
- __eewr_block (__dst, __src, __n, eeprom_write_byte);
-#else
- /* If ATmega256x device, do not call function. */
- while (__n--)
- eeprom_write_byte (__dst++, *(uint8_t *)__src++);
-#endif
-}
+void eeprom_write_block (const void *__src, void *__dst, size_t __n);
+
+
+/** \ingroup avr_eeprom
+ Update a byte \a __value to EEPROM address \a __p.
+ */
+void eeprom_update_byte (uint8_t *__p, uint8_t __value);
+
+/** \ingroup avr_eeprom
+ Update a word \a __value to EEPROM address \a __p.
+ */
+void eeprom_update_word (uint16_t *__p, uint16_t __value);
+
+/** \ingroup avr_eeprom
+ Update a 32-bit double word \a __value to EEPROM address \a __p.
+ */
+void eeprom_update_dword (uint32_t *__p, uint32_t __value);
+
+/** \ingroup avr_eeprom
+ Update a float \a __value to EEPROM address \a __p.
+ */
+void eeprom_update_float (float *__p, float __value);
+
+/** \ingroup avr_eeprom
+ Update a block of \a __n bytes to EEPROM address \a __dst from \a __src.
+ \note The argument order is mismatch with common functions like strcpy().
+ */
+void eeprom_update_block (const void *__src, void *__dst, size_t __n);
+
/** \name IAR C compatibility defines */
/*@{*/
@@ -407,17 +580,27 @@
Write a byte to EEPROM. Compatibility define for IAR C. */
#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
+/** \def __EEPUT
+ \ingroup avr_eeprom
+ Write a byte to EEPROM. Compatibility define for IAR C. */
+#define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
+
/** \def _EEGET
\ingroup avr_eeprom
Read a byte from EEPROM. Compatibility define for IAR C. */
#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
-/*@}*/
+/** \def __EEGET
+ \ingroup avr_eeprom
+ Read a byte from EEPROM. Compatibility define for IAR C. */
+#define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
-#endif /* E2END || defined(__DOXYGEN__) */
+/*@}*/
#ifdef __cplusplus
}
#endif
-#endif /* !_AVR_EEPROM_H */
+#endif /* !__ASSEMBLER__ */
+#endif /* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */
+#endif /* !_AVR_EEPROM_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/fuse.h:1.2 rtems/cpukit/score/cpu/avr/avr/fuse.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/fuse.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/fuse.h Mon May 10 11:31:20 2010
@@ -35,6 +35,11 @@
#ifndef _AVR_FUSE_H_
#define _AVR_FUSE_H_ 1
+/* This file must be explicitly included by <avr/io.h>. */
+#if !defined(_AVR_IO_H_)
+#error "You must #include <avr/io.h> and not <avr/fuse.h> by itself."
+#endif
+
/** \file */
/** \defgroup avr_fuse <avr/fuse.h>: Fuse Support
@@ -49,37 +54,37 @@
the ELF file, by extracting this information and determining if the fuses
need to be programmed before programming the Flash and EEPROM memories.
This also allows a single ELF file to contain all the
- information needed to program an AVR.
+ information needed to program an AVR.
To use the Fuse API, include the <avr/io.h> header file, which in turn
automatically includes the individual I/O header file and the <avr/fuse.h>
file. These other two files provides everything necessary to set the AVR
fuses.
-
+
\par Fuse API
-
+
Each I/O header file must define the FUSE_MEMORY_SIZE macro which is
defined to the number of fuse bytes that exist in the AVR device.
-
- A new type, __fuse_t, is defined as a structure. The number of fields in
- this structure are determined by the number of fuse bytes in the
+
+ A new type, __fuse_t, is defined as a structure. The number of fields in
+ this structure are determined by the number of fuse bytes in the
FUSE_MEMORY_SIZE macro.
-
+
If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type
unsigned char.
-
+
If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type
unsigned char.
-
+
If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended,
of type unsigned char.
-
+
If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array
of unsigned char with the size of the array being FUSE_MEMORY_SIZE.
-
- A convenience macro, FUSEMEM, is defined as a GCC attribute for a
+
+ A convenience macro, FUSEMEM, is defined as a GCC attribute for a
custom-named section of ".fuse".
-
+
A convenience macro, FUSES, is defined that declares a variable, __fuse, of
type __fuse_t with the attribute defined by FUSEMEM. This variable
allows the end user to easily set the fuse data.
@@ -97,20 +102,20 @@
\code
#define FUSE_EESAVE ~_BV(3)
\endcode
- \note The _BV macro creates a bit mask from a bit number. It is then
+ \note The _BV macro creates a bit mask from a bit number. It is then
inverted to represent logical values for a fuse memory byte.
-
+
To combine the fuse bits macros together to represent a whole fuse byte,
use the bitwise AND operator, like so:
\code
(FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN)
\endcode
-
+
Each device I/O header file also defines macros that provide default values
for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low
Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT
is defined for an Extended Fuse byte.
-
+
If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that
provide default values for each fuse byte like so:
FUSE0_DEFAULT
@@ -119,15 +124,15 @@
FUSE3_DEFAULT
FUSE4_DEFAULT
....
-
+
\par API Usage Example
-
+
Putting all of this together is easy. Using C99's designated initializers:
-
+
\code
#include <avr/io.h>
- FUSES =
+ FUSES =
{
.low = LFUSE_DEFAULT,
.high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
@@ -139,13 +144,13 @@
return 0;
}
\endcode
-
+
Or, using the variable directly instead of the FUSES macro,
-
+
\code
#include <avr/io.h>
- __fuse_t __fuse __attribute__((section (".fuse"))) =
+ __fuse_t __fuse __attribute__((section (".fuse"))) =
{
.low = LFUSE_DEFAULT,
.high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
@@ -157,14 +162,14 @@
return 0;
}
\endcode
-
+
If you are compiling in C++, you cannot use the designated intializers so
you must do:
\code
#include <avr/io.h>
- FUSES =
+ FUSES =
{
LFUSE_DEFAULT, // .low
(FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high
@@ -176,33 +181,33 @@
return 0;
}
\endcode
-
-
+
+
However there are a number of caveats that you need to be aware of to
use this API properly.
-
+
Be sure to include <avr/io.h> to get all of the definitions for the API.
- The FUSES macro defines a global variable to store the fuse data. This
- variable is assigned to its own linker section. Assign the desired fuse
+ The FUSES macro defines a global variable to store the fuse data. This
+ variable is assigned to its own linker section. Assign the desired fuse
values immediately in the variable initialization.
-
- The .fuse section in the ELF file will get its values from the initial
- variable assignment ONLY. This means that you can NOT assign values to
+
+ The .fuse section in the ELF file will get its values from the initial
+ variable assignment ONLY. This means that you can NOT assign values to
this variable in functions and the new values will not be put into the
ELF .fuse section.
-
- The global variable is declared in the FUSES macro has two leading
+
+ The global variable is declared in the FUSES macro has two leading
underscores, which means that it is reserved for the "implementation",
meaning the library, so it will not conflict with a user-named variable.
-
+
You must initialize ALL fields in the __fuse_t structure. This is because
- the fuse bits in all bytes default to a logical 1, meaning unprogrammed.
+ the fuse bits in all bytes default to a logical 1, meaning unprogrammed.
Normal uninitialized data defaults to all locgial zeros. So it is vital that
all fuse bytes are initialized, even with default data. If they are not,
then the fuse bits may not programmed to the desired settings.
-
+
Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
- your linker command line to have the correct device selected and to have
+ your linker command line to have the correct device selected and to have
the correct I/O header file included when you include <avr/io.h>.
You can print out the contents of the .fuse section in the ELF file by
diff -u rtems/cpukit/score/cpu/avr/avr/interrupt.h:1.2 rtems/cpukit/score/cpu/avr/avr/interrupt.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/interrupt.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/interrupt.h Mon May 10 11:31:20 2010
@@ -42,16 +42,16 @@
#define __STRINGIFY(x) #x
#endif /* !defined(__DOXYGEN__) */
-/**
-\file
-\@{
+/**
+\file
+\@{
*/
/** \name Global manipulation of the interrupt flag
The global interrupt flag is maintained in the I bit of the status
- register (SREG).
+ register (SREG).
*/
#if defined(__DOXYGEN__)
@@ -209,7 +209,7 @@
}
ISR_ALIAS(INT1_vect, INT0_vect);
- \endcode
+ \endcode
*/
# define ISR_ALIAS(vector, target_vector)
#else /* real code */
diff -u rtems/cpukit/score/cpu/avr/avr/io.h:1.2 rtems/cpukit/score/cpu/avr/avr/io.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
but most of the details come from the respective include file.
Note that this file always includes the following files:
- \code
+ \code
#include <avr/sfr_defs.h>
#include <avr/portpins.h>
#include <avr/common.h>
@@ -71,8 +71,8 @@
<br>
- \b XRAMEND
<br>
- The last possible RAM location that is addressable. This is equal to
- RAMEND for devices that do not allow for external RAM. For devices
+ The last possible RAM location that is addressable. This is equal to
+ RAMEND for devices that do not allow for external RAM. For devices
that allow external RAM, this will be larger than RAMEND.
<br>
- \b E2END
@@ -86,11 +86,11 @@
- \b SPM_PAGESIZE
<br>
For devices with bootloader support, the flash pagesize
- (in bytes) to be used for the \c SPM instruction.
+ (in bytes) to be used for the \c SPM instruction.
- \b E2PAGESIZE
<br>
The size of the EEPROM page.
-
+
*/
#ifndef _AVR_IO_H_
@@ -124,14 +124,20 @@
# include <avr/io90pwm316.h>
#elif defined (__AVR_AT90PWM81__)
# include <avr/io90pwm81.h>
+#elif defined (__AVR_ATmega8U2__)
+# include <avr/iom8u2.h>
#elif defined (__AVR_ATmega16M1__)
# include <avr/iom16m1.h>
+#elif defined (__AVR_ATmega16U2__)
+# include <avr/iom16u2.h>
#elif defined (__AVR_ATmega16U4__)
# include <avr/iom16u4.h>
#elif defined (__AVR_ATmega32C1__)
# include <avr/iom32c1.h>
#elif defined (__AVR_ATmega32M1__)
# include <avr/iom32m1.h>
+#elif defined (__AVR_ATmega32U2__)
+# include <avr/iom32u2.h>
#elif defined (__AVR_ATmega32U4__)
# include <avr/iom32u4.h>
#elif defined (__AVR_ATmega32U6__)
@@ -176,26 +182,34 @@
# include <avr/iom64.h>
#elif defined (__AVR_ATmega640__)
# include <avr/iom640.h>
-#elif defined (__AVR_ATmega644__)
+#elif defined (__AVR_ATmega644__) || defined (__AVR_ATmega644A__)
# include <avr/iom644.h>
#elif defined (__AVR_ATmega644P__)
-# include <avr/iom644.h>
-#elif defined (__AVR_ATmega645__)
+# include <avr/iom644p.h>
+#elif defined (__AVR_ATmega644PA__)
+# include <avr/iom644pa.h>
+#elif defined (__AVR_ATmega645__) || defined (__AVR_ATmega645A__) || defined (__AVR_ATmega645P__)
# include <avr/iom645.h>
-#elif defined (__AVR_ATmega6450__)
+#elif defined (__AVR_ATmega6450__) || defined (__AVR_ATmega6450A__) || defined (__AVR_ATmega6450P__)
# include <avr/iom6450.h>
-#elif defined (__AVR_ATmega649__)
+#elif defined (__AVR_ATmega649__) || defined (__AVR_ATmega649A__)
# include <avr/iom649.h>
-#elif defined (__AVR_ATmega6490__)
+#elif defined (__AVR_ATmega6490__) || defined (__AVR_ATmega6490A__) || defined (__AVR_ATmega6490P__)
# include <avr/iom6490.h>
+#elif defined (__AVR_ATmega649P__)
+# include <avr/iom649p.h>
+#elif defined (__AVR_ATmega64HVE__)
+# include <avr/iom64hve.h>
#elif defined (__AVR_ATmega103__)
# include <avr/iom103.h>
#elif defined (__AVR_ATmega32__)
# include <avr/iom32.h>
#elif defined (__AVR_ATmega323__)
# include <avr/iom323.h>
-#elif defined (__AVR_ATmega324P__)
+#elif defined (__AVR_ATmega324P__) || defined (__AVR_ATmega324A__)
# include <avr/iom324.h>
+#elif defined (__AVR_ATmega324PA__)
+# include <avr/iom324pa.h>
#elif defined (__AVR_ATmega325__)
# include <avr/iom325.h>
#elif defined (__AVR_ATmega325P__)
@@ -204,11 +218,11 @@
# include <avr/iom3250.h>
#elif defined (__AVR_ATmega3250P__)
# include <avr/iom3250.h>
-#elif defined (__AVR_ATmega328P__)
+#elif defined (__AVR_ATmega328P__) || defined (__AVR_ATmega328__)
# include <avr/iom328p.h>
#elif defined (__AVR_ATmega329__)
# include <avr/iom329.h>
-#elif defined (__AVR_ATmega329P__)
+#elif defined (__AVR_ATmega329P__) || defined (__AVR_ATmega329PA__)
# include <avr/iom329.h>
#elif defined (__AVR_ATmega3290__)
# include <avr/iom3290.h>
@@ -220,40 +234,50 @@
# include <avr/iom406.h>
#elif defined (__AVR_ATmega16__)
# include <avr/iom16.h>
+#elif defined (__AVR_ATmega16A__)
+# include <avr/iom16a.h>
#elif defined (__AVR_ATmega161__)
# include <avr/iom161.h>
#elif defined (__AVR_ATmega162__)
# include <avr/iom162.h>
#elif defined (__AVR_ATmega163__)
# include <avr/iom163.h>
-#elif defined (__AVR_ATmega164P__)
+#elif defined (__AVR_ATmega164P__) || defined (__AVR_ATmega164A__)
# include <avr/iom164.h>
-#elif defined (__AVR_ATmega165__)
+#elif defined (__AVR_ATmega165__) || defined (__AVR_ATmega165A__)
# include <avr/iom165.h>
#elif defined (__AVR_ATmega165P__)
# include <avr/iom165p.h>
-#elif defined (__AVR_ATmega168__)
+#elif defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
# include <avr/iom168.h>
#elif defined (__AVR_ATmega168P__)
# include <avr/iom168p.h>
-#elif defined (__AVR_ATmega169__)
+#elif defined (__AVR_ATmega169__) || defined (__AVR_ATmega169A__)
# include <avr/iom169.h>
#elif defined (__AVR_ATmega169P__)
# include <avr/iom169p.h>
+#elif defined (__AVR_ATmega169PA__)
+# include <avr/iom169pa.h>
#elif defined (__AVR_ATmega8HVA__)
# include <avr/iom8hva.h>
#elif defined (__AVR_ATmega16HVA__)
# include <avr/iom16hva.h>
+#elif defined (__AVR_ATmega16HVA2__)
+# include <avr/iom16hva2.h>
+#elif defined (__AVR_ATmega16HVB__)
+# include <avr/iom16hvb.h>
#elif defined (__AVR_ATmega8__)
# include <avr/iom8.h>
-#elif defined (__AVR_ATmega48__)
+#elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega48A__)
# include <avr/iom48.h>
#elif defined (__AVR_ATmega48P__)
# include <avr/iom48p.h>
-#elif defined (__AVR_ATmega88__)
+#elif defined (__AVR_ATmega88__) || defined (__AVR_ATmega88A__)
# include <avr/iom88.h>
#elif defined (__AVR_ATmega88P__)
# include <avr/iom88p.h>
+#elif defined (__AVR_ATmega88PA__)
+# include <avr/iom88pa.h>
#elif defined (__AVR_ATmega8515__)
# include <avr/iom8515.h>
#elif defined (__AVR_ATmega8535__)
@@ -284,28 +308,42 @@
# include <avr/io2313.h>
#elif defined (__AVR_ATtiny2313__)
# include <avr/iotn2313.h>
+#elif defined (__AVR_ATtiny2313A__)
+# include <avr/iotn2313a.h>
#elif defined (__AVR_ATtiny13__)
# include <avr/iotn13.h>
#elif defined (__AVR_ATtiny13A__)
# include <avr/iotn13a.h>
#elif defined (__AVR_ATtiny25__)
# include <avr/iotn25.h>
+#elif defined (__AVR_ATtiny4313__)
+# include <avr/iotn4313.h>
#elif defined (__AVR_ATtiny45__)
# include <avr/iotn45.h>
#elif defined (__AVR_ATtiny85__)
# include <avr/iotn85.h>
#elif defined (__AVR_ATtiny24__)
# include <avr/iotn24.h>
+#elif defined (__AVR_ATtiny24A__)
+# include <avr/iotn24a.h>
#elif defined (__AVR_ATtiny44__)
# include <avr/iotn44.h>
+#elif defined (__AVR_ATtiny44A__)
+# include <avr/iotn44a.h>
#elif defined (__AVR_ATtiny84__)
# include <avr/iotn84.h>
#elif defined (__AVR_ATtiny261__)
# include <avr/iotn261.h>
+#elif defined (__AVR_ATtiny261A__)
+# include <avr/iotn261a.h>
#elif defined (__AVR_ATtiny461__)
# include <avr/iotn461.h>
+#elif defined (__AVR_ATtiny461A__)
+# include <avr/iotn461a.h>
#elif defined (__AVR_ATtiny861__)
# include <avr/iotn861.h>
+#elif defined (__AVR_ATtiny861A__)
+# include <avr/iotn861a.h>
#elif defined (__AVR_ATtiny43U__)
# include <avr/iotn43u.h>
#elif defined (__AVR_ATtiny48__)
@@ -330,14 +368,24 @@
# include <avr/iox64a1.h>
#elif defined (__AVR_ATxmega64A3__)
# include <avr/iox64a3.h>
+#elif defined (__AVR_ATxmega64D3__)
+# include <avr/iox64d3.h>
#elif defined (__AVR_ATxmega128A1__)
# include <avr/iox128a1.h>
#elif defined (__AVR_ATxmega128A3__)
# include <avr/iox128a3.h>
+#elif defined (__AVR_ATxmega128D3__)
+# include <avr/iox128d3.h>
+#elif defined (__AVR_ATxmega192A3__)
+# include <avr/iox192a3.h>
+#elif defined (__AVR_ATxmega192D3__)
+# include <avr/iox192d3.h>
#elif defined (__AVR_ATxmega256A3__)
# include <avr/iox256a3.h>
#elif defined (__AVR_ATxmega256A3B__)
# include <avr/iox256a3b.h>
+#elif defined (__AVR_ATxmega256D3__)
+# include <avr/iox256d3.h>
#elif defined (__AVR_ATA6289__)
# include <avr/ioa6289.h>
/* avr1: the following only supported for assembler programs */
diff -u rtems/cpukit/score/cpu/avr/avr/io1200.h:1.2 rtems/cpukit/score/cpu/avr/avr/io1200.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io1200.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io1200.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io1200.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef __ASSEMBLER__
# warning "MCU not supported by the C compiler"
diff -u rtems/cpukit/score/cpu/avr/avr/io2313.h:1.2 rtems/cpukit/score/cpu/avr/avr/io2313.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io2313.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io2313.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io2313.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -190,48 +190,48 @@
/*
* The Register Bit names are represented by their bit number (0-7).
- */
-
+ */
+
/* General Interrupt MaSK register */
#define INT1 7
#define INT0 6
-
+
/* General Interrupt Flag Register */
#define INTF1 7
#define INTF0 6
-
-/* Timer/Counter Interrupt MaSK register */
+
+/* Timer/Counter Interrupt MaSK register */
#define TOIE1 7
#define OCIE1A 6
-#define TICIE 3 /* old name */
+#define TICIE 3 /* old name */
#define TICIE1 3
#define TOIE0 1
-
-/* Timer/Counter Interrupt Flag register */
+
+/* Timer/Counter Interrupt Flag register */
#define TOV1 7
#define OCF1A 6
#define ICF1 3
#define TOV0 1
-
-/* MCU general Control Register */
+
+/* MCU general Control Register */
#define SE 5
#define SM 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
-
+
/* Timer/Counter 0 Control Register */
#define CS02 2
#define CS01 1
#define CS00 0
-
+
/* Timer/Counter 1 Control Register */
#define COM1A1 7
#define COM1A0 6
#define PWM11 1
#define PWM10 0
-
+
/* Timer/Counter 1 Control and Status Register */
#define ICNC1 7
#define ICES1 6
@@ -239,20 +239,20 @@
#define CS12 2
#define CS11 1
#define CS10 0
-
+
/* Watchdog Timer Control Register */
#define WDTOE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
-
+
/* EEPROM Control Register */
#define EEMWE 2
#define EEWE 1
#define EERE 0
-
-/* Data Register, Port B */
+
+/* Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
@@ -261,7 +261,7 @@
#define PB2 2
#define PB1 1
#define PB0 0
-
+
/* Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
@@ -271,7 +271,7 @@
#define DDB2 2
#define DDB1 1
#define DDB0 0
-
+
/* Input Pins, Port B */
#define PINB7 7
#define PINB6 6
@@ -281,7 +281,7 @@
#define PINB2 2
#define PINB1 1
#define PINB0 0
-
+
/* Data Register, Port D */
#define PD6 6
#define PD5 5
@@ -290,7 +290,7 @@
#define PD2 2
#define PD1 1
#define PD0 0
-
+
/* Data Direction Register, Port D */
#define DDD6 6
#define DDD5 5
@@ -299,7 +299,7 @@
#define DDD2 2
#define DDD1 1
#define DDD0 0
-
+
/* Input Pins, Port D */
#define PIND6 6
#define PIND5 5
@@ -308,14 +308,14 @@
#define PIND2 2
#define PIND1 1
#define PIND0 0
-
+
/* UART Status Register */
#define RXC 7
#define TXC 6
#define UDRE 5
#define FE 4
#define DOR 3
-
+
/* UART Control Register */
#define RXCIE 7
#define TXCIE 6
@@ -325,8 +325,8 @@
#define CHR9 2
#define RXB8 1
#define TXB8 0
-
-/* Analog Comparator Control and Status Register */
+
+/* Analog Comparator Control and Status Register */
#define ACD 7
#define ACO 5
#define ACI 4
@@ -340,8 +340,8 @@
#define EEMWE 2
#define EEWE 1
#define EERE 0
-
-/* Constants */
+
+/* Constants */
#define RAMEND 0xDF
#define XRAMEND RAMEND
#define E2END 0x7F
diff -u rtems/cpukit/score/cpu/avr/avr/io2323.h:1.2 rtems/cpukit/score/cpu/avr/avr/io2323.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io2323.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io2323.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io2323.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io2333.h:1.2 rtems/cpukit/score/cpu/avr/avr/io2333.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io2333.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io2333.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io2333.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io2343.h:1.2 rtems/cpukit/score/cpu/avr/avr/io2343.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io2343.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io2343.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io2343.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io43u32x.h:1.2 rtems/cpukit/score/cpu/avr/avr/io43u32x.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io43u32x.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io43u32x.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io43u32x.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -71,7 +71,7 @@
#define DDRE _SFR_IO8(0x02)
/* Data Register, Port E */
-#define PORTE _SFR_IO8(0x03)
+#define PORTE _SFR_IO8(0x03)
/* SPI Control Register */
#define SPCR _SFR_IO8(0x0D)
diff -u rtems/cpukit/score/cpu/avr/avr/io43u35x.h:1.2 rtems/cpukit/score/cpu/avr/avr/io43u35x.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io43u35x.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io43u35x.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io43u35x.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -417,7 +417,7 @@
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
-#define ADPS0 0
+#define ADPS0 0
/* Constants */
#define RAMEND 0x045F /*Last On-Chip SRAM Location*/
diff -u rtems/cpukit/score/cpu/avr/avr/io4414.h:1.2 rtems/cpukit/score/cpu/avr/avr/io4414.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io4414.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io4414.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io4414.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io4433.h:1.2 rtems/cpukit/score/cpu/avr/avr/io4433.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io4433.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io4433.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io4433.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io4434.h:1.2 rtems/cpukit/score/cpu/avr/avr/io4434.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io4434.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io4434.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io4434.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io76c711.h:1.2 rtems/cpukit/score/cpu/avr/avr/io76c711.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io76c711.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io76c711.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io76c711.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io8515.h:1.2 rtems/cpukit/score/cpu/avr/avr/io8515.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io8515.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io8515.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io8515.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io8534.h:1.2 rtems/cpukit/score/cpu/avr/avr/io8534.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io8534.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io8534.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io8534.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io8535.h:1.2 rtems/cpukit/score/cpu/avr/avr/io8535.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io8535.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io8535.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io8535.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/io86r401.h:1.2 rtems/cpukit/score/cpu/avr/avr/io86r401.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io86r401.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io86r401.h Mon May 10 11:31:20 2010
@@ -83,7 +83,7 @@
#define BTCNT _SFR_IO8(0x20)
-/*
+/*
NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
you may want to remove the leading D.
*/
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwm1.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwm1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwm1.h:1.2 Mon Nov 30 10:01:43 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwm1.h Mon May 10 11:31:20 2010
@@ -46,7 +46,7 @@
# define _AVR_IOXXX_H_ "iopwm1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -1115,7 +1115,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
#endif /* _AVR_IOPWM1_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwm216.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwm216.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwm216.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwm216.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io90pwm216.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -1169,7 +1169,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwm2b.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwm2b.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwm2b.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwm2b.h Mon May 10 11:31:20 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "io90pwm2b.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IO90PWM2B_H_
@@ -80,7 +80,7 @@
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
-
+
#define PINC _SFR_IO8(0x06)
#define PINC0 0
#define PINC1 1
@@ -386,7 +386,7 @@
#define WDP0 0
#define WDP1 1
#define WDP2 2
-#define WDE3 3
+#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
@@ -818,7 +818,7 @@
#define STP0 0
#define STP1 1
#define F1617 2
-#define FEM 3
+#define FEM 3
#define MUBRR _SFR_MEM16(0xCC)
@@ -1363,7 +1363,7 @@
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
@@ -1380,7 +1380,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwm316.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwm316.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwm316.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwm316.h Mon May 10 11:31:20 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io90pwm316.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -1212,7 +1212,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwm3b.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwm3b.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwm3b.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwm3b.h Mon May 10 11:31:20 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "io90pwm3b.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IO90PWM3B_H_
@@ -80,7 +80,7 @@
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
-
+
#define PINC _SFR_IO8(0x06)
#define PINC0 0
#define PINC1 1
@@ -386,7 +386,7 @@
#define WDP0 0
#define WDP1 1
#define WDP2 2
-#define WDE3 3
+#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
@@ -818,7 +818,7 @@
#define STP0 0
#define STP1 1
#define F1617 2
-#define FEM 3
+#define FEM 3
#define MUBRR _SFR_MEM16(0xCC)
@@ -1363,7 +1363,7 @@
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
@@ -1380,7 +1380,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwm81.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwm81.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwm81.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwm81.h Mon May 10 11:31:21 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "io90pwm81.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_AT90PWM81_H_
diff -u rtems/cpukit/score/cpu/avr/avr/io90pwmx.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90pwmx.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90pwmx.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90pwmx.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "io90pwmX.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -1365,7 +1365,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
#endif /* _AVR_IO90PWMX_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/io90scr100.h:1.2 rtems/cpukit/score/cpu/avr/avr/io90scr100.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/io90scr100.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/io90scr100.h Mon May 10 11:31:21 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "io90scr100.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_AT90SCR100_H_
diff -u rtems/cpukit/score/cpu/avr/avr/ioa6289.h:1.2 rtems/cpukit/score/cpu/avr/avr/ioa6289.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/ioa6289.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/ioa6289.h Mon May 10 11:31:21 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "ioa6289.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATA6289_H_
diff -u rtems/cpukit/score/cpu/avr/avr/ioat94k.h:1.2 rtems/cpukit/score/cpu/avr/avr/ioat94k.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/ioat94k.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/ioat94k.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "ioat94k.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -210,33 +210,33 @@
/* Interrupt vectors */
-#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */
+#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */
#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */
-#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */
+#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */
#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */
-#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */
+#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */
#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */
-#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */
+#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */
#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */
-#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */
-#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */
-#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */
-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */
-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */
-#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */
-#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */
-#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */
-#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */
-#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */
-#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */
-#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */
+#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */
+#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */
+#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */
+#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */
+#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */
+#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */
+#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */
+#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */
+#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */
+#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */
+#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */
+#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */
#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */
#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */
#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */
-#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */
-#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */
-#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */
-#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */
+#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */
+#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */
+#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */
+#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */
#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */
#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */
#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */
diff -u rtems/cpukit/score/cpu/avr/avr/iocan128.h:1.2 rtems/cpukit/score/cpu/avr/avr/iocan128.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iocan128.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iocan128.h Mon May 10 11:31:21 2010
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iocan32.h:1.2 rtems/cpukit/score/cpu/avr/avr/iocan32.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iocan32.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iocan32.h Mon May 10 11:31:21 2010
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iocan64.h:1.2 rtems/cpukit/score/cpu/avr/avr/iocan64.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iocan64.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iocan64.h Mon May 10 11:31:21 2010
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iocanxx.h:1.2 rtems/cpukit/score/cpu/avr/avr/iocanxx.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iocanxx.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iocanxx.h Mon May 10 11:31:21 2010
@@ -53,7 +53,7 @@
# define _AVR_IOXXX_H_ "iocanxx.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers and bit definitions. */
@@ -952,9 +952,9 @@
#define ADPS0 0
/* End Register Bits */
-/*
- The ADHSM bit has been removed from all documentation,
- as being not needed at all since the comparator has proven
+/*
+ The ADHSM bit has been removed from all documentation,
+ as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
diff -u rtems/cpukit/score/cpu/avr/avr/iom103.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom103.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom103.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom103.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom103.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u rtems/cpukit/score/cpu/avr/avr/iom128.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom128.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom128.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom128.h Mon May 10 11:31:21 2010
@@ -31,7 +31,7 @@
/* $Id$ */
-/* avr/iom128.h - defines for ATmega128
+/* avr/iom128.h - defines for ATmega128
As of 2002-08-27:
- This should be up to date with data sheet 2467E-AVR-05/02 */
@@ -49,7 +49,7 @@
# define _AVR_IOXXX_H_ "iom128.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -794,9 +794,9 @@
#define WDP1 1
#define WDP0 0
-/*
- The ADHSM bit has been removed from all documentation,
- as being not needed at all since the comparator has proven
+/*
+ The ADHSM bit has been removed from all documentation,
+ as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
@@ -966,7 +966,7 @@
#define PINA5 5
#define PINA4 4
#define PINA3 3
-#define PINA2 2
+#define PINA2 2
#define PINA1 1
#define PINA0 0
@@ -996,7 +996,7 @@
#define PINB5 5
#define PINB4 4
#define PINB3 3
-#define PINB2 2
+#define PINB2 2
#define PINB1 1
#define PINB0 0
@@ -1026,7 +1026,7 @@
#define PINC5 5
#define PINC4 4
#define PINC3 3
-#define PINC2 2
+#define PINC2 2
#define PINC1 1
#define PINC0 0
@@ -1056,7 +1056,7 @@
#define PIND5 5
#define PIND4 4
#define PIND3 3
-#define PIND2 2
+#define PIND2 2
#define PIND1 1
#define PIND0 0
@@ -1086,7 +1086,7 @@
#define PINE5 5
#define PINE4 4
#define PINE3 3
-#define PINE2 2
+#define PINE2 2
#define PINE1 1
#define PINE0 0
@@ -1116,7 +1116,7 @@
#define PINF5 5
#define PINF4 4
#define PINF3 3
-#define PINF2 2
+#define PINF2 2
#define PINF1 1
#define PINF0 0
@@ -1137,7 +1137,7 @@
/* Port G Input Pins - PING */
#define PING4 4
#define PING3 3
-#define PING2 2
+#define PING2 2
#define PING1 1
#define PING0 0
@@ -1191,7 +1191,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom1280.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom1280.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom1280.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom1280.h Mon May 10 11:31:21 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005 Anatoly Sokolov
+/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom1281.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom1281.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom1281.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom1281.h Mon May 10 11:31:21 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005 Anatoly Sokolov
+/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom128rfa1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom128rfa1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom128rfa1.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom128rfa1.h Mon May 10 11:31:21 2010
@@ -52,6 +52,7 @@
#ifndef __ASSEMBLER__
# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
+# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
#endif /* __ASSEMBLER__ */
/*
@@ -413,9 +414,9 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIFR0 {
- unsigned int _tov0 : 1; /* Timer/Counter0 Overflow Flag */
- unsigned int _ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */
- unsigned int _ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */
+ unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */
+ unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */
+ unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */
unsigned int : 5;
};
@@ -435,12 +436,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIFR1 {
- unsigned int _tov1 : 1; /* Timer/Counter1 Overflow Flag */
- unsigned int _ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */
- unsigned int _ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */
- unsigned int _ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */
+ unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */
+ unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */
+ unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */
+ unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */
unsigned int : 1;
- unsigned int _icf1 : 1; /* Timer/Counter1 Input Capture Flag */
+ unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */
unsigned int : 2;
};
@@ -462,9 +463,9 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIFR2 {
- unsigned int _tov2 : 1; /* Timer/Counter2 Overflow Flag */
- unsigned int _ocf2a : 1; /* Output Compare Flag 2 A */
- unsigned int _ocf2b : 1; /* Output Compare Flag 2 B */
+ unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */
+ unsigned int ocf2a : 1; /* Output Compare Flag 2 A */
+ unsigned int ocf2b : 1; /* Output Compare Flag 2 B */
unsigned int : 5;
};
@@ -484,12 +485,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIFR3 {
- unsigned int _tov3 : 1; /* Timer/Counter3 Overflow Flag */
- unsigned int _ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */
- unsigned int _ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */
- unsigned int _ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */
+ unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */
+ unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */
+ unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */
+ unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */
unsigned int : 1;
- unsigned int _icf3 : 1; /* Timer/Counter3 Input Capture Flag */
+ unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */
unsigned int : 2;
};
@@ -511,12 +512,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIFR4 {
- unsigned int _tov4 : 1; /* Timer/Counter4 Overflow Flag */
- unsigned int _ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */
- unsigned int _ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */
- unsigned int _ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */
+ unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */
+ unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */
+ unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */
+ unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */
unsigned int : 1;
- unsigned int _icf4 : 1; /* Timer/Counter4 Input Capture Flag */
+ unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */
unsigned int : 2;
};
@@ -538,12 +539,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIFR5 {
- unsigned int _tov5 : 1; /* Timer/Counter5 Overflow Flag */
- unsigned int _ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */
- unsigned int _ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */
- unsigned int _ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */
+ unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */
+ unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */
+ unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */
+ unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */
unsigned int : 1;
- unsigned int _icf5 : 1; /* Timer/Counter5 Input Capture Flag */
+ unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */
unsigned int : 2;
};
@@ -565,7 +566,7 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PCIFR {
- unsigned int _pcif : 3; /* Pin Change Interrupt Flag 2 */
+ unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */
unsigned int : 5;
};
@@ -585,7 +586,7 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_EIFR {
- unsigned int _intf : 8; /* External Interrupt Flag */
+ unsigned int intf : 8; /* External Interrupt Flag */
};
#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
@@ -609,7 +610,7 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_EIMSK {
- unsigned int _int : 8; /* External Interrupt Request Enable */
+ unsigned int intm : 8; /* External Interrupt Request Enable */
};
#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
@@ -633,7 +634,7 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_GPIOR0 {
- unsigned int _gpior0 : 8; /* General Purpose I/O Register 0 Value */
+ unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */
};
#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
@@ -666,11 +667,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_EECR {
- unsigned int _eere : 1; /* EEPROM Read Enable */
- unsigned int _eepe : 1; /* EEPROM Programming Enable */
- unsigned int _eempe : 1; /* EEPROM Master Write Enable */
- unsigned int _eerie : 1; /* EEPROM Ready Interrupt Enable */
- unsigned int _eepm : 2; /* EEPROM Programming Mode */
+ unsigned int eere : 1; /* EEPROM Read Enable */
+ unsigned int eepe : 1; /* EEPROM Programming Enable */
+ unsigned int eempe : 1; /* EEPROM Master Write Enable */
+ unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */
+ unsigned int eepm : 2; /* EEPROM Programming Mode */
unsigned int : 2;
};
@@ -712,10 +713,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_GTCCR {
- unsigned int _psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */
- unsigned int _psrasy : 1; /* Prescaler Reset Timer/Counter2 */
+ unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */
+ unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */
unsigned int : 5;
- unsigned int _tsm : 1; /* Timer/Counter Synchronization Mode */
+ unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */
};
#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
@@ -736,10 +737,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR0A {
- unsigned int _wgm0 : 2; /* Waveform Generation Mode */
+ unsigned int wgm0 : 2; /* Waveform Generation Mode */
unsigned int : 2;
- unsigned int _com0b : 2; /* Compare Match Output B Mode */
- unsigned int _com0a : 2; /* Compare Match Output A Mode */
+ unsigned int com0b : 2; /* Compare Match Output B Mode */
+ unsigned int com0a : 2; /* Compare Match Output A Mode */
};
#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
@@ -761,11 +762,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR0B {
- unsigned int _cs0 : 3; /* Clock Select */
- unsigned int _wgm02 : 1; /* */
+ unsigned int cs0 : 3; /* Clock Select */
+ unsigned int wgm02 : 1; /* */
unsigned int : 2;
- unsigned int _foc0b : 1; /* Force Output Compare B */
- unsigned int _foc0a : 1; /* Force Output Compare A */
+ unsigned int foc0b : 1; /* Force Output Compare B */
+ unsigned int foc0a : 1; /* Force Output Compare A */
};
#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
@@ -829,7 +830,7 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_GPIOR1 {
- unsigned int _gpior1 : 8; /* General Purpose I/O Register 1 Value */
+ unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */
};
#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
@@ -853,7 +854,7 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_GPIOR2 {
- unsigned int _gpior2 : 8; /* General Purpose I/O Register 2 Value */
+ unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */
};
#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
@@ -877,13 +878,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SPCR {
- unsigned int _spr : 2; /* SPI Clock Rate Select 1 and 0 */
- unsigned int _cpha : 1; /* Clock Phase */
- unsigned int _cpol : 1; /* Clock polarity */
- unsigned int _mstr : 1; /* Master/Slave Select */
- unsigned int _dord : 1; /* Data Order */
- unsigned int _spe : 1; /* SPI Enable */
- unsigned int _spie : 1; /* SPI Interrupt Enable */
+ unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */
+ unsigned int cpha : 1; /* Clock Phase */
+ unsigned int cpol : 1; /* Clock polarity */
+ unsigned int mstr : 1; /* Master/Slave Select */
+ unsigned int dord : 1; /* Data Order */
+ unsigned int spe : 1; /* SPI Enable */
+ unsigned int spie : 1; /* SPI Interrupt Enable */
};
#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
@@ -907,10 +908,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SPSR {
- unsigned int _spi2x : 1; /* Double SPI Speed Bit */
+ unsigned int spi2x : 1; /* Double SPI Speed Bit */
unsigned int : 5;
- unsigned int _wcol : 1; /* Write Collision Flag */
- unsigned int _spif : 1; /* SPI Interrupt Flag */
+ unsigned int wcol : 1; /* Write Collision Flag */
+ unsigned int spif : 1; /* SPI Interrupt Flag */
};
#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
@@ -943,13 +944,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ACSR {
- unsigned int _acis : 2; /* Analog Comparator Interrupt Mode Select */
- unsigned int _acic : 1; /* Analog Comparator Input Capture Enable */
- unsigned int _acie : 1; /* Analog Comparator Interrupt Enable */
- unsigned int _aci : 1; /* Analog Comparator Interrupt Flag */
- unsigned int _aco : 1; /* Analog Compare Output */
- unsigned int _acbg : 1; /* Analog Comparator Bandgap Select */
- unsigned int _acd : 1; /* Analog Comparator Disable */
+ unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */
+ unsigned int acic : 1; /* Analog Comparator Input Capture Enable */
+ unsigned int acie : 1; /* Analog Comparator Interrupt Enable */
+ unsigned int aci : 1; /* Analog Comparator Interrupt Flag */
+ unsigned int aco : 1; /* Analog Compare Output */
+ unsigned int acbg : 1; /* Analog Comparator Bandgap Select */
+ unsigned int acd : 1; /* Analog Comparator Disable */
};
#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
@@ -970,6 +971,16 @@
/* On-Chip Debug Register */
#define OCDR _SFR_IO8(0x31)
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_OCDR {
+ unsigned int ocdr : 8; /* On-Chip Debug Register Data */
+};
+
+#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
+
+#endif /* __ASSEMBLER__ */
+
/* OCDR */
#define OCDR0 0
@@ -988,8 +999,8 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SMCR {
- unsigned int _se : 1; /* Sleep Enable */
- unsigned int _sm : 3; /* Sleep Mode Select bits */
+ unsigned int se : 1; /* Sleep Enable */
+ unsigned int sm : 3; /* Sleep Mode Select bits */
unsigned int : 4;
};
@@ -1010,11 +1021,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_MCUSR {
- unsigned int _porf : 1; /* Power-on Reset Flag */
- unsigned int _extrf : 1; /* External Reset Flag */
- unsigned int _borf : 1; /* Brown-out Reset Flag */
- unsigned int _wdrf : 1; /* Watchdog Reset Flag */
- unsigned int _jtrf : 1; /* JTAG Reset Flag */
+ unsigned int porf : 1; /* Power-on Reset Flag */
+ unsigned int extrf : 1; /* External Reset Flag */
+ unsigned int borf : 1; /* Brown-out Reset Flag */
+ unsigned int wdrf : 1; /* Watchdog Reset Flag */
+ unsigned int jtrf : 1; /* JTAG Reset Flag */
unsigned int : 3;
};
@@ -1036,12 +1047,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_MCUCR {
- unsigned int _ivce : 1; /* Interrupt Vector Change Enable */
- unsigned int _ivsel : 1; /* Interrupt Vector Select */
+ unsigned int ivce : 1; /* Interrupt Vector Change Enable */
+ unsigned int ivsel : 1; /* Interrupt Vector Select */
unsigned int : 2;
- unsigned int _pud : 1; /* Pull-up Disable */
+ unsigned int pud : 1; /* Pull-up Disable */
unsigned int : 2;
- unsigned int _jtd : 1; /* JTAG Interface Disable */
+ unsigned int jtd : 1; /* JTAG Interface Disable */
};
#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
@@ -1061,14 +1072,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SPMCSR {
- unsigned int _spmen : 1; /* Store Program Memory Enable */
- unsigned int _pgers : 1; /* Page Erase */
- unsigned int _pgwrt : 1; /* Page Write */
- unsigned int _blbset : 1; /* Boot Lock Bit Set */
- unsigned int _rwwsre : 1; /* Read While Write Section Read Enable */
- unsigned int _sigrd : 1; /* Signature Row Read */
- unsigned int _rwwsb : 1; /* Read While Write Section Busy */
- unsigned int _spmie : 1; /* SPM Interrupt Enable */
+ unsigned int spmen : 1; /* Store Program Memory Enable */
+ unsigned int pgers : 1; /* Page Erase */
+ unsigned int pgwrt : 1; /* Page Write */
+ unsigned int blbset : 1; /* Boot Lock Bit Set */
+ unsigned int rwwsre : 1; /* Read While Write Section Read Enable */
+ unsigned int sigrd : 1; /* Signature Row Read */
+ unsigned int rwwsb : 1; /* Read While Write Section Busy */
+ unsigned int spmie : 1; /* SPM Interrupt Enable */
};
#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
@@ -1089,6 +1100,17 @@
/* Extended Z-pointer Register for ELPM/SPM */
#define RAMPZ _SFR_IO8(0x3B)
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_RAMPZ {
+ unsigned int rampz : 2; /* Extended Z-Pointer Value */
+ unsigned int : 6;
+};
+
+#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
+
+#endif /* __ASSEMBLER__ */
+
/* RAMPZ */
#define RAMPZ0 0
@@ -1105,14 +1127,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SREG {
- unsigned int _c : 1; /* Carry Flag */
- unsigned int _z : 1; /* Zero Flag */
- unsigned int _n : 1; /* Negative Flag */
- unsigned int _v : 1; /* Two's Complement Overflow Flag */
- unsigned int _s : 1; /* Sign Bit */
- unsigned int _h : 1; /* Half Carry Flag */
- unsigned int _t : 1; /* Bit Copy Storage */
- unsigned int _i : 1; /* Global Interrupt Enable */
+ unsigned int c : 1; /* Carry Flag */
+ unsigned int z : 1; /* Zero Flag */
+ unsigned int n : 1; /* Negative Flag */
+ unsigned int v : 1; /* Two's Complement Overflow Flag */
+ unsigned int s : 1; /* Sign Bit */
+ unsigned int h : 1; /* Half Carry Flag */
+ unsigned int t : 1; /* Bit Copy Storage */
+ unsigned int i : 1; /* Global Interrupt Enable */
};
#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
@@ -1136,15 +1158,15 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_WDTCSR {
- unsigned int _wdp : 3; /* Watchdog Timer Prescaler bits */
- unsigned int _wde : 1; /* Watch Dog Enable */
- unsigned int _wdce : 1; /* Watchdog Change Enable */
+ unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */
+ unsigned int wde : 1; /* Watch Dog Enable */
+ unsigned int wdce : 1; /* Watchdog Change Enable */
unsigned int : 1;
- unsigned int _wdie : 1; /* Watchdog Timeout Interrupt Enable */
- unsigned int _wdif : 1; /* Watchdog Timeout Interrupt Flag */
+ unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */
+ unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */
};
-#define WDTCSR_struct _SFR_IO8_STRUCT(0x60, struct __reg_WDTCSR)
+#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
#endif /* __ASSEMBLER__ */
@@ -1165,12 +1187,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_CLKPR {
- unsigned int _clkps : 4; /* Clock Prescaler Select Bits */
+ unsigned int clkps : 4; /* Clock Prescaler Select Bits */
unsigned int : 3;
- unsigned int _clkpce : 1; /* Clock Prescaler Change Enable */
+ unsigned int clkpce : 1; /* Clock Prescaler Change Enable */
};
-#define CLKPR_struct _SFR_IO8_STRUCT(0x61, struct __reg_CLKPR)
+#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
#endif /* __ASSEMBLER__ */
@@ -1188,11 +1210,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PRR2 {
- unsigned int _prram : 4; /* Power Reduction SRAM 3 */
+ unsigned int prram : 4; /* Power Reduction SRAM 3 */
unsigned int : 4;
};
-#define PRR2_struct _SFR_IO8_STRUCT(0x63, struct __reg_PRR2)
+#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
#endif /* __ASSEMBLER__ */
@@ -1209,17 +1231,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PRR0 {
- unsigned int _pradc : 1; /* Power Reduction ADC */
- unsigned int _prusart0 : 1; /* Power Reduction USART */
- unsigned int _prspi : 1; /* Power Reduction Serial Peripheral Interface */
- unsigned int _prtim1 : 1; /* Power Reduction Timer/Counter1 */
- unsigned int _prpga : 1; /* Power Reduction PGA */
- unsigned int _prtim0 : 1; /* Power Reduction Timer/Counter0 */
- unsigned int _prtim2 : 1; /* Power Reduction Timer/Counter2 */
- unsigned int _prtwi : 1; /* Power Reduction TWI */
+ unsigned int pradc : 1; /* Power Reduction ADC */
+ unsigned int prusart0 : 1; /* Power Reduction USART */
+ unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */
+ unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */
+ unsigned int prpga : 1; /* Power Reduction PGA */
+ unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */
+ unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */
+ unsigned int prtwi : 1; /* Power Reduction TWI */
};
-#define PRR0_struct _SFR_IO8_STRUCT(0x64, struct __reg_PRR0)
+#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
#endif /* __ASSEMBLER__ */
@@ -1240,15 +1262,15 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PRR1 {
- unsigned int _prusart : 3; /* Reserved */
- unsigned int _prtim3 : 1; /* Power Reduction Timer/Counter3 */
- unsigned int _prtim4 : 1; /* Power Reduction Timer/Counter4 */
- unsigned int _prtim5 : 1; /* Power Reduction Timer/Counter5 */
- unsigned int _prtrx24 : 1; /* Power Reduction Transceiver */
+ unsigned int prusart : 3; /* Reserved */
+ unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */
+ unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */
+ unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */
+ unsigned int prtrx24 : 1; /* Power Reduction Transceiver */
unsigned int : 1;
};
-#define PRR1_struct _SFR_IO8_STRUCT(0x65, struct __reg_PRR1)
+#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
#endif /* __ASSEMBLER__ */
@@ -1265,6 +1287,16 @@
/* Oscillator Calibration Value */
#define OSCCAL _SFR_MEM8(0x66)
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_OSCCAL {
+ unsigned int cal : 8; /* Oscillator Calibration Tuning Value */
+};
+
+#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
+
+#endif /* __ASSEMBLER__ */
+
/* OSCCAL */
#define CAL0 0
@@ -1279,6 +1311,18 @@
/* Reference Voltage Calibration Register */
#define BGCR _SFR_MEM8(0x67)
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_BGCR {
+ unsigned int bgcal : 3; /* Coarse Calibration Bits */
+ unsigned int bgcal_fine : 4; /* Fine Calibration Bits */
+ unsigned int : 1;
+};
+
+#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
+
+#endif /* __ASSEMBLER__ */
+
/* BGCR */
#define BGCAL0 0
@@ -1295,11 +1339,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PCICR {
- unsigned int _pcie : 3; /* Pin Change Interrupt Enable 2 */
+ unsigned int pcie : 3; /* Pin Change Interrupt Enable 2 */
unsigned int : 5;
};
-#define PCICR_struct _SFR_IO8_STRUCT(0x68, struct __reg_PCICR)
+#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
#endif /* __ASSEMBLER__ */
@@ -1315,13 +1359,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_EICRA {
- unsigned int _isc0 : 2; /* External Interrupt 0 Sense Control Bit */
- unsigned int _isc1 : 2; /* External Interrupt 1 Sense Control Bit */
- unsigned int _isc2 : 2; /* External Interrupt 2 Sense Control Bit */
- unsigned int _isc3 : 2; /* External Interrupt 3 Sense Control Bit */
+ unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */
+ unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */
+ unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */
+ unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */
};
-#define EICRA_struct _SFR_IO8_STRUCT(0x69, struct __reg_EICRA)
+#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
#endif /* __ASSEMBLER__ */
@@ -1342,13 +1386,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_EICRB {
- unsigned int _isc4 : 2; /* External Interrupt 4 Sense Control Bit */
- unsigned int _isc5 : 2; /* External Interrupt 5 Sense Control Bit */
- unsigned int _isc6 : 2; /* External Interrupt 6 Sense Control Bit */
- unsigned int _isc7 : 2; /* External Interrupt 7 Sense Control Bit */
+ unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */
+ unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */
+ unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */
+ unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */
};
-#define EICRB_struct _SFR_IO8_STRUCT(0x6a, struct __reg_EICRB)
+#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
#endif /* __ASSEMBLER__ */
@@ -1380,6 +1424,17 @@
/* Pin Change Mask Register 1 */
#define PCMSK1 _SFR_MEM8(0x6C)
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_PCMSK1 {
+ unsigned int pcint : 2; /* Pin Change Enable Mask */
+ unsigned int pcint1 : 6; /* Pin Change Enable Mask */
+};
+
+#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
+
+#endif /* __ASSEMBLER__ */
+
/* PCMSK1 */
#define PCINT8 0
@@ -1394,6 +1449,17 @@
/* Pin Change Mask Register 2 */
#define PCMSK2 _SFR_MEM8(0x6D)
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_PCMSK2 {
+ unsigned int pcint1 : 4; /* Pin Change Enable Mask */
+ unsigned int pcint2 : 4; /* Pin Change Enable Mask */
+};
+
+#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
+
+#endif /* __ASSEMBLER__ */
+
/* PCMSK2 */
#define PCINT16 0
@@ -1411,13 +1477,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIMSK0 {
- unsigned int _toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */
- unsigned int _ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */
- unsigned int _ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */
+ unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */
+ unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */
+ unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */
unsigned int : 5;
};
-#define TIMSK0_struct _SFR_IO8_STRUCT(0x6e, struct __reg_TIMSK0)
+#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
#endif /* __ASSEMBLER__ */
@@ -1433,16 +1499,16 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIMSK1 {
- unsigned int _toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */
- unsigned int _ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */
- unsigned int _ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */
- unsigned int _ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */
+ unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */
+ unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */
+ unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */
+ unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */
unsigned int : 1;
- unsigned int _icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */
+ unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */
unsigned int : 2;
};
-#define TIMSK1_struct _SFR_IO8_STRUCT(0x6f, struct __reg_TIMSK1)
+#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
#endif /* __ASSEMBLER__ */
@@ -1460,13 +1526,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIMSK2 {
- unsigned int _toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */
- unsigned int _ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */
- unsigned int _ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */
+ unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */
+ unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */
+ unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */
unsigned int : 5;
};
-#define TIMSK2_struct _SFR_IO8_STRUCT(0x70, struct __reg_TIMSK2)
+#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
#endif /* __ASSEMBLER__ */
@@ -1483,16 +1549,16 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIMSK3 {
- unsigned int _toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */
- unsigned int _ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */
- unsigned int _ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */
- unsigned int _ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */
+ unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */
+ unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */
+ unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */
+ unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */
unsigned int : 1;
- unsigned int _icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */
+ unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */
unsigned int : 2;
};
-#define TIMSK3_struct _SFR_IO8_STRUCT(0x71, struct __reg_TIMSK3)
+#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
#endif /* __ASSEMBLER__ */
@@ -1510,16 +1576,16 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIMSK4 {
- unsigned int _toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */
- unsigned int _ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */
- unsigned int _ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */
- unsigned int _ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */
+ unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */
+ unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */
+ unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */
+ unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */
unsigned int : 1;
- unsigned int _icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */
+ unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */
unsigned int : 2;
};
-#define TIMSK4_struct _SFR_IO8_STRUCT(0x72, struct __reg_TIMSK4)
+#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
#endif /* __ASSEMBLER__ */
@@ -1537,16 +1603,16 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TIMSK5 {
- unsigned int _toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */
- unsigned int _ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */
- unsigned int _ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */
- unsigned int _ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */
+ unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */
+ unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */
+ unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */
+ unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */
unsigned int : 1;
- unsigned int _icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */
+ unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */
unsigned int : 2;
};
-#define TIMSK5_struct _SFR_IO8_STRUCT(0x73, struct __reg_TIMSK5)
+#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
#endif /* __ASSEMBLER__ */
@@ -1558,17 +1624,40 @@
#define OCIE5C 3
#define ICIE5 5
+/* Flash Extended-Mode Control-Register */
+#define NEMCR _SFR_MEM8(0x75)
+
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_NEMCR {
+ unsigned int : 4;
+ unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */
+ unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */
+ unsigned int : 1;
+};
+
+#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
+
+#endif /* __ASSEMBLER__ */
+
+ /* NEMCR */
+
+#define AEAM0 4
+#define AEAM1 5
+#define ENEAM 6
+
/* The ADC Control and Status Register C */
#define ADCSRC _SFR_MEM8(0x77)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ADCSRC {
- unsigned int _adsut : 6; /* ADC Start-up Time */
- unsigned int _adtht : 2; /* ADC Track-and-Hold Time */
+ unsigned int adsut : 5; /* ADC Start-up Time */
+ unsigned int res0 : 1; /* Reserved */
+ unsigned int adtht : 2; /* ADC Track-and-Hold Time */
};
-#define ADCSRC_struct _SFR_IO8_STRUCT(0x77, struct __reg_ADCSRC)
+#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
#endif /* __ASSEMBLER__ */
@@ -1579,7 +1668,6 @@
#define ADSUT2 2
#define ADSUT3 3
#define ADSUT4 4
-#define ADSUT5 5
#define ADTHT0 6
#define ADTHT1 7
@@ -1599,15 +1687,15 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ADCSRA {
- unsigned int _adps : 3; /* ADC Prescaler Select Bits */
- unsigned int _adie : 1; /* ADC Interrupt Enable */
- unsigned int _adif : 1; /* ADC Interrupt Flag */
- unsigned int _adate : 1; /* ADC Auto Trigger Enable */
- unsigned int _adsc : 1; /* ADC Start Conversion */
- unsigned int _aden : 1; /* ADC Enable */
+ unsigned int adps : 3; /* ADC Prescaler Select Bits */
+ unsigned int adie : 1; /* ADC Interrupt Enable */
+ unsigned int adif : 1; /* ADC Interrupt Flag */
+ unsigned int adate : 1; /* ADC Auto Trigger Enable */
+ unsigned int adsc : 1; /* ADC Start Conversion */
+ unsigned int aden : 1; /* ADC Enable */
};
-#define ADCSRA_struct _SFR_IO8_STRUCT(0x7a, struct __reg_ADCSRA)
+#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
#endif /* __ASSEMBLER__ */
@@ -1628,15 +1716,15 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ADCSRB {
- unsigned int _adts : 3; /* ADC Auto Trigger Source */
- unsigned int _mux5 : 1; /* Analog Channel and Gain Selection Bits */
- unsigned int _acch : 1; /* Analog Channel Change */
- unsigned int _refok : 1; /* Reference Voltage OK */
- unsigned int _acme : 1; /* Analog Comparator Multiplexer Enable */
- unsigned int _avddok : 1; /* AVDD Supply Voltage OK */
+ unsigned int adts : 3; /* ADC Auto Trigger Source */
+ unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */
+ unsigned int acch : 1; /* Analog Channel Change */
+ unsigned int refok : 1; /* Reference Voltage OK */
+ unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */
+ unsigned int avddok : 1; /* AVDD Supply Voltage OK */
};
-#define ADCSRB_struct _SFR_IO8_STRUCT(0x7b, struct __reg_ADCSRB)
+#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
#endif /* __ASSEMBLER__ */
@@ -1657,12 +1745,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ADMUX {
- unsigned int _mux : 5; /* Analog Channel and Gain Selection Bits */
- unsigned int _adlar : 1; /* ADC Left Adjust Result */
- unsigned int _refs : 2; /* Reference Selection Bits */
+ unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */
+ unsigned int adlar : 1; /* ADC Left Adjust Result */
+ unsigned int refs : 2; /* Reference Selection Bits */
};
-#define ADMUX_struct _SFR_IO8_STRUCT(0x7c, struct __reg_ADMUX)
+#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
#endif /* __ASSEMBLER__ */
@@ -1683,17 +1771,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_DIDR2 {
- unsigned int _adc8d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc9d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc10d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc11d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc12d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc13d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc14d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
- unsigned int _adc15d : 1; /* ADC15D:ADC8D: ADC15:8 Digital Input Disable */
+ unsigned int adc8d : 1; /* Reserved Bits */
+ unsigned int adc9d : 1; /* Reserved Bits */
+ unsigned int adc10d : 1; /* Reserved Bits */
+ unsigned int adc11d : 1; /* Reserved Bits */
+ unsigned int adc12d : 1; /* Reserved Bits */
+ unsigned int adc13d : 1; /* Reserved Bits */
+ unsigned int adc14d : 1; /* Reserved Bits */
+ unsigned int adc15d : 1; /* Reserved Bits */
};
-#define DIDR2_struct _SFR_IO8_STRUCT(0x7d, struct __reg_DIDR2)
+#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
#endif /* __ASSEMBLER__ */
@@ -1714,17 +1802,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_DIDR0 {
- unsigned int _adc0d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc1d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc2d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc3d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc4d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc5d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc6d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
- unsigned int _adc7d : 1; /* ADC7D:ADC0D: ADC7:0 Digital Input Disable */
+ unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */
+ unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */
};
-#define DIDR0_struct _SFR_IO8_STRUCT(0x7e, struct __reg_DIDR0)
+#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
#endif /* __ASSEMBLER__ */
@@ -1745,12 +1833,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_DIDR1 {
- unsigned int _ain0d : 1; /* AIN0 Digital Input Disable */
- unsigned int _ain1d : 1; /* AIN1 Digital Input Disable */
+ unsigned int ain0d : 1; /* AIN0 Digital Input Disable */
+ unsigned int ain1d : 1; /* AIN1 Digital Input Disable */
unsigned int : 6;
};
-#define DIDR1_struct _SFR_IO8_STRUCT(0x7f, struct __reg_DIDR1)
+#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
#endif /* __ASSEMBLER__ */
@@ -1765,13 +1853,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR1A {
- unsigned int _wgm1 : 2; /* Waveform Generation Mode */
- unsigned int _com1c : 2; /* Compare Output Mode for Channel C */
- unsigned int _com1b : 2; /* Compare Output Mode for Channel B */
- unsigned int _com1a : 2; /* Compare Output Mode for Channel A */
+ unsigned int wgm1 : 2; /* Waveform Generation Mode */
+ unsigned int com1c : 2; /* Compare Output Mode for Channel C */
+ unsigned int com1b : 2; /* Compare Output Mode for Channel B */
+ unsigned int com1a : 2; /* Compare Output Mode for Channel A */
};
-#define TCCR1A_struct _SFR_IO8_STRUCT(0x80, struct __reg_TCCR1A)
+#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
#endif /* __ASSEMBLER__ */
@@ -1792,14 +1880,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR1B {
- unsigned int _cs1 : 3; /* Clock Select */
- unsigned int _wgm1 : 2; /* Waveform Generation Mode */
+ unsigned int cs1 : 3; /* Clock Select */
+ unsigned int wgm1 : 2; /* Waveform Generation Mode */
unsigned int : 1;
- unsigned int _ices1 : 1; /* Input Capture 1 Edge Select */
- unsigned int _icnc1 : 1; /* Input Capture 1 Noise Canceller */
+ unsigned int ices1 : 1; /* Input Capture 1 Edge Select */
+ unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */
};
-#define TCCR1B_struct _SFR_IO8_STRUCT(0x81, struct __reg_TCCR1B)
+#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
#endif /* __ASSEMBLER__ */
@@ -1820,12 +1908,12 @@
struct __reg_TCCR1C {
unsigned int : 5;
- unsigned int _foc1c : 1; /* Force Output Compare for Channel C */
- unsigned int _foc1b : 1; /* Force Output Compare for Channel B */
- unsigned int _foc1a : 1; /* Force Output Compare for Channel A */
+ unsigned int foc1c : 1; /* Force Output Compare for Channel C */
+ unsigned int foc1b : 1; /* Force Output Compare for Channel B */
+ unsigned int foc1a : 1; /* Force Output Compare for Channel A */
};
-#define TCCR1C_struct _SFR_IO8_STRUCT(0x82, struct __reg_TCCR1C)
+#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
#endif /* __ASSEMBLER__ */
@@ -1866,13 +1954,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR3A {
- unsigned int _wgm3 : 2; /* Waveform Generation Mode */
- unsigned int _com3c : 2; /* Compare Output Mode for Channel C */
- unsigned int _com3b : 2; /* Compare Output Mode for Channel B */
- unsigned int _com3a : 2; /* Compare Output Mode for Channel A */
+ unsigned int wgm3 : 2; /* Waveform Generation Mode */
+ unsigned int com3c : 2; /* Compare Output Mode for Channel C */
+ unsigned int com3b : 2; /* Compare Output Mode for Channel B */
+ unsigned int com3a : 2; /* Compare Output Mode for Channel A */
};
-#define TCCR3A_struct _SFR_IO8_STRUCT(0x90, struct __reg_TCCR3A)
+#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
#endif /* __ASSEMBLER__ */
@@ -1893,14 +1981,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR3B {
- unsigned int _cs3 : 3; /* Clock Select */
- unsigned int _wgm3 : 2; /* Waveform Generation Mode */
+ unsigned int cs3 : 3; /* Clock Select */
+ unsigned int wgm3 : 2; /* Waveform Generation Mode */
unsigned int : 1;
- unsigned int _ices3 : 1; /* Input Capture 3 Edge Select */
- unsigned int _icnc3 : 1; /* Input Capture 3 Noise Canceller */
+ unsigned int ices3 : 1; /* Input Capture 3 Edge Select */
+ unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */
};
-#define TCCR3B_struct _SFR_IO8_STRUCT(0x91, struct __reg_TCCR3B)
+#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
#endif /* __ASSEMBLER__ */
@@ -1921,12 +2009,12 @@
struct __reg_TCCR3C {
unsigned int : 5;
- unsigned int _foc3c : 1; /* Force Output Compare for Channel C */
- unsigned int _foc3b : 1; /* Force Output Compare for Channel B */
- unsigned int _foc3a : 1; /* Force Output Compare for Channel A */
+ unsigned int foc3c : 1; /* Force Output Compare for Channel C */
+ unsigned int foc3b : 1; /* Force Output Compare for Channel B */
+ unsigned int foc3a : 1; /* Force Output Compare for Channel A */
};
-#define TCCR3C_struct _SFR_IO8_STRUCT(0x92, struct __reg_TCCR3C)
+#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
#endif /* __ASSEMBLER__ */
@@ -1967,13 +2055,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR4A {
- unsigned int _wgm4 : 2; /* Waveform Generation Mode */
- unsigned int _com4c : 2; /* Compare Output Mode for Channel C */
- unsigned int _com4b : 2; /* Compare Output Mode for Channel B */
- unsigned int _com4a : 2; /* Compare Output Mode for Channel A */
+ unsigned int wgm4 : 2; /* Waveform Generation Mode */
+ unsigned int com4c : 2; /* Compare Output Mode for Channel C */
+ unsigned int com4b : 2; /* Compare Output Mode for Channel B */
+ unsigned int com4a : 2; /* Compare Output Mode for Channel A */
};
-#define TCCR4A_struct _SFR_IO8_STRUCT(0xa0, struct __reg_TCCR4A)
+#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
#endif /* __ASSEMBLER__ */
@@ -1994,14 +2082,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR4B {
- unsigned int _cs4 : 3; /* Clock Select */
- unsigned int _wgm4 : 2; /* Waveform Generation Mode */
+ unsigned int cs4 : 3; /* Clock Select */
+ unsigned int wgm4 : 2; /* Waveform Generation Mode */
unsigned int : 1;
- unsigned int _ices4 : 1; /* Input Capture 4 Edge Select */
- unsigned int _icnc4 : 1; /* Input Capture 4 Noise Canceller */
+ unsigned int ices4 : 1; /* Input Capture 4 Edge Select */
+ unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */
};
-#define TCCR4B_struct _SFR_IO8_STRUCT(0xa1, struct __reg_TCCR4B)
+#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
#endif /* __ASSEMBLER__ */
@@ -2022,12 +2110,12 @@
struct __reg_TCCR4C {
unsigned int : 5;
- unsigned int _foc4c : 1; /* Force Output Compare for Channel C */
- unsigned int _foc4b : 1; /* Force Output Compare for Channel B */
- unsigned int _foc4a : 1; /* Force Output Compare for Channel A */
+ unsigned int foc4c : 1; /* Force Output Compare for Channel C */
+ unsigned int foc4b : 1; /* Force Output Compare for Channel B */
+ unsigned int foc4a : 1; /* Force Output Compare for Channel A */
};
-#define TCCR4C_struct _SFR_IO8_STRUCT(0xa2, struct __reg_TCCR4C)
+#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
#endif /* __ASSEMBLER__ */
@@ -2068,13 +2156,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR2A {
- unsigned int _wgm2 : 2; /* Waveform Generation Mode */
+ unsigned int wgm2 : 2; /* Waveform Generation Mode */
unsigned int : 2;
- unsigned int _com2b : 2; /* Compare Match Output B Mode */
- unsigned int _com2a : 2; /* Compare Match Output A Mode */
+ unsigned int com2b : 2; /* Compare Match Output B Mode */
+ unsigned int com2a : 2; /* Compare Match Output A Mode */
};
-#define TCCR2A_struct _SFR_IO8_STRUCT(0xb0, struct __reg_TCCR2A)
+#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
#endif /* __ASSEMBLER__ */
@@ -2093,14 +2181,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR2B {
- unsigned int _cs2 : 3; /* Clock Select */
- unsigned int _wgm22 : 1; /* Waveform Generation Mode */
+ unsigned int cs2 : 3; /* Clock Select */
+ unsigned int wgm22 : 1; /* Waveform Generation Mode */
unsigned int : 2;
- unsigned int _foc2b : 1; /* Force Output Compare B */
- unsigned int _foc2a : 1; /* Force Output Compare A */
+ unsigned int foc2b : 1; /* Force Output Compare B */
+ unsigned int foc2a : 1; /* Force Output Compare A */
};
-#define TCCR2B_struct _SFR_IO8_STRUCT(0xb1, struct __reg_TCCR2B)
+#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
#endif /* __ASSEMBLER__ */
@@ -2161,17 +2249,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ASSR {
- unsigned int _tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */
- unsigned int _tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */
- unsigned int _ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */
- unsigned int _ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */
- unsigned int _tcn2ub : 1; /* Timer/Counter2 Update Busy */
- unsigned int _as2 : 1; /* Timer/Counter2 Asynchronous Mode */
- unsigned int _exclk : 1; /* Enable External Clock Input */
- unsigned int _exclkamr : 1; /* Enable External Clock Input for AMR */
+ unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */
+ unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */
+ unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */
+ unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */
+ unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */
+ unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */
+ unsigned int exclk : 1; /* Enable External Clock Input */
+ unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */
};
-#define ASSR_struct _SFR_IO8_STRUCT(0xb6, struct __reg_ASSR)
+#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
#endif /* __ASSEMBLER__ */
@@ -2206,12 +2294,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TWSR {
- unsigned int _twps : 2; /* TWI Prescaler Bits */
+ unsigned int twps : 2; /* TWI Prescaler Bits */
unsigned int : 1;
- unsigned int _tws : 5; /* TWI Status */
+ unsigned int tws : 5; /* TWI Status */
};
-#define TWSR_struct _SFR_IO8_STRUCT(0xb9, struct __reg_TWSR)
+#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
#endif /* __ASSEMBLER__ */
@@ -2231,11 +2319,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TWAR {
- unsigned int _twgce : 1; /* TWI General Call Recognition Enable Bit */
- unsigned int _twa : 7; /* TWI (Slave) Address */
+ unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */
+ unsigned int twa : 7; /* TWI (Slave) Address */
};
-#define TWAR_struct _SFR_IO8_STRUCT(0xba, struct __reg_TWAR)
+#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
#endif /* __ASSEMBLER__ */
@@ -2270,17 +2358,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TWCR {
- unsigned int _twie : 1; /* TWI Interrupt Enable */
+ unsigned int twie : 1; /* TWI Interrupt Enable */
unsigned int : 1;
- unsigned int _twen : 1; /* TWI Enable Bit */
- unsigned int _twwc : 1; /* TWI Write Collision Flag */
- unsigned int _twsto : 1; /* TWI STOP Condition Bit */
- unsigned int _twsta : 1; /* TWI START Condition Bit */
- unsigned int _twea : 1; /* TWI Enable Acknowledge Bit */
- unsigned int _twint : 1; /* TWI Interrupt Flag */
+ unsigned int twen : 1; /* TWI Enable Bit */
+ unsigned int twwc : 1; /* TWI Write Collision Flag */
+ unsigned int twsto : 1; /* TWI STOP Condition Bit */
+ unsigned int twsta : 1; /* TWI START Condition Bit */
+ unsigned int twea : 1; /* TWI Enable Acknowledge Bit */
+ unsigned int twint : 1; /* TWI Interrupt Flag */
};
-#define TWCR_struct _SFR_IO8_STRUCT(0xbc, struct __reg_TWCR)
+#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
#endif /* __ASSEMBLER__ */
@@ -2301,10 +2389,10 @@
struct __reg_TWAMR {
unsigned int : 1;
- unsigned int _twam : 7; /* TWI Address Mask */
+ unsigned int twam : 7; /* TWI Address Mask */
};
-#define TWAMR_struct _SFR_IO8_STRUCT(0xbd, struct __reg_TWAMR)
+#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
#endif /* __ASSEMBLER__ */
@@ -2331,17 +2419,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_UCSR0A {
- unsigned int _mpcm0 : 1; /* Multi-processor Communication Mode */
- unsigned int _u2x0 : 1; /* Double the USART Transmission Speed */
- unsigned int _upe0 : 1; /* USART Parity Error */
- unsigned int _dor0 : 1; /* Data OverRun */
- unsigned int _fe0 : 1; /* Frame Error */
- unsigned int _udre0 : 1; /* USART Data Register Empty */
- unsigned int _txc0 : 1; /* USART Transmit Complete */
- unsigned int _rxc0 : 1; /* USART Receive Complete */
+ unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */
+ unsigned int u2x0 : 1; /* Double the USART Transmission Speed */
+ unsigned int upe0 : 1; /* USART Parity Error */
+ unsigned int dor0 : 1; /* Data OverRun */
+ unsigned int fe0 : 1; /* Frame Error */
+ unsigned int udre0 : 1; /* USART Data Register Empty */
+ unsigned int txc0 : 1; /* USART Transmit Complete */
+ unsigned int rxc0 : 1; /* USART Receive Complete */
};
-#define UCSR0A_struct _SFR_IO8_STRUCT(0xc0, struct __reg_UCSR0A)
+#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
#endif /* __ASSEMBLER__ */
@@ -2362,17 +2450,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_UCSR0B {
- unsigned int _txb80 : 1; /* Transmit Data Bit 8 */
- unsigned int _rxb80 : 1; /* Receive Data Bit 8 */
- unsigned int _ucsz02 : 1; /* Character Size */
- unsigned int _txen0 : 1; /* Transmitter Enable */
- unsigned int _rxen0 : 1; /* Receiver Enable */
- unsigned int _udrie0 : 1; /* USART Data Register Empty Interrupt Enable */
- unsigned int _txcie0 : 1; /* TX Complete Interrupt Enable */
- unsigned int _rxcie0 : 1; /* RX Complete Interrupt Enable */
+ unsigned int txb80 : 1; /* Transmit Data Bit 8 */
+ unsigned int rxb80 : 1; /* Receive Data Bit 8 */
+ unsigned int ucsz02 : 1; /* Character Size */
+ unsigned int txen0 : 1; /* Transmitter Enable */
+ unsigned int rxen0 : 1; /* Receiver Enable */
+ unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */
+ unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */
+ unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */
};
-#define UCSR0B_struct _SFR_IO8_STRUCT(0xc1, struct __reg_UCSR0B)
+#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
#endif /* __ASSEMBLER__ */
@@ -2393,16 +2481,16 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_UCSR0C {
- unsigned int _ucpol0 : 1; /* Clock Polarity */
- unsigned int _ucsz0 : 2; /* Character Size */
- unsigned int _ucpha0 : 1; /* Clock Phase */
- unsigned int _udord0 : 1; /* Data Order */
- unsigned int _usbs0 : 1; /* Stop Bit Select */
- unsigned int _upm0 : 2; /* Parity Mode */
- unsigned int _umsel0 : 2; /* USART Mode Select */
+ unsigned int ucpol0 : 1; /* Clock Polarity */
+ unsigned int ucsz0 : 2; /* Character Size */
+ unsigned int ucpha0 : 1; /* Clock Phase */
+ unsigned int udord0 : 1; /* Data Order */
+ unsigned int usbs0 : 1; /* Stop Bit Select */
+ unsigned int upm0 : 2; /* Parity Mode */
+ unsigned int umsel0 : 2; /* USART Mode Select */
};
-#define UCSR0C_struct _SFR_IO8_STRUCT(0xc2, struct __reg_UCSR0C)
+#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
#endif /* __ASSEMBLER__ */
@@ -2448,17 +2536,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_UCSR1A {
- unsigned int _mpcm1 : 1; /* Multi-processor Communication Mode */
- unsigned int _u2x1 : 1; /* Double the USART Transmission Speed */
- unsigned int _upe1 : 1; /* USART Parity Error */
- unsigned int _dor1 : 1; /* Data OverRun */
- unsigned int _fe1 : 1; /* Frame Error */
- unsigned int _udre1 : 1; /* USART Data Register Empty */
- unsigned int _txc1 : 1; /* USART Transmit Complete */
- unsigned int _rxc1 : 1; /* USART Receive Complete */
+ unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */
+ unsigned int u2x1 : 1; /* Double the USART Transmission Speed */
+ unsigned int upe1 : 1; /* USART Parity Error */
+ unsigned int dor1 : 1; /* Data OverRun */
+ unsigned int fe1 : 1; /* Frame Error */
+ unsigned int udre1 : 1; /* USART Data Register Empty */
+ unsigned int txc1 : 1; /* USART Transmit Complete */
+ unsigned int rxc1 : 1; /* USART Receive Complete */
};
-#define UCSR1A_struct _SFR_IO8_STRUCT(0xc8, struct __reg_UCSR1A)
+#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
#endif /* __ASSEMBLER__ */
@@ -2479,17 +2567,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_UCSR1B {
- unsigned int _txb81 : 1; /* Transmit Data Bit 8 */
- unsigned int _rxb81 : 1; /* Receive Data Bit 8 */
- unsigned int _ucsz12 : 1; /* Character Size */
- unsigned int _txen1 : 1; /* Transmitter Enable */
- unsigned int _rxen1 : 1; /* Receiver Enable */
- unsigned int _udrie1 : 1; /* USART Data Register Empty Interrupt Enable */
- unsigned int _txcie1 : 1; /* TX Complete Interrupt Enable */
- unsigned int _rxcie1 : 1; /* RX Complete Interrupt Enable */
+ unsigned int txb81 : 1; /* Transmit Data Bit 8 */
+ unsigned int rxb81 : 1; /* Receive Data Bit 8 */
+ unsigned int ucsz12 : 1; /* Character Size */
+ unsigned int txen1 : 1; /* Transmitter Enable */
+ unsigned int rxen1 : 1; /* Receiver Enable */
+ unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */
+ unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */
+ unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */
};
-#define UCSR1B_struct _SFR_IO8_STRUCT(0xc9, struct __reg_UCSR1B)
+#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
#endif /* __ASSEMBLER__ */
@@ -2510,16 +2598,16 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_UCSR1C {
- unsigned int _ucpol1 : 1; /* Clock Polarity */
- unsigned int _ucsz1 : 2; /* Character Size */
- unsigned int _ucpha1 : 1; /* Clock Phase */
- unsigned int _udord1 : 1; /* Data Order */
- unsigned int _usbs1 : 1; /* Stop Bit Select */
- unsigned int _upm1 : 2; /* Parity Mode */
- unsigned int _umsel1 : 2; /* USART Mode Select */
+ unsigned int ucpol1 : 1; /* Clock Polarity */
+ unsigned int ucsz1 : 2; /* Character Size */
+ unsigned int ucpha1 : 1; /* Clock Phase */
+ unsigned int udord1 : 1; /* Data Order */
+ unsigned int usbs1 : 1; /* Stop Bit Select */
+ unsigned int upm1 : 2; /* Parity Mode */
+ unsigned int umsel1 : 2; /* USART Mode Select */
};
-#define UCSR1C_struct _SFR_IO8_STRUCT(0xca, struct __reg_UCSR1C)
+#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
#endif /* __ASSEMBLER__ */
@@ -2557,21 +2645,21 @@
#define UDR16 6
#define UDR17 7
-/* Symbol Counter Cotrol Register 0 */
+/* Symbol Counter Control Register 0 */
#define SCCR0 _SFR_MEM8(0xDC)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCCR0 {
- unsigned int _sccmp : 3; /* Symbol Counter Compare Unit 3 Mode selct */
- unsigned int _sctse : 1; /* Symbol Counter Automatic Time Stamping enable */
- unsigned int _sccksel : 1; /* Symbol Counter Clock Source select */
- unsigned int _scen : 1; /* Symbol Counter enable */
- unsigned int _scmbts : 1; /* Manuall Beacon Time Stamp */
- unsigned int _scres : 1; /* Symbol Counter Synchronization */
+ unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */
+ unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */
+ unsigned int sccksel : 1; /* Symbol Counter Clock Source select */
+ unsigned int scen : 1; /* Symbol Counter enable */
+ unsigned int scmbts : 1; /* Manual Beacon Timestamp */
+ unsigned int scres : 1; /* Symbol Counter Synchronization */
};
-#define SCCR0_struct _SFR_IO8_STRUCT(0xdc, struct __reg_SCCR0)
+#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
#endif /* __ASSEMBLER__ */
@@ -2592,11 +2680,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCCR1 {
- unsigned int _scenbo : 1; /* Backoff Slot Counter enable */
+ unsigned int scenbo : 1; /* Backoff Slot Counter enable */
unsigned int : 7;
};
-#define SCCR1_struct _SFR_IO8_STRUCT(0xdd, struct __reg_SCCR1)
+#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
#endif /* __ASSEMBLER__ */
@@ -2610,11 +2698,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCSR {
- unsigned int _scbsy : 1; /* Symbol Counter busy */
+ unsigned int scbsy : 1; /* Symbol Counter busy */
unsigned int : 7;
};
-#define SCSR_struct _SFR_IO8_STRUCT(0xde, struct __reg_SCSR)
+#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
#endif /* __ASSEMBLER__ */
@@ -2628,13 +2716,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCIRQM {
- unsigned int _irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */
- unsigned int _irqmof : 1; /* Symbol Counter Overflow IRQ enable */
- unsigned int _irqmbo : 1; /* Backoff Slot Conter IRQ enable */
+ unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */
+ unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */
+ unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */
unsigned int : 3;
};
-#define SCIRQM_struct _SFR_IO8_STRUCT(0xdf, struct __reg_SCIRQM)
+#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
#endif /* __ASSEMBLER__ */
@@ -2652,13 +2740,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCIRQS {
- unsigned int _irqscp : 3; /* Compare Unit 3 Compare Match IRQ */
- unsigned int _irqsof : 1; /* Symbol Counter Overflow IRQ */
- unsigned int _irqsbo : 1; /* Backoff Slot Counter IRQ */
+ unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */
+ unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */
+ unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */
unsigned int : 3;
};
-#define SCIRQS_struct _SFR_IO8_STRUCT(0xe0, struct __reg_SCIRQS)
+#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
#endif /* __ASSEMBLER__ */
@@ -2676,10 +2764,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCCNTLL {
- unsigned int _sccntll : 8; /* Symbol Counter Register LL-Byte bits */
+ unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */
};
-#define SCCNTLL_struct _SFR_IO8_STRUCT(0xe1, struct __reg_SCCNTLL)
+#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
#endif /* __ASSEMBLER__ */
@@ -2700,10 +2788,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCCNTLH {
- unsigned int _sccntlh : 8; /* Symbol Counter Register LH-Byte bits */
+ unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */
};
-#define SCCNTLH_struct _SFR_IO8_STRUCT(0xe2, struct __reg_SCCNTLH)
+#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
#endif /* __ASSEMBLER__ */
@@ -2724,10 +2812,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCCNTHL {
- unsigned int _sccnthl : 8; /* Symbol Counter Register HL-Byte bits */
+ unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */
};
-#define SCCNTHL_struct _SFR_IO8_STRUCT(0xe3, struct __reg_SCCNTHL)
+#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
#endif /* __ASSEMBLER__ */
@@ -2748,10 +2836,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCCNTHH {
- unsigned int _sccnthh : 8; /* Symbol Counter Register HH-Byte bits */
+ unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */
};
-#define SCCNTHH_struct _SFR_IO8_STRUCT(0xe4, struct __reg_SCCNTHH)
+#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
#endif /* __ASSEMBLER__ */
@@ -2766,16 +2854,16 @@
#define SCCNTHH6 6
#define SCCNTHH7 7
-/* Symbol Counter Beacon Time Stamp Register LL-Byte */
+/* Symbol Counter Beacon Timestamp Register LL-Byte */
#define SCBTSRLL _SFR_MEM8(0xE5)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCBTSRLL {
- unsigned int _scbtsrll : 8; /* Symbol Counter Beacon Time Stamp Register LL-Byte bits */
+ unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */
};
-#define SCBTSRLL_struct _SFR_IO8_STRUCT(0xe5, struct __reg_SCBTSRLL)
+#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
#endif /* __ASSEMBLER__ */
@@ -2790,16 +2878,16 @@
#define SCBTSRLL6 6
#define SCBTSRLL7 7
-/* Symbol Counter Beacon Time Stamp Register LH-Byte */
+/* Symbol Counter Beacon Timestamp Register LH-Byte */
#define SCBTSRLH _SFR_MEM8(0xE6)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCBTSRLH {
- unsigned int _scbtsrlh : 8; /* Symbol Counter Beacon Time Stamp Register LH-Byte bits */
+ unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */
};
-#define SCBTSRLH_struct _SFR_IO8_STRUCT(0xe6, struct __reg_SCBTSRLH)
+#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
#endif /* __ASSEMBLER__ */
@@ -2814,16 +2902,16 @@
#define SCBTSRLH6 6
#define SCBTSRLH7 7
-/* Symbol Counter Beacon Time Stamp Register HL-Byte */
+/* Symbol Counter Beacon Timestamp Register HL-Byte */
#define SCBTSRHL _SFR_MEM8(0xE7)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCBTSRHL {
- unsigned int _scbtsrhl : 8; /* Symbol Counter Beacon Time Stamp Register HL-Byte bits */
+ unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */
};
-#define SCBTSRHL_struct _SFR_IO8_STRUCT(0xe7, struct __reg_SCBTSRHL)
+#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
#endif /* __ASSEMBLER__ */
@@ -2838,16 +2926,16 @@
#define SCBTSRHL6 6
#define SCBTSRHL7 7
-/* Symbol Counter Beacon Time Stamp Register HH-Byte */
+/* Symbol Counter Beacon Timestamp Register HH-Byte */
#define SCBTSRHH _SFR_MEM8(0xE8)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCBTSRHH {
- unsigned int _scbtsrhh : 8; /* Symbol Counter Beacon Time Stamp Register HH-Byte bits */
+ unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */
};
-#define SCBTSRHH_struct _SFR_IO8_STRUCT(0xe8, struct __reg_SCBTSRHH)
+#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
#endif /* __ASSEMBLER__ */
@@ -2862,16 +2950,16 @@
#define SCBTSRHH6 6
#define SCBTSRHH7 7
-/* Symbol Counter Frame Time Stamp Register LL-Byte */
+/* Symbol Counter Frame Timestamp Register LL-Byte */
#define SCTSRLL _SFR_MEM8(0xE9)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCTSRLL {
- unsigned int _sctsrll : 8; /* Symbol Counter Frame Time Stamp Register LL-Byte bits */
+ unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */
};
-#define SCTSRLL_struct _SFR_IO8_STRUCT(0xe9, struct __reg_SCTSRLL)
+#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
#endif /* __ASSEMBLER__ */
@@ -2886,16 +2974,16 @@
#define SCTSRLL6 6
#define SCTSRLL7 7
-/* Symbol Counter Frame Time Stamp Register LH-Byte */
+/* Symbol Counter Frame Timestamp Register LH-Byte */
#define SCTSRLH _SFR_MEM8(0xEA)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCTSRLH {
- unsigned int _sctsrlh : 8; /* Symbol Counter Frame Time Stamp Register LH-Byte bits */
+ unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */
};
-#define SCTSRLH_struct _SFR_IO8_STRUCT(0xea, struct __reg_SCTSRLH)
+#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
#endif /* __ASSEMBLER__ */
@@ -2910,16 +2998,16 @@
#define SCTSRLH6 6
#define SCTSRLH7 7
-/* Symbol Counter Frame Time Stamp Register HL-Byte */
+/* Symbol Counter Frame Timestamp Register HL-Byte */
#define SCTSRHL _SFR_MEM8(0xEB)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCTSRHL {
- unsigned int _sctsrhl : 8; /* Symbol Counter Frame Time Stamp Register HL-Byte bits */
+ unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */
};
-#define SCTSRHL_struct _SFR_IO8_STRUCT(0xeb, struct __reg_SCTSRHL)
+#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
#endif /* __ASSEMBLER__ */
@@ -2934,16 +3022,16 @@
#define SCTSRHL6 6
#define SCTSRHL7 7
-/* Symbol Counter Frame Time Stamp Register HH-Byte */
+/* Symbol Counter Frame Timestamp Register HH-Byte */
#define SCTSRHH _SFR_MEM8(0xEC)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCTSRHH {
- unsigned int _sctsrhh : 8; /* Symbol Counter Frame Time Stamp Register HH-Byte bits */
+ unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */
};
-#define SCTSRHH_struct _SFR_IO8_STRUCT(0xec, struct __reg_SCTSRHH)
+#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
#endif /* __ASSEMBLER__ */
@@ -2964,10 +3052,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR3LL {
- unsigned int _scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte bits */
+ unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */
};
-#define SCOCR3LL_struct _SFR_IO8_STRUCT(0xed, struct __reg_SCOCR3LL)
+#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
#endif /* __ASSEMBLER__ */
@@ -2988,10 +3076,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR3LH {
- unsigned int _scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte bits */
+ unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */
};
-#define SCOCR3LH_struct _SFR_IO8_STRUCT(0xee, struct __reg_SCOCR3LH)
+#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
#endif /* __ASSEMBLER__ */
@@ -3012,10 +3100,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR3HL {
- unsigned int _scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte bits */
+ unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */
};
-#define SCOCR3HL_struct _SFR_IO8_STRUCT(0xef, struct __reg_SCOCR3HL)
+#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
#endif /* __ASSEMBLER__ */
@@ -3036,10 +3124,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR3HH {
- unsigned int _scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte bits */
+ unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */
};
-#define SCOCR3HH_struct _SFR_IO8_STRUCT(0xf0, struct __reg_SCOCR3HH)
+#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
#endif /* __ASSEMBLER__ */
@@ -3060,10 +3148,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR2LL {
- unsigned int _scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte bits */
+ unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */
};
-#define SCOCR2LL_struct _SFR_IO8_STRUCT(0xf1, struct __reg_SCOCR2LL)
+#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
#endif /* __ASSEMBLER__ */
@@ -3084,10 +3172,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR2LH {
- unsigned int _scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte bits */
+ unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */
};
-#define SCOCR2LH_struct _SFR_IO8_STRUCT(0xf2, struct __reg_SCOCR2LH)
+#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
#endif /* __ASSEMBLER__ */
@@ -3108,10 +3196,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR2HL {
- unsigned int _scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte bits */
+ unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */
};
-#define SCOCR2HL_struct _SFR_IO8_STRUCT(0xf3, struct __reg_SCOCR2HL)
+#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
#endif /* __ASSEMBLER__ */
@@ -3132,10 +3220,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR2HH {
- unsigned int _scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte bits */
+ unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */
};
-#define SCOCR2HH_struct _SFR_IO8_STRUCT(0xf4, struct __reg_SCOCR2HH)
+#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
#endif /* __ASSEMBLER__ */
@@ -3156,10 +3244,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR1LL {
- unsigned int _scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte bits */
+ unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */
};
-#define SCOCR1LL_struct _SFR_IO8_STRUCT(0xf5, struct __reg_SCOCR1LL)
+#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
#endif /* __ASSEMBLER__ */
@@ -3180,10 +3268,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR1LH {
- unsigned int _scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte bits */
+ unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */
};
-#define SCOCR1LH_struct _SFR_IO8_STRUCT(0xf6, struct __reg_SCOCR1LH)
+#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
#endif /* __ASSEMBLER__ */
@@ -3204,10 +3292,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR1HL {
- unsigned int _scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte bits */
+ unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */
};
-#define SCOCR1HL_struct _SFR_IO8_STRUCT(0xf7, struct __reg_SCOCR1HL)
+#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
#endif /* __ASSEMBLER__ */
@@ -3228,10 +3316,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SCOCR1HH {
- unsigned int _scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte bits */
+ unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */
};
-#define SCOCR1HH_struct _SFR_IO8_STRUCT(0xf8, struct __reg_SCOCR1HH)
+#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
#endif /* __ASSEMBLER__ */
@@ -3252,13 +3340,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR5A {
- unsigned int _wgm5 : 2; /* Waveform Generation Mode */
- unsigned int _com5c : 2; /* Compare Output Mode for Channel C */
- unsigned int _com5b : 2; /* Compare Output Mode for Channel B */
- unsigned int _com5a : 2; /* Compare Output Mode for Channel A */
+ unsigned int wgm5 : 2; /* Waveform Generation Mode */
+ unsigned int com5c : 2; /* Compare Output Mode for Channel C */
+ unsigned int com5b : 2; /* Compare Output Mode for Channel B */
+ unsigned int com5a : 2; /* Compare Output Mode for Channel A */
};
-#define TCCR5A_struct _SFR_IO8_STRUCT(0x120, struct __reg_TCCR5A)
+#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
#endif /* __ASSEMBLER__ */
@@ -3279,14 +3367,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TCCR5B {
- unsigned int _cs5 : 3; /* Clock Select */
- unsigned int _wgm5 : 2; /* Waveform Generation Mode */
+ unsigned int cs5 : 3; /* Clock Select */
+ unsigned int wgm5 : 2; /* Waveform Generation Mode */
unsigned int : 1;
- unsigned int _ices5 : 1; /* Input Capture 5 Edge Select */
- unsigned int _icnc5 : 1; /* Input Capture 5 Noise Canceller */
+ unsigned int ices5 : 1; /* Input Capture 5 Edge Select */
+ unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */
};
-#define TCCR5B_struct _SFR_IO8_STRUCT(0x121, struct __reg_TCCR5B)
+#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
#endif /* __ASSEMBLER__ */
@@ -3307,12 +3395,12 @@
struct __reg_TCCR5C {
unsigned int : 5;
- unsigned int _foc5c : 1; /* Force Output Compare for Channel C */
- unsigned int _foc5b : 1; /* Force Output Compare for Channel B */
- unsigned int _foc5a : 1; /* Force Output Compare for Channel A */
+ unsigned int foc5c : 1; /* Force Output Compare for Channel C */
+ unsigned int foc5b : 1; /* Force Output Compare for Channel B */
+ unsigned int foc5a : 1; /* Force Output Compare for Channel A */
};
-#define TCCR5C_struct _SFR_IO8_STRUCT(0x122, struct __reg_TCCR5C)
+#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
#endif /* __ASSEMBLER__ */
@@ -3347,6 +3435,77 @@
#define OCR5CL _SFR_MEM8(0x12C)
#define OCR5CH _SFR_MEM8(0x12D)
+/* Low Leakage Voltage Regulator Control Register */
+#define LLCR _SFR_MEM8(0x12F)
+
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_LLCR {
+ unsigned int llencal : 1; /* Enable Automatic Calibration */
+ unsigned int llshort : 1; /* Short Lower Calibration Circuit */
+ unsigned int lltco : 1; /* Temperature Coefficient of Current Source */
+ unsigned int llcal : 1; /* Calibration Active */
+ unsigned int llcomp : 1; /* Comparator Output */
+ unsigned int lldone : 1; /* Calibration Done */
+ unsigned int : 2;
+};
+
+#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
+
+#endif /* __ASSEMBLER__ */
+
+ /* LLCR */
+
+#define LLENCAL 0
+#define LLSHORT 1
+#define LLTCO 2
+#define LLCAL 3
+#define LLCOMP 4
+#define LLDONE 5
+
+/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
+#define LLDRL _SFR_MEM8(0x130)
+
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_LLDRL {
+ unsigned int lldrl : 4; /* Low-Byte Data Register Bits */
+ unsigned int : 4;
+};
+
+#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
+
+#endif /* __ASSEMBLER__ */
+
+ /* LLDRL */
+
+#define LLDRL0 0
+#define LLDRL1 1
+#define LLDRL2 2
+#define LLDRL3 3
+
+/* Low Leakage Voltage Regulator Data Register (High-Byte) */
+#define LLDRH _SFR_MEM8(0x131)
+
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_LLDRH {
+ unsigned int lldrh : 5; /* High-Byte Data Register Bits */
+ unsigned int : 3;
+};
+
+#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
+
+#endif /* __ASSEMBLER__ */
+
+ /* LLDRH */
+
+#define LLDRH0 0
+#define LLDRH1 1
+#define LLDRH2 2
+#define LLDRH3 3
+#define LLDRH4 4
+
/* Data Retention Configuration Register of SRAM 3 */
#define DRTRAM3 _SFR_MEM8(0x132)
@@ -3354,17 +3513,19 @@
struct __reg_DRTRAM3 {
unsigned int : 4;
- unsigned int _endrt : 1; /* Enable SRAM Data Retention */
- unsigned int : 3;
+ unsigned int endrt : 1; /* Enable SRAM Data Retention */
+ unsigned int drtswok : 1; /* DRT Switch OK */
+ unsigned int : 2;
};
-#define DRTRAM3_struct _SFR_IO8_STRUCT(0x132, struct __reg_DRTRAM3)
+#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
#endif /* __ASSEMBLER__ */
/* DRTRAM3 */
#define ENDRT 4
+#define DRTSWOK 5
/* Data Retention Configuration Register of SRAM 2 */
#define DRTRAM2 _SFR_MEM8(0x133)
@@ -3373,17 +3534,19 @@
struct __reg_DRTRAM2 {
unsigned int : 4;
- unsigned int _endrt : 1; /* Enable SRAM Data Retention */
- unsigned int : 3;
+ unsigned int endrt : 1; /* Enable SRAM Data Retention */
+ unsigned int drtswok : 1; /* DRT Switch OK */
+ unsigned int : 2;
};
-#define DRTRAM2_struct _SFR_IO8_STRUCT(0x133, struct __reg_DRTRAM2)
+#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
#endif /* __ASSEMBLER__ */
/* DRTRAM2 */
#define ENDRT 4
+#define DRTSWOK 5
/* Data Retention Configuration Register of SRAM 1 */
#define DRTRAM1 _SFR_MEM8(0x134)
@@ -3392,17 +3555,19 @@
struct __reg_DRTRAM1 {
unsigned int : 4;
- unsigned int _endrt : 1; /* Enable SRAM Data Retention */
- unsigned int : 3;
+ unsigned int endrt : 1; /* Enable SRAM Data Retention */
+ unsigned int drtswok : 1; /* DRT Switch OK */
+ unsigned int : 2;
};
-#define DRTRAM1_struct _SFR_IO8_STRUCT(0x134, struct __reg_DRTRAM1)
+#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
#endif /* __ASSEMBLER__ */
/* DRTRAM1 */
#define ENDRT 4
+#define DRTSWOK 5
/* Data Retention Configuration Register of SRAM 0 */
#define DRTRAM0 _SFR_MEM8(0x135)
@@ -3411,17 +3576,19 @@
struct __reg_DRTRAM0 {
unsigned int : 4;
- unsigned int _endrt : 1; /* Enable SRAM Data Retention */
- unsigned int : 3;
+ unsigned int endrt : 1; /* Enable SRAM Data Retention */
+ unsigned int drtswok : 1; /* DRT Switch OK */
+ unsigned int : 2;
};
-#define DRTRAM0_struct _SFR_IO8_STRUCT(0x135, struct __reg_DRTRAM0)
+#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
#endif /* __ASSEMBLER__ */
/* DRTRAM0 */
#define ENDRT 4
+#define DRTSWOK 5
/* Port Driver Strength Register 0 */
#define DPDS0 _SFR_MEM8(0x136)
@@ -3429,13 +3596,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_DPDS0 {
- unsigned int _pbdrv : 2; /* Driver Strength Port B */
- unsigned int _pddrv : 2; /* Driver Strength Port D */
- unsigned int _pedrv : 2; /* Driver Strength Port E */
- unsigned int _pfdrv : 2; /* Driver Strength Port F */
+ unsigned int pbdrv : 2; /* Driver Strength Port B */
+ unsigned int pddrv : 2; /* Driver Strength Port D */
+ unsigned int pedrv : 2; /* Driver Strength Port E */
+ unsigned int pfdrv : 2; /* Driver Strength Port F */
};
-#define DPDS0_struct _SFR_IO8_STRUCT(0x136, struct __reg_DPDS0)
+#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
#endif /* __ASSEMBLER__ */
@@ -3456,11 +3623,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_DPDS1 {
- unsigned int _pgdrv : 2; /* Driver Strength Port G */
+ unsigned int pgdrv : 2; /* Driver Strength Port G */
unsigned int : 6;
};
-#define DPDS1_struct _SFR_IO8_STRUCT(0x137, struct __reg_DPDS1)
+#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
#endif /* __ASSEMBLER__ */
@@ -3475,12 +3642,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TRXPR {
- unsigned int _trxrst : 1; /* Force Transceiver Reset */
- unsigned int _slptr : 1; /* Multi-purpose Transceiver Control Bit */
+ unsigned int trxrst : 1; /* Force Transceiver Reset */
+ unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */
unsigned int : 6;
};
-#define TRXPR_struct _SFR_IO8_STRUCT(0x139, struct __reg_TRXPR)
+#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
#endif /* __ASSEMBLER__ */
@@ -3489,53 +3656,33 @@
#define TRXRST 0
#define SLPTR 1
-/* AES Test Control Register */
-#define AES_TEST _SFR_MEM8(0x13B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_TEST {
- unsigned int _aes_ok : 1; /* AES BIST OK */
- unsigned int _aes_done : 1; /* AES BIST Done */
- unsigned int : 5;
- unsigned int _aes_tr : 1; /* AES Test Run */
-};
-
-#define AES_TEST_struct _SFR_IO8_STRUCT(0x13b, struct __reg_AES_TEST)
-
-#endif /* __ASSEMBLER__ */
-
- /* AES_TEST */
-
-#define AES_OK 0
-#define AES_DONE 1
-#define AES_TR 7
-
/* AES Control Register */
-#define AES_CON _SFR_MEM8(0x13C)
+#define AES_CTRL _SFR_MEM8(0x13C)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-struct __reg_AES_CON {
+struct __reg_AES_CTRL {
unsigned int : 2;
- unsigned int _aes_im : 1; /* AES Interrupt Enable */
- unsigned int _aes_dir : 1; /* Set AES Operation Direction */
+ unsigned int aes_im : 1; /* AES Interrupt Enable */
+ unsigned int aes_dir : 1; /* Set AES Operation Direction */
unsigned int : 1;
- unsigned int _aes_mode : 1; /* Set AES Operation Mode */
+ unsigned int aes_mode : 1; /* Set AES Operation Mode */
unsigned int : 1;
- unsigned int _aes_request : 1; /* Request AES Operation. */
+ unsigned int aes_request : 1; /* Request AES Operation. */
};
-#define AES_CON_struct _SFR_IO8_STRUCT(0x13c, struct __reg_AES_CON)
+#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
/* symbolic names */
-#define AES_DIR_DEC 0
-#define AES_DIR_ENC 1
+#define AES_DIR_ENC 0
+#define AES_DIR_DEC 1
+#define AES_MODE_ECB 0
+#define AES_MODE_CBC 1
#endif /* __ASSEMBLER__ */
- /* AES_CON */
+ /* AES_CTRL */
#define AES_IM 2
#define AES_DIR 3
@@ -3543,23 +3690,23 @@
#define AES_REQUEST 7
/* AES Status Register */
-#define AES_ST _SFR_MEM8(0x13D)
+#define AES_STATUS _SFR_MEM8(0x13D)
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-struct __reg_AES_ST {
- unsigned int _aes_ry : 1; /* AES Operation Finished with Success */
+struct __reg_AES_STATUS {
+ unsigned int aes_done : 1; /* AES Operation Finished with Success */
unsigned int : 6;
- unsigned int _aes_er : 1; /* AES Operation Finished with Error */
+ unsigned int aes_er : 1; /* AES Operation Finished with Error */
};
-#define AES_ST_struct _SFR_IO8_STRUCT(0x13d, struct __reg_AES_ST)
+#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
#endif /* __ASSEMBLER__ */
- /* AES_ST */
+ /* AES_STATUS */
-#define AES_RY 0
+#define AES_DONE 0
#define AES_ER 7
/* AES Plain and Cipher Text Buffer Register */
@@ -3568,10 +3715,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_AES_STATE {
- unsigned int _aes_state : 8; /* AES Plain and Cipher Text Buffer */
+ unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */
};
-#define AES_STATE_struct _SFR_IO8_STRUCT(0x13e, struct __reg_AES_STATE)
+#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
#endif /* __ASSEMBLER__ */
@@ -3592,10 +3739,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_AES_KEY {
- unsigned int _aes_key : 8; /* AES Encryption/Decryption Key Buffer */
+ unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */
};
-#define AES_KEY_struct _SFR_IO8_STRUCT(0x13f, struct __reg_AES_KEY)
+#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
#endif /* __ASSEMBLER__ */
@@ -3616,13 +3763,13 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TRX_STATUS {
- unsigned int _trx_status : 5; /* Transceiver Main Status */
- unsigned int _tst_status : 1; /* Test mode status */
- unsigned int _cca_status : 1; /* CCA Status Result */
- unsigned int _cca_done : 1; /* CCA Algorithm Status */
+ unsigned int trx_status : 5; /* Transceiver Main Status */
+ unsigned int tst_status : 1; /* Test mode status */
+ unsigned int cca_status : 1; /* CCA Status Result */
+ unsigned int cca_done : 1; /* CCA Algorithm Status */
};
-#define TRX_STATUS_struct _SFR_IO8_STRUCT(0x141, struct __reg_TRX_STATUS)
+#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
/* symbolic names */
@@ -3637,9 +3784,6 @@
#define BUSY_TX_ARET 18
#define RX_AACK_ON 22
#define TX_ARET_ON 25
-#define RX_ON_NOCLK 28
-#define RX_AACK_ON_NOCLK 29
-#define BUSY_RX_AACK_NOCLK 30
#define STATE_TRANSITION_IN_PROGRESS 31
#define TST_DISABLED 0
#define TST_ENABLED 1
@@ -3667,11 +3811,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TRX_STATE {
- unsigned int _trx_cmd : 5; /* State Control Command */
- unsigned int _trac_status : 3; /* Transaction Status */
+ unsigned int trx_cmd : 5; /* State Control Command */
+ unsigned int trac_status : 3; /* Transaction Status */
};
-#define TRX_STATE_struct _SFR_IO8_STRUCT(0x142, struct __reg_TRX_STATE)
+#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
/* symbolic names */
@@ -3684,12 +3828,12 @@
#define CMD_PLL_ON 9
#define CMD_RX_AACK_ON 22
#define CMD_TX_ARET_ON 25
-#define SUCCESS 0
-#define SUCCESS_DATA_PENDING 1
-#define SUCCESS_WAIT_FOR_ACK 2
-#define CHANNEL_ACCESS_FAILURE 3
-#define NO_ACK 5
-#define INVALID 7
+#define TRAC_SUCCESS 0
+#define TRAC_SUCCESS_DATA_PENDING 1
+#define TRAC_SUCCESS_WAIT_FOR_ACK 2
+#define TRAC_CHANNEL_ACCESS_FAILURE 3
+#define TRAC_NO_ACK 5
+#define TRAC_INVALID 7
#endif /* __ASSEMBLER__ */
@@ -3714,12 +3858,12 @@
struct __reg_TRX_CTRL_1 {
unsigned int : 5;
- unsigned int _tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */
- unsigned int _irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */
- unsigned int _pa_ext_en : 1; /* External PA support enable */
+ unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */
+ unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */
+ unsigned int pa_ext_en : 1; /* External PA support enable */
};
-#define TRX_CTRL_1_struct _SFR_IO8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
+#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
#endif /* __ASSEMBLER__ */
@@ -3735,12 +3879,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PHY_TX_PWR {
- unsigned int _tx_pwr : 4; /* Transmit Power Setting */
- unsigned int _pa_lt : 2; /* Power Amplifier Lead Time */
- unsigned int _pa_buf_lt : 2; /* Power Amplifier Buffer Lead Time */
+ unsigned int tx_pwr : 4; /* Transmit Power Setting */
+ unsigned int pa_lt : 2; /* Power Amplifier Lead Time */
+ unsigned int pa_buf_lt : 2; /* Power Amplifier Buffer Lead Time */
};
-#define PHY_TX_PWR_struct _SFR_IO8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
+#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
/* symbolic names */
@@ -3772,12 +3916,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PHY_RSSI {
- unsigned int _rssi : 5; /* Receiver Signal Strength Indicator */
- unsigned int _rnd_value : 2; /* Random Value */
- unsigned int _rx_crc_valid : 1; /* Received Frame CRC Status */
+ unsigned int rssi : 5; /* Receiver Signal Strength Indicator */
+ unsigned int rnd_value : 2; /* Random Value */
+ unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */
};
-#define PHY_RSSI_struct _SFR_IO8_STRUCT(0x146, struct __reg_PHY_RSSI)
+#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
/* symbolic names */
@@ -3806,10 +3950,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PHY_ED_LEVEL {
- unsigned int _ed_level : 8; /* Energy Detection Level */
+ unsigned int ed_level : 8; /* Energy Detection Level */
};
-#define PHY_ED_LEVEL_struct _SFR_IO8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
+#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
/* symbolic names */
@@ -3837,12 +3981,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PHY_CC_CCA {
- unsigned int _channel : 5; /* RX/TX Channel Selection */
- unsigned int _cca_mode : 2; /* Select CCA Measurement Mode */
- unsigned int _cca_request : 1; /* Manual CCA Measurement Request */
+ unsigned int channel : 5; /* RX/TX Channel Selection */
+ unsigned int cca_mode : 2; /* Select CCA Measurement Mode */
+ unsigned int cca_request : 1; /* Manual CCA Measurement Request */
};
-#define PHY_CC_CCA_struct _SFR_IO8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
+#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
/* symbolic names */
@@ -3886,32 +4030,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_CCA_THRES {
- unsigned int _cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */
- unsigned int _cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */
+ unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */
+ unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */
};
-#define CCA_THRES_struct _SFR_IO8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-/* symbolic names */
-
-#define RSSI_BASE_VAL_PLUS_0DB 0
-#define RSSI_BASE_VAL_PLUS_2DB 1
-#define RSSI_BASE_VAL_PLUS_4DB 2
-#define RSSI_BASE_VAL_PLUS_6DB 3
-#define RSSI_BASE_VAL_PLUS_8DB 4
-#define RSSI_BASE_VAL_PLUS_10DB 5
-#define RSSI_BASE_VAL_PLUS_12DB 6
-#define RSSI_BASE_VAL_PLUS_14DB 7
-#define RSSI_BASE_VAL_PLUS_16DB 8
-#define RSSI_BASE_VAL_PLUS_18DB 9
-#define RSSI_BASE_VAL_PLUS_20DB 10
-#define RSSI_BASE_VAL_PLUS_22DB 11
-#define RSSI_BASE_VAL_PLUS_24DB 12
-#define RSSI_BASE_VAL_PLUS_26DB 13
-#define RSSI_BASE_VAL_PLUS_28DB 14
-#define RSSI_BASE_VAL_PLUS_30DB 15
-#define CCA_CS_THRES_MIN 9
-#define CCA_CS_THRES_MAX 15
+#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
#endif /* __ASSEMBLER__ */
@@ -3932,11 +4055,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_RX_CTRL {
- unsigned int _pdt_thres : 4; /* Receiver Sensitivity Control */
+ unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */
unsigned int : 4;
};
-#define RX_CTRL_struct _SFR_IO8_STRUCT(0x14a, struct __reg_RX_CTRL)
+#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
/* symbolic names */
@@ -3958,10 +4081,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SFD_VALUE {
- unsigned int _sfd_value : 8; /* Start of Frame Delimiter Value */
+ unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */
};
-#define SFD_VALUE_struct _SFR_IO8_STRUCT(0x14b, struct __reg_SFD_VALUE)
+#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
/* symbolic names */
@@ -3986,12 +4109,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_TRX_CTRL_2 {
- unsigned int _oqpsk_data_rate : 2; /* Data Rate Selection */
+ unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */
unsigned int : 5;
- unsigned int _rx_safe_mode : 1; /* RX Safe Mode */
+ unsigned int rx_safe_mode : 1; /* RX Safe Mode */
};
-#define TRX_CTRL_2_struct _SFR_IO8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
+#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
/* symbolic names */
@@ -4014,14 +4137,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_ANT_DIV {
- unsigned int _ant_ctrl : 2; /* Static Antenna Diversity Switch Control */
- unsigned int _ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */
- unsigned int _ant_div_en : 1; /* Enable Antenna Diversity */
+ unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */
+ unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */
+ unsigned int ant_div_en : 1; /* Enable Antenna Diversity */
unsigned int : 3;
- unsigned int _ant_sel : 1; /* Antenna Diversity Antenna Status */
+ unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */
};
-#define ANT_DIV_struct _SFR_IO8_STRUCT(0x14d, struct __reg_ANT_DIV)
+#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
/* symbolic names */
@@ -4030,11 +4153,8 @@
#define ANT_RESET 3
#define ANT_DIV_EXT_SW_DIS 0
#define ANT_DIV_EXT_SW_EN 1
-#define ANT_DIV_DIS 0
-#define ANT_DIV_EN 1
-#define ANTENNA_0 1
-#define ANTENNA_1 2
-#define ANTENNA_X 3
+#define ANTENNA_0 0
+#define ANTENNA_1 1
#endif /* __ASSEMBLER__ */
@@ -4052,17 +4172,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IRQ_MASK {
- unsigned int _pll_lock_en : 1; /* PLL Lock Interrupt Enable */
- unsigned int _pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */
- unsigned int _rx_start_en : 1; /* RX_START Interrupt Enable */
- unsigned int _rx_end_en : 1; /* RX_END Interrupt Enable */
- unsigned int _cca_ed_ready_en : 1; /* End of ED Measurement Interrupt Enable */
- unsigned int _ami_en : 1; /* Address Match Interrupt Enable */
- unsigned int _tx_end_en : 1; /* TX_END Interrupt Enable */
- unsigned int _awake_en : 1; /* Awake Interrupt Enable */
+ unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */
+ unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */
+ unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */
+ unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */
+ unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */
+ unsigned int ami_en : 1; /* Address Match Interrupt Enable */
+ unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */
+ unsigned int awake_en : 1; /* Awake Interrupt Enable */
};
-#define IRQ_MASK_struct _SFR_IO8_STRUCT(0x14e, struct __reg_IRQ_MASK)
+#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
#endif /* __ASSEMBLER__ */
@@ -4072,7 +4192,7 @@
#define PLL_UNLOCK_EN 1
#define RX_START_EN 2
#define RX_END_EN 3
-#define CCA_ED_READY_EN 4
+#define CCA_ED_DONE_EN 4
#define AMI_EN 5
#define TX_END_EN 6
#define AWAKE_EN 7
@@ -4083,17 +4203,17 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IRQ_STATUS {
- unsigned int _pll_lock : 1; /* PLL Lock Interrupt Status */
- unsigned int _pll_unlock : 1; /* PLL Unlock Interrupt Status */
- unsigned int _rx_start : 1; /* RX_START Interrupt Status */
- unsigned int _rx_end : 1; /* RX_END Interrupt Status */
- unsigned int _cca_ed_ready : 1; /* End of ED Measurement Interrupt Status */
- unsigned int _ami : 1; /* Address Match Interrupt Status */
- unsigned int _tx_end : 1; /* TX_END Interrupt Status */
- unsigned int _awake : 1; /* Awake Interrupt Status */
+ unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */
+ unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */
+ unsigned int rx_start : 1; /* RX_START Interrupt Status */
+ unsigned int rx_end : 1; /* RX_END Interrupt Status */
+ unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */
+ unsigned int ami : 1; /* Address Match Interrupt Status */
+ unsigned int tx_end : 1; /* TX_END Interrupt Status */
+ unsigned int awake : 1; /* Awake Interrupt Status */
};
-#define IRQ_STATUS_struct _SFR_IO8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
+#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
#endif /* __ASSEMBLER__ */
@@ -4103,7 +4223,7 @@
#define PLL_UNLOCK 1
#define RX_START 2
#define RX_END 3
-#define CCA_ED_READY 4
+#define CCA_ED_DONE 4
#define AMI 5
#define TX_END 6
#define AWAKE 7
@@ -4114,32 +4234,20 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_VREG_CTRL {
- unsigned int _dvreg_trim : 2; /* Adjust DVDD Supply Voltage */
- unsigned int _dvdd_ok : 1; /* DVDD Supply Voltage Valid */
- unsigned int _dvreg_ext : 1; /* Use External DVDD Regulator */
- unsigned int _avreg_trim : 2; /* Adjust AVDD Supply Voltage */
- unsigned int _avdd_ok : 1; /* AVDD Supply Voltage Valid */
- unsigned int _avreg_ext : 1; /* Use External AVDD Regulator */
+ unsigned int : 2;
+ unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */
+ unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */
+ unsigned int : 2;
+ unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */
+ unsigned int avreg_ext : 1; /* Use External AVDD Regulator */
};
-#define VREG_CTRL_struct _SFR_IO8_STRUCT(0x150, struct __reg_VREG_CTRL)
+#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
/* symbolic names */
-#define DVREG_1_80V 0
-#define DVREG_1_75V 1
-#define DVREG_1_84V 2
-#define DVREG_1_88V 3
-#define DVDD_NOT_OK 0
-#define DVDD_OK 1
#define DVDD_INT 0
#define DVDD_EXT 1
-#define AVREG_1_80V 0
-#define AVREG_1_75V 1
-#define AVREG_1_84V 2
-#define AVREG_1_88V 3
-#define AVDD_NOT_OK 0
-#define AVDD_OK 1
#define AVDD_INT 0
#define AVDD_EXT 1
@@ -4147,12 +4255,8 @@
/* VREG_CTRL */
-#define DVREG_TRIM0 0
-#define DVREG_TRIM1 1
#define DVDD_OK 2
#define DVREG_EXT 3
-#define AVREG_TRIM0 4
-#define AVREG_TRIM1 5
#define AVDD_OK 6
#define AVREG_EXT 7
@@ -4162,21 +4266,19 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_BATMON {
- unsigned int _batmon_vth : 4; /* Battery Monitor Threshold Voltage */
- unsigned int _batmon_hr : 1; /* Battery Monitor Voltage Range */
- unsigned int _batmon_ok : 1; /* Battery Monitor Status */
- unsigned int _bat_low_en : 1; /* Battery Monitor Interrupt Enable */
- unsigned int _bat_low : 1; /* Battery Monitor Interrupt Status */
+ unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */
+ unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */
+ unsigned int batmon_ok : 1; /* Battery Monitor Status */
+ unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */
+ unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */
};
-#define BATMON_struct _SFR_IO8_STRUCT(0x151, struct __reg_BATMON)
+#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
/* symbolic names */
#define BATMON_HR_DIS 0
#define BATMON_HR_EN 1
-#define BATMON_LOW 0
-#define BATMON_OK 1
#endif /* __ASSEMBLER__ */
@@ -4197,11 +4299,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_XOSC_CTRL {
- unsigned int _xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */
- unsigned int _xtal_mode : 4; /* Crystal Oscillator Operating Mode */
+ unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */
+ unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */
};
-#define XOSC_CTRL_struct _SFR_IO8_STRUCT(0x152, struct __reg_XOSC_CTRL)
+#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
/* symbolic names */
@@ -4227,12 +4329,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_RX_SYN {
- unsigned int _rx_pdt_level : 4; /* Reduce Receiver Sensitivity */
+ unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */
unsigned int : 3;
- unsigned int _rx_pdt_dis : 1; /* Prevent Frame Reception */
+ unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */
};
-#define RX_SYN_struct _SFR_IO8_STRUCT(0x155, struct __reg_RX_SYN)
+#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
/* symbolic names */
@@ -4256,15 +4358,15 @@
struct __reg_XAH_CTRL_1 {
unsigned int : 1;
- unsigned int _aack_prom_mode : 1; /* Enable Acknowledgment in Promiscuous Mode */
- unsigned int _aack_ack_time : 1; /* Reduce Acknowledgment Time */
+ unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */
+ unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */
unsigned int : 1;
- unsigned int _aack_upld_res_ft : 1; /* Process Reserved Frames */
- unsigned int _aack_fltr_res_ft : 1; /* Filter Reserved Frames */
+ unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */
+ unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */
unsigned int : 2;
};
-#define XAH_CTRL_1_struct _SFR_IO8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
+#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
/* symbolic names */
@@ -4287,10 +4389,10 @@
struct __reg_FTN_CTRL {
unsigned int : 7;
- unsigned int _ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */
+ unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */
};
-#define FTN_CTRL_struct _SFR_IO8_STRUCT(0x158, struct __reg_FTN_CTRL)
+#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
#endif /* __ASSEMBLER__ */
@@ -4305,10 +4407,10 @@
struct __reg_PLL_CF {
unsigned int : 7;
- unsigned int _pll_cf_start : 1; /* Start Center Frequency Calibration */
+ unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */
};
-#define PLL_CF_struct _SFR_IO8_STRUCT(0x15a, struct __reg_PLL_CF)
+#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
#endif /* __ASSEMBLER__ */
@@ -4323,10 +4425,10 @@
struct __reg_PLL_DCU {
unsigned int : 7;
- unsigned int _pll_dcu_start : 1; /* Start Delay Cell Calibration */
+ unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */
};
-#define PLL_DCU_struct _SFR_IO8_STRUCT(0x15b, struct __reg_PLL_DCU)
+#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
#endif /* __ASSEMBLER__ */
@@ -4340,18 +4442,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PART_NUM {
- unsigned int _part_num : 8; /* Part Number */
+ unsigned int part_num : 8; /* Part Number */
};
-#define PART_NUM_struct _SFR_IO8_STRUCT(0x15c, struct __reg_PART_NUM)
+#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
/* symbolic names */
-#define RF210 0
-#define RF220 1
-#define RF230 2
-#define RF231 3
-#define ATmega128RFA1 131
+#define P_ATmega128RFA1 131
#endif /* __ASSEMBLER__ */
@@ -4372,10 +4470,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_VERSION_NUM {
- unsigned int _version_num : 8; /* Version Number */
+ unsigned int version_num : 8; /* Version Number */
};
-#define VERSION_NUM_struct _SFR_IO8_STRUCT(0x15d, struct __reg_VERSION_NUM)
+#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
/* symbolic names */
@@ -4401,10 +4499,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_MAN_ID_0 {
- unsigned int _man_id_0 : 8; /* Manufacturer ID (Low Byte) */
+ unsigned int man_id_0 : 8; /* Manufacturer ID (Low Byte) */
};
-#define MAN_ID_0_struct _SFR_IO8_STRUCT(0x15e, struct __reg_MAN_ID_0)
+#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
/* symbolic names */
@@ -4429,10 +4527,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_MAN_ID_1 {
- unsigned int _man_id_1 : 8; /* Manufacturer ID (High Byte) */
+ unsigned int man_id_1 : 8; /* Manufacturer ID (High Byte) */
};
-#define MAN_ID_1_struct _SFR_IO8_STRUCT(0x15f, struct __reg_MAN_ID_1)
+#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
/* symbolic names */
@@ -4457,10 +4555,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SHORT_ADDR_0 {
- unsigned int _short_addr_0 : 8; /* MAC Short Address */
+ unsigned int short_addr_0 : 8; /* MAC Short Address */
};
-#define SHORT_ADDR_0_struct _SFR_IO8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
+#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
#endif /* __ASSEMBLER__ */
@@ -4481,10 +4579,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_SHORT_ADDR_1 {
- unsigned int _short_addr_1 : 8; /* MAC Short Address */
+ unsigned int short_addr_1 : 8; /* MAC Short Address */
};
-#define SHORT_ADDR_1_struct _SFR_IO8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
+#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
#endif /* __ASSEMBLER__ */
@@ -4505,10 +4603,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PAN_ID_0 {
- unsigned int _pan_id_0 : 8; /* MAC Personal Area Network ID */
+ unsigned int pan_id_0 : 8; /* MAC Personal Area Network ID */
};
-#define PAN_ID_0_struct _SFR_IO8_STRUCT(0x162, struct __reg_PAN_ID_0)
+#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
#endif /* __ASSEMBLER__ */
@@ -4529,10 +4627,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_PAN_ID_1 {
- unsigned int _pan_id_1 : 8; /* MAC Personal Area Network ID */
+ unsigned int pan_id_1 : 8; /* MAC Personal Area Network ID */
};
-#define PAN_ID_1_struct _SFR_IO8_STRUCT(0x163, struct __reg_PAN_ID_1)
+#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
#endif /* __ASSEMBLER__ */
@@ -4553,10 +4651,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_0 {
- unsigned int _ieee_addr_0 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_0 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_0_struct _SFR_IO8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
+#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
#endif /* __ASSEMBLER__ */
@@ -4577,10 +4675,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_1 {
- unsigned int _ieee_addr_1 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_1 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_1_struct _SFR_IO8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
+#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
#endif /* __ASSEMBLER__ */
@@ -4601,10 +4699,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_2 {
- unsigned int _ieee_addr_2 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_2 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_2_struct _SFR_IO8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
+#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
#endif /* __ASSEMBLER__ */
@@ -4625,10 +4723,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_3 {
- unsigned int _ieee_addr_3 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_3 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_3_struct _SFR_IO8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
+#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
#endif /* __ASSEMBLER__ */
@@ -4649,10 +4747,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_4 {
- unsigned int _ieee_addr_4 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_4 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_4_struct _SFR_IO8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
+#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
#endif /* __ASSEMBLER__ */
@@ -4673,10 +4771,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_5 {
- unsigned int _ieee_addr_5 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_5 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_5_struct _SFR_IO8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
+#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
#endif /* __ASSEMBLER__ */
@@ -4697,10 +4795,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_6 {
- unsigned int _ieee_addr_6 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_6 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_6_struct _SFR_IO8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
+#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
#endif /* __ASSEMBLER__ */
@@ -4721,10 +4819,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_IEEE_ADDR_7 {
- unsigned int _ieee_addr_7 : 8; /* MAC IEEE Address */
+ unsigned int ieee_addr_7 : 8; /* MAC IEEE Address */
};
-#define IEEE_ADDR_7_struct _SFR_IO8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
+#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
#endif /* __ASSEMBLER__ */
@@ -4745,12 +4843,12 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_XAH_CTRL_0 {
- unsigned int _slotted_operation : 1; /* Set Slotted Acknowledgment */
- unsigned int _max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */
- unsigned int _max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */
+ unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */
+ unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */
+ unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */
};
-#define XAH_CTRL_0_struct _SFR_IO8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
+#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
/* symbolic names */
@@ -4776,10 +4874,10 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_CSMA_SEED_0 {
- unsigned int _csma_seed_0 : 8; /* Seed Value for CSMA Random Number Generator */
+ unsigned int csma_seed_0 : 8; /* Seed Value for CSMA Random Number Generator */
};
-#define CSMA_SEED_0_struct _SFR_IO8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
+#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
#endif /* __ASSEMBLER__ */
@@ -4800,14 +4898,14 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_CSMA_SEED_1 {
- unsigned int _csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */
- unsigned int _aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */
- unsigned int _aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */
- unsigned int _aack_set_pd : 1; /* Set Frame Pending Sub-field */
- unsigned int _aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */
+ unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */
+ unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */
+ unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */
+ unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */
+ unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */
};
-#define CSMA_SEED_1_struct _SFR_IO8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
+#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
#endif /* __ASSEMBLER__ */
@@ -4828,11 +4926,11 @@
#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
struct __reg_CSMA_BE {
- unsigned int _min_be : 4; /* Minimum Back-off Exponent */
- unsigned int _max_be : 4; /* Maximum Back-off Exponent */
+ unsigned int min_be : 4; /* Minimum Back-off Exponent */
+ unsigned int max_be : 4; /* Maximum Back-off Exponent */
};
-#define CSMA_BE_struct _SFR_IO8_STRUCT(0x16f, struct __reg_CSMA_BE)
+#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
#endif /* __ASSEMBLER__ */
@@ -4847,6 +4945,27 @@
#define MAX_BE2 6
#define MAX_BE3 7
+/* Transceiver Digital Test Control Register */
+#define TST_CTRL_DIGI _SFR_MEM8(0x176)
+
+#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
+
+struct __reg_TST_CTRL_DIGI {
+ unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */
+ unsigned int : 4;
+};
+
+#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
+
+#endif /* __ASSEMBLER__ */
+
+ /* TST_CTRL_DIGI */
+
+#define TST_CTRL_DIG0 0
+#define TST_CTRL_DIG1 1
+#define TST_CTRL_DIG2 2
+#define TST_CTRL_DIG3 3
+
/* Transceiver Received Frame Length Register */
#define TST_RX_LENGTH _SFR_MEM8(0x17B)
@@ -4856,7 +4975,7 @@
unsigned int rx_length : 8; /* Received Frame Length */
};
-#define TST_RX_LENGTH_struct _SFR_IO8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
+#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
#endif /* __ASSEMBLER__ */
@@ -4874,9 +4993,31 @@
/* Start of frame buffer */
#define TRXFBST _SFR_MEM8(0x180)
+ /* TRXFBST */
+
+#define TRXFBST0 0
+#define TRXFBST1 1
+#define TRXFBST2 2
+#define TRXFBST3 3
+#define TRXFBST4 4
+#define TRXFBST5 5
+#define TRXFBST6 6
+#define TRXFBST7 7
+
/* End of frame buffer */
#define TRXFBEND _SFR_MEM8(0x1FF)
+ /* TRXFBEND */
+
+#define TRXFBEND0 0
+#define TRXFBEND1 1
+#define TRXFBEND2 2
+#define TRXFBEND3 3
+#define TRXFBEND4 4
+#define TRXFBEND5 5
+#define TRXFBEND6 6
+#define TRXFBEND7 7
+
/* Interrupt vectors */
/* Vector 0 is the reset vector */
@@ -5123,9 +5264,9 @@
#define TRX24_RX_END_vect _VECTOR(60)
#define TRX24_RX_END_vect_num 60
-/* TRX24 - CCA/ED ready interrupt */
-#define TRX24_CCA_ED_READY_vect _VECTOR(61)
-#define TRX24_CCA_ED_READY_vect_num 61
+/* TRX24 - CCA/ED done interrupt */
+#define TRX24_CCA_ED_DONE_vect _VECTOR(61)
+#define TRX24_CCA_ED_DONE_vect_num 61
/* TRX24 - XAH - AMI */
#define TRX24_XAH_AMI_vect _VECTOR(62)
@@ -5159,9 +5300,9 @@
#define SCNT_BACKOFF_vect _VECTOR(69)
#define SCNT_BACKOFF_vect_num 69
-/* TRX AES engine ready interrupt */
-#define TRX24_AES_RDY_vect _VECTOR(70)
-#define TRX24_AES_RDY_vect_num 70
+/* AES engine ready interrupt */
+#define AES_READY_vect _VECTOR(70)
+#define AES_READY_vect_num 70
/* Battery monitor indicates supply voltage below threshold */
#define BAT_LOW_vect _VECTOR(71)
diff -u rtems/cpukit/score/cpu/avr/avr/iom16.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom16.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom16.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom16.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom16.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -369,9 +369,9 @@
#define COM1A0 6
#define COM1A1 7
-/*
- The ADHSM bit has been removed from all documentation,
- as being not needed at all since the comparator has proven
+/*
+ The ADHSM bit has been removed from all documentation,
+ as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
@@ -602,7 +602,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom161.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom161.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom161.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom161.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom161.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -661,7 +661,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom162.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom162.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom162.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom162.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom162.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Memory mapped I/O registers */
@@ -164,7 +164,7 @@
#define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */
#define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */
#define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */
-
+
/* Interrupt vectors (byte addresses) */
@@ -457,7 +457,7 @@
-/* SPMCR bit definitions */
+/* SPMCR bit definitions */
#define SPMIE 7
#define RWWSB 6
@@ -940,7 +940,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom163.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom163.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom163.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom163.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom163.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -627,7 +627,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom164.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom164.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom164.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom164.h Mon May 10 11:31:21 2010
@@ -82,7 +82,13 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature (ATmega164P) */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x0A
#endif /* _AVR_IOM164_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/iom165.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom165.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom165.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom165.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom165.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -808,7 +808,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom165p.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom165p.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom165p.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom165p.h Mon May 10 11:31:21 2010
@@ -46,7 +46,7 @@
# define _AVR_IOXXX_H_ "iom165p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -810,7 +810,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom168.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom168.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom168.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom168.h Mon May 10 11:31:21 2010
@@ -79,7 +79,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom168p.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom168p.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom168p.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom168p.h Mon May 10 11:31:21 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iom168p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOM168P_H_
@@ -331,7 +331,7 @@
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
+#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
@@ -796,7 +796,7 @@
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
@@ -862,7 +862,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom169.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom169.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom169.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom169.h Mon May 10 11:31:21 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2002, 2003, 2004, 2005
+/* Copyright (c) 2002, 2003, 2004, 2005
Juergen Schilling <juergen.schilling at honeywell.com>
Eric B. Weddington
All rights reserved.
@@ -49,7 +49,7 @@
# define _AVR_IOXXX_H_ "iom169.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -1095,7 +1095,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom169p.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom169p.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom169p.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom169p.h Mon May 10 11:31:21 2010
@@ -48,7 +48,7 @@
# define _AVR_IOXXX_H_ "iom169p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -1018,7 +1018,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom169pa.h:1.1
--- /dev/null Mon May 10 12:10:53 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom169pa.h Mon May 10 11:31:21 2010
@@ -0,0 +1,1472 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom169pa.h - definitions for ATmega169PA */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom169pa.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega169PA_H_
+#define _AVR_ATmega169PA_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define PINE _SFR_IO8(0x0C)
+#define PINE0 0
+#define PINE1 1
+#define PINE2 2
+#define PINE3 3
+#define PINE4 4
+#define PINE5 5
+#define PINE6 6
+#define PINE7 7
+
+#define DDRE _SFR_IO8(0x0D)
+#define DDE0 0
+#define DDE1 1
+#define DDE2 2
+#define DDE3 3
+#define DDE4 4
+#define DDE5 5
+#define DDE6 6
+#define DDE7 7
+
+#define PORTE _SFR_IO8(0x0E)
+#define PORTE0 0
+#define PORTE1 1
+#define PORTE2 2
+#define PORTE3 3
+#define PORTE4 4
+#define PORTE5 5
+#define PORTE6 6
+#define PORTE7 7
+
+#define PINF _SFR_IO8(0x0F)
+#define PINF0 0
+#define PINF1 1
+#define PINF2 2
+#define PINF3 3
+#define PINF4 4
+#define PINF5 5
+#define PINF6 6
+#define PINF7 7
+
+#define DDRF _SFR_IO8(0x10)
+#define DDF0 0
+#define DDF1 1
+#define DDF2 2
+#define DDF3 3
+#define DDF4 4
+#define DDF5 5
+#define DDF6 6
+#define DDF7 7
+
+#define PORTF _SFR_IO8(0x11)
+#define PORTF0 0
+#define PORTF1 1
+#define PORTF2 2
+#define PORTF3 3
+#define PORTF4 4
+#define PORTF5 5
+#define PORTF6 6
+#define PORTF7 7
+
+#define PING _SFR_IO8(0x12)
+#define PING0 0
+#define PING1 1
+#define PING2 2
+#define PING3 3
+#define PING4 4
+#define PING5 5
+
+#define DDRG _SFR_IO8(0x13)
+#define DDG0 0
+#define DDG1 1
+#define DDG2 2
+#define DDG3 3
+#define DDG4 4
+#define DDG5 5
+
+#define PORTG _SFR_IO8(0x14)
+#define PORTG0 0
+#define PORTG1 1
+#define PORTG2 2
+#define PORTG3 3
+#define PORTG4 4
+#define PORTG5 5
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIFR2 _SFR_IO8(0x17)
+#define TOV2 0
+#define OCF2A 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define PCIF0 4
+#define PCIF1 5
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define PCIE0 4
+#define PCIE1 5
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEWE 1
+#define EEMWE 2
+#define EERIE 3
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSR310 0
+#define PSR2 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM01 3
+#define COM0A0 4
+#define COM0A1 5
+#define WGM00 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define OCDR _SFR_IO8(0x31)
+#define OCDR0 0
+#define OCDR1 1
+#define OCDR2 2
+#define OCDR3 3
+#define OCDR4 4
+#define OCDR5 5
+#define OCDR6 6
+#define OCDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define JTRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+#define JTD 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSART0 1
+#define PRSPI 2
+#define PRTIM1 3
+#define PRLCD 4
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define TIMSK2 _SFR_MEM8(0x70)
+#define TOIE2 0
+#define OCIE2A 1
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_MEM16(0x78)
+#endif
+#define ADCW _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define TCCR2A _SFR_MEM8(0xB0)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM21 3
+#define COM2A0 4
+#define COM2A1 5
+#define WGM20 6
+#define FOC2A 7
+
+#define TCCR2B _SFR_MEM8(0xB1)
+
+#define TCNT2 _SFR_MEM8(0xB2)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define OCR2A _SFR_MEM8(0xB3)
+#define OCR2A0 0
+#define OCR2A1 1
+#define OCR2A2 2
+#define OCR2A3 3
+#define OCR2A4 4
+#define OCR2A5 5
+#define OCR2A6 6
+#define OCR2A7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR2UB 0
+#define OCR2UB 1
+#define TCN2UB 2
+#define AS2 3
+#define EXCLK 4
+
+#define USICR _SFR_MEM8(0xB8)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_MEM8(0xBA)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define UCSR0A _SFR_MEM8(0xC0)
+#define MPCM0 0
+#define U2X0 1
+#define UPE0 2
+#define DOR0 3
+#define FE0 4
+#define UDRE0 5
+#define TXC0 6
+#define RXC0 7
+
+#define UCSR0B _SFR_MEM8(0xC1)
+#define TXB80 0
+#define RXB80 1
+#define UCSZ02 2
+#define TXEN0 3
+#define RXEN0 4
+#define UDRIE0 5
+#define TXCIE0 6
+#define RXCIE0 7
+
+#define UCSR0C _SFR_MEM8(0xC2)
+#define UCPOL0 0
+#define UCSZ00 1
+#define UCSZ01 2
+#define USBS0 3
+#define UPM00 4
+#define UPM01 5
+#define UMSEL0 6
+
+#define UBRR0 _SFR_MEM16(0xC4)
+
+#define UBRR0L _SFR_MEM8(0xC4)
+#define UBRR0 0
+#define UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UBRR0H _SFR_MEM8(0xC5)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UDR0 _SFR_MEM8(0xC6)
+#define UDR00 0
+#define UDR01 1
+#define UDR02 2
+#define UDR03 3
+#define UDR04 4
+#define UDR05 5
+#define UDR06 6
+#define UDR07 7
+
+#define LCDCRA _SFR_MEM8(0xE4)
+#define LCDBL 0
+#define LCDCCD 1
+#define LCDBD 2
+#define LCDIE 3
+#define LCDIF 4
+#define LCDAB 6
+#define LCDEN 7
+
+#define LCDCRB _SFR_MEM8(0xE5)
+#define LCDPM0 0
+#define LCDPM1 1
+#define LCDPM2 2
+#define LCDMUX0 4
+#define LCDMUX1 5
+#define LCD2B 6
+#define LCDCS 7
+
+#define LCDFRR _SFR_MEM8(0xE6)
+#define LCDCD0 0
+#define LCDCD1 1
+#define LCDCD2 2
+#define LCDPS0 4
+#define LCDPS1 5
+#define LCDPS2 6
+
+#define LCDCCR _SFR_MEM8(0xE7)
+#define LCDCC0 0
+#define LCDCC1 1
+#define LCDCC2 2
+#define LCDCC3 3
+#define LCDMDT 4
+#define LCDDC0 5
+#define LCDDC1 6
+#define LCDDC2 7
+
+#define LCDDR0 _SFR_MEM8(0xEC)
+#define SEG000 0
+#define SEG001 1
+#define SEG002 2
+#define SEG003 3
+#define SEG004 4
+#define SEG005 5
+#define SEG006 6
+#define SEG007 7
+
+#define LCDDR1 _SFR_MEM8(0xED)
+#define SEG008 0
+#define SEG009 1
+#define SEG010 2
+#define SEG011 3
+#define SEG012 4
+#define SEG013 5
+#define SEG014 6
+#define SEG015 7
+
+#define LCDDR2 _SFR_MEM8(0xEE)
+#define SEG016 0
+#define SEG017 1
+#define SEG018 2
+#define SEG019 3
+#define SEG020 4
+#define SEG021 5
+#define SEG022 6
+#define SEG023 7
+
+#define LCDDR3 _SFR_MEM8(0xEF)
+#define SEG024 0
+
+#define LCDDR5 _SFR_MEM8(0xF1)
+#define SEG100 0
+#define SEG101 1
+#define SEG102 2
+#define SEG103 3
+#define SEG104 4
+#define SEG105 5
+#define SEG106 6
+#define SEG107 7
+
+#define LCDDR6 _SFR_MEM8(0xF2)
+#define SEG108 0
+#define SEG109 1
+#define SEG110 2
+#define SEG111 3
+#define SEG112 4
+#define SEG113 5
+#define SEG114 6
+#define SEG115 7
+
+#define LCDDR7 _SFR_MEM8(0xF3)
+#define SEG116 0
+#define SEG117 1
+#define SEG118 2
+#define SEG119 3
+#define SEG120 4
+#define SEG121 5
+#define SEG122 6
+#define SEG123 7
+
+#define LCDDR8 _SFR_MEM8(0xF4)
+#define SEG124 0
+
+#define LCDDR10 _SFR_MEM8(0xF6)
+#define SEG200 0
+#define SEG201 1
+#define SEG202 2
+#define SEG203 3
+#define SEG204 4
+#define SEG205 5
+#define SEG206 6
+#define SEG207 7
+
+#define LCDDR11 _SFR_MEM8(0xF7)
+#define SEG208 0
+#define SEG209 1
+#define SEG210 2
+#define SEG211 3
+#define SEG212 4
+#define SEG213 5
+#define SEG214 6
+#define SEG215 7
+
+#define LCDDR12 _SFR_MEM8(0xF8)
+#define SEG216 0
+#define SEG217 1
+#define SEG218 2
+#define SEG219 3
+#define SEG220 4
+#define SEG221 5
+#define SEG222 6
+#define SEG223 7
+
+#define LCDDR13 _SFR_MEM8(0xF9)
+#define SEG224 0
+
+#define LCDDR15 _SFR_MEM8(0xFB)
+#define SEG300 0
+#define SEG301 1
+#define SEG302 2
+#define SEG303 3
+#define SEG304 4
+#define SEG305 5
+#define SEG306 6
+#define SEG307 7
+
+#define LCDDR16 _SFR_MEM8(0xFC)
+#define SEG308 0
+#define SEG309 1
+#define SEG310 2
+#define SEG311 3
+#define SEG312 4
+#define SEG313 5
+#define SEG314 6
+#define SEG315 7
+
+#define LCDDR17 _SFR_MEM8(0xFD)
+#define SEG316 0
+#define SEG317 1
+#define SEG318 2
+#define SEG319 3
+#define SEG320 4
+#define SEG321 5
+#define SEG322 6
+#define SEG323 7
+
+#define LCDDR18 _SFR_MEM8(0xFE)
+#define SEG324 0
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define PCINT0_vect_num 2
+#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 3
+#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */
+#define TIMER2_COMP_vect_num 4
+#define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */
+#define TIMER2_OVF_vect_num 5
+#define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect_num 6
+#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 7
+#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect_num 8
+#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */
+#define TIMER1_OVF_vect_num 9
+#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */
+#define TIMER0_COMP_vect_num 10
+#define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */
+#define TIMER0_OVF_vect_num 11
+#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 12
+#define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */
+#define USART0_RX_vect_num 13
+#define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */
+#define USART0_UDRE_vect_num 14
+#define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */
+#define USART0_TX_vect_num 15
+#define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */
+#define USI_START_vect_num 16
+#define USI_START_vect _VECTOR(16) /* USI Start Condition */
+#define USI_OVERFLOW_vect_num 17
+#define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */
+#define ANALOG_COMP_vect_num 18
+#define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */
+#define ADC_vect_num 19
+#define ADC_vect _VECTOR(19) /* ADC Conversion Complete */
+#define EE_READY_vect_num 20
+#define EE_READY_vect _VECTOR(20) /* EEPROM Ready */
+#define SPM_READY_vect_num 21
+#define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */
+#define LCD_vect_num 22
+#define LCD_vect _VECTOR(22) /* LCD Start of Frame */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (23 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (1024)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x3FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
+#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
+#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown out detector trigger level */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x05
+
+
+/* Device Pin Definitions */
+#define RXD_DDR DDRE
+#define RXD_PORT PORTE
+#define RXD_PIN PINE
+#define RXD_BIT 0
+
+#define PCINT0_DDR DDRE
+#define PCINT0_PORT PORTE
+#define PCINT0_PIN PINE
+#define PCINT0_BIT 0
+
+#define TXD_DDR DDRE
+#define TXD_PORT PORTE
+#define TXD_PIN PINE
+#define TXD_BIT 1
+
+#define PCINT1_DDR DDRE
+#define PCINT1_PORT PORTE
+#define PCINT1_PIN PINE
+#define PCINT1_BIT 1
+
+#define XCK_DDR DDRE
+#define XCK_PORT PORTE
+#define XCK_PIN PINE
+#define XCK_BIT 2
+
+#define AIN0_DDR DDRE
+#define AIN0_PORT PORTE
+#define AIN0_PIN PINE
+#define AIN0_BIT 2
+
+#define PCINT2_DDR DDRE
+#define PCINT2_PORT PORTE
+#define PCINT2_PIN PINE
+#define PCINT2_BIT 2
+
+#define AIN1_DDR DDRE
+#define AIN1_PORT PORTE
+#define AIN1_PIN PINE
+#define AIN1_BIT 3
+
+#define PCINT3_DDR DDRE
+#define PCINT3_PORT PORTE
+#define PCINT3_PIN PINE
+#define PCINT3_BIT 3
+
+#define USCK_DDR DDRE
+#define USCK_PORT PORTE
+#define USCK_PIN PINE
+#define USCK_BIT 4
+
+#define SCL_DDR DDRE
+#define SCL_PORT PORTE
+#define SCL_PIN PINE
+#define SCL_BIT 4
+
+#define PCINT4_DDR DDRE
+#define PCINT4_PORT PORTE
+#define PCINT4_PIN PINE
+#define PCINT4_BIT 4
+
+#define DI_DDR DDRE
+#define DI_PORT PORTE
+#define DI_PIN PINE
+#define DI_BIT 5
+
+#define SDA_DDR DDRE
+#define SDA_PORT PORTE
+#define SDA_PIN PINE
+#define SDA_BIT 5
+
+#define PCINT5_DDR DDRE
+#define PCINT5_PORT PORTE
+#define PCINT5_PIN PINE
+#define PCINT5_BIT 5
+
+#define DO_DDR DDRE
+#define DO_PORT PORTE
+#define DO_PIN PINE
+#define DO_BIT 6
+
+#define PCINT6_DDR DDRE
+#define PCINT6_PORT PORTE
+#define PCINT6_PIN PINE
+#define PCINT6_BIT 6
+
+#define PCINT7_DDR DDRE
+#define PCINT7_PORT PORTE
+#define PCINT7_PIN PINE
+#define PCINT7_BIT 7
+
+#define SS_DDR DDRB
+#define SS_PORT PORTB
+#define SS_PIN PINB
+#define SS_BIT 0
+
+#define PCINT8_DDR DDRB
+#define PCINT8_PORT PORTB
+#define PCINT8_PIN PINB
+#define PCINT8_BIT 0
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 1
+
+#define PCINT9_DDR DDRB
+#define PCINT9_PORT PORTB
+#define PCINT9_PIN PINB
+#define PCINT9_BIT 1
+
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 2
+
+#define PCINT10_DDR DDRB
+#define PCINT10_PORT PORTB
+#define PCINT10_PIN PINB
+#define PCINT10_BIT 2
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 3
+
+#define PCINT11_DDR DDRB
+#define PCINT11_PORT PORTB
+#define PCINT11_PIN PINB
+#define PCINT11_BIT 3
+
+#define OC0_DDR DDRB
+#define OC0_PORT PORTB
+#define OC0_PIN PINB
+#define OC0_BIT 4
+
+#define PCINT12_DDR DDRB
+#define PCINT12_PORT PORTB
+#define PCINT12_PIN PINB
+#define PCINT12_BIT 4
+
+#define OC1A_DDR DDRB
+#define OC1A_PORT PORTB
+#define OC1A_PIN PINB
+#define OC1A_BIT 5
+
+#define PCINT13_DDR DDRB
+#define PCINT13_PORT PORTB
+#define PCINT13_PIN PINB
+#define PCINT13_BIT 5
+
+#define OC1B_DDR DDRB
+#define OC1B_PORT PORTB
+#define OC1B_PIN PINB
+#define OC1B_BIT 6
+
+#define PCINT14_DDR DDRB
+#define PCINT14_PORT PORTB
+#define PCINT14_PIN PINB
+#define PCINT14_BIT 6
+
+#define OC2_DDR DDRB
+#define OC2_PORT PORTB
+#define OC2_PIN PINB
+#define OC2_BIT 7
+
+#define PCINT15_DDR DDRB
+#define PCINT15_PORT PORTB
+#define PCINT15_PIN PINB
+#define PCINT15_BIT 7
+
+#define T1_DDR DDRG
+#define T1_PORT PORTG
+#define T1_PIN PING
+#define T1_BIT 3
+
+#define SEG24_DDR DDRG
+#define SEG24_PORT PORTG
+#define SEG24_PIN PING
+#define SEG24_BIT 3
+
+#define T0_DDR DDRG
+#define T0_PORT PORTG
+#define T0_PIN PING
+#define T0_BIT 4
+
+#define SEG23_DDR DDRG
+#define SEG23_PORT PORTG
+#define SEG23_PIN PING
+#define SEG23_BIT 4
+
+#define ICP/SEG22_DDR DDRD
+#define ICP/SEG22_PORT PORTD
+#define ICP/SEG22_PIN PIND
+#define ICP/SEG22_BIT 0
+
+#define INT0/SEG21_DDR DDRD
+#define INT0/SEG21_PORT PORTD
+#define INT0/SEG21_PIN PIND
+#define INT0/SEG21_BIT 1
+
+#define SEG20_DDR DDRD
+#define SEG20_PORT PORTD
+#define SEG20_PIN PIND
+#define SEG20_BIT 2
+
+#define SEG19_DDR DDRD
+#define SEG19_PORT PORTD
+#define SEG19_PIN PIND
+#define SEG19_BIT 3
+
+#define SEG18_DDR DDRD
+#define SEG18_PORT PORTD
+#define SEG18_PIN PIND
+#define SEG18_BIT 4
+
+#define SEG17_DDR DDRD
+#define SEG17_PORT PORTD
+#define SEG17_PIN PIND
+#define SEG17_BIT 5
+
+#define SEG16_DDR DDRD
+#define SEG16_PORT PORTD
+#define SEG16_PIN PIND
+#define SEG16_BIT 6
+
+#define SEG15_DDR DDRD
+#define SEG15_PORT PORTD
+#define SEG15_PIN PIND
+#define SEG15_BIT 7
+
+#define SEG14_DDR DDRG
+#define SEG14_PORT PORTG
+#define SEG14_PIN PING
+#define SEG14_BIT 0
+
+#define SEG13_DDR DDRG
+#define SEG13_PORT PORTG
+#define SEG13_PIN PING
+#define SEG13_BIT 1
+
+#define SEG12_DDR DDRC
+#define SEG12_PORT PORTC
+#define SEG12_PIN PINC
+#define SEG12_BIT 0
+
+#define SEG11_DDR DDRC
+#define SEG11_PORT PORTC
+#define SEG11_PIN PINC
+#define SEG11_BIT 1
+
+#define SEG10_DDR DDRC
+#define SEG10_PORT PORTC
+#define SEG10_PIN PINC
+#define SEG10_BIT 2
+
+#define SEG9_DDR DDRC
+#define SEG9_PORT PORTC
+#define SEG9_PIN PINC
+#define SEG9_BIT 3
+
+#define SEG8_DDR DDRC
+#define SEG8_PORT PORTC
+#define SEG8_PIN PINC
+#define SEG8_BIT 4
+
+#define SEG7_DDR DDRC
+#define SEG7_PORT PORTC
+#define SEG7_PIN PINC
+#define SEG7_BIT 5
+
+#define SEG6_DDR DDRC
+#define SEG6_PORT PORTC
+#define SEG6_PIN PINC
+#define SEG6_BIT 6
+
+#define SEG5_DDR DDRC
+#define SEG5_PORT PORTC
+#define SEG5_PIN PINC
+#define SEG5_BIT 7
+
+#define SEG4_DDR DDRG
+#define SEG4_PORT PORTG
+#define SEG4_PIN PING
+#define SEG4_BIT 2
+
+#define SEG3_DDR DDRA
+#define SEG3_PORT PORTA
+#define SEG3_PIN PINA
+#define SEG3_BIT 7
+
+#define SEG2_DDR DDRA
+#define SEG2_PORT PORTA
+#define SEG2_PIN PINA
+#define SEG2_BIT 6
+
+#define SEG1_DDR DDRA
+#define SEG1_PORT PORTA
+#define SEG1_PIN PINA
+#define SEG1_BIT 5
+
+#define SEG0_DDR DDRA
+#define SEG0_PORT PORTA
+#define SEG0_PIN PINA
+#define SEG0_BIT 4
+
+#define COM3_DDR DDRA
+#define COM3_PORT PORTA
+#define COM3_PIN PINA
+#define COM3_BIT 3
+
+#define COM2_DDR DDRA
+#define COM2_PORT PORTA
+#define COM2_PIN PINA
+#define COM2_BIT 2
+
+#define COM1_DDR DDRA
+#define COM1_PORT PORTA
+#define COM1_PIN PINA
+#define COM1_BIT 1
+
+#define COM0_DDR DDRA
+#define COM0_PORT PORTA
+#define COM0_PIN PINA
+#define COM0_BIT 0
+
+#define ADC7_DDR DDRF
+#define ADC7_PORT PORTF
+#define ADC7_PIN PINF
+#define ADC7_BIT 7
+
+#define ADC6_DDR DDRF
+#define ADC6_PORT PORTF
+#define ADC6_PIN PINF
+#define ADC6_BIT 6
+
+#define TD0_DDR DDRF
+#define TD0_PORT PORTF
+#define TD0_PIN PINF
+#define TD0_BIT 6
+
+#define ADC5_DDR DDRF
+#define ADC5_PORT PORTF
+#define ADC5_PIN PINF
+#define ADC5_BIT 5
+
+#define ADC4_DDR DDRF
+#define ADC4_PORT PORTF
+#define ADC4_PIN PINF
+#define ADC4_BIT 4
+
+#define ADC3_DDR DDRF
+#define ADC3_PORT PORTF
+#define ADC3_PIN PINF
+#define ADC3_BIT 3
+
+#define ADC2_DDR DDRF
+#define ADC2_PORT PORTF
+#define ADC2_PIN PINF
+#define ADC2_BIT 2
+
+#define ADC1_DDR DDRF
+#define ADC1_PORT PORTF
+#define ADC1_PIN PINF
+#define ADC1_BIT 1
+
+#define ADC0_DDR DDRF
+#define ADC0_PORT PORTF
+#define ADC0_PIN PINF
+#define ADC0_BIT 0
+
+#endif /* _AVR_ATmega169PA_H_ */
+
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom16a.h:1.1
--- /dev/null Mon May 10 12:10:53 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom16a.h Mon May 10 11:31:21 2010
@@ -0,0 +1,904 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom16a.h - definitions for ATmega16A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom16a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega16A_H_
+#define _AVR_ATmega16A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define TWBR _SFR_IO8(0x00)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_IO8(0x01)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_IO8(0x02)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_IO8(0x03)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSR _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define UBRRL _SFR_IO8(0x09)
+#define UBRR0 0
+#define UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UCSRB _SFR_IO8(0x0A)
+#define TXB8 0
+#define RXB8 1
+#define UCSZ2 2
+#define TXEN 3
+#define RXEN 4
+#define UDRIE 5
+#define TXCIE 6
+#define RXCIE 7
+
+#define UCSRA _SFR_IO8(0x0B)
+#define MPCM 0
+#define U2X 1
+#define UPE 2
+#define DOR 3
+#define FE 4
+#define UDRE 5
+#define TXC 6
+#define RXC 7
+
+#define UDR _SFR_IO8(0x0C)
+#define UDR0 0
+#define UDR1 1
+#define UDR2 2
+#define UDR3 3
+#define UDR4 4
+#define UDR5 5
+#define UDR6 6
+#define UDR7 7
+
+#define SPCR _SFR_IO8(0x0D)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x0E)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x0F)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define PIND _SFR_IO8(0x10)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x11)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x12)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define PINC _SFR_IO8(0x13)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x14)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x15)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEWE 1
+#define EEMWE 2
+#define EERIE 3
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define UBRRH _SFR_IO8(0x20)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UCSRC _SFR_IO8(0x20)
+#define UCPOL 0
+#define UCSZ0 1
+#define UCSZ1 2
+#define USBS 3
+#define UPM0 4
+#define UPM1 5
+#define UMSEL 6
+#define URSEL 7
+
+#define WDTCR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDTOE 4
+
+#define ASSR _SFR_IO8(0x22)
+#define TCR2UB 0
+#define OCR2UB 1
+#define TCN2UB 2
+#define AS2 3
+
+#define OCR2 _SFR_IO8(0x23)
+#define OCR2_0 0
+#define OCR2_1 1
+#define OCR2_2 2
+#define OCR2_3 3
+#define OCR2_4 4
+#define OCR2_5 5
+#define OCR2_6 6
+#define OCR2_7 7
+
+#define TCNT2 _SFR_IO8(0x24)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define TCCR2 _SFR_IO8(0x25)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM21 3
+#define COM20 4
+#define COM21 5
+#define WGM20 6
+#define FOC2 7
+
+#define ICR1 _SFR_IO16(0x26)
+
+#define ICR1L _SFR_IO8(0x26)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_IO8(0x27)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1B _SFR_IO16(0x28)
+
+#define OCR1BL _SFR_IO8(0x28)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_IO8(0x29)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1A _SFR_IO16(0x2A)
+
+#define OCR1AL _SFR_IO8(0x2A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_IO8(0x2B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCNT1 _SFR_IO16(0x2C)
+
+#define TCNT1L _SFR_IO8(0x2C)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_IO8(0x2D)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define TCCR1B _SFR_IO8(0x2E)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1A _SFR_IO8(0x2F)
+#define WGM10 0
+#define WGM11 1
+#define FOC1B 2
+#define FOC1A 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define SFIOR _SFR_IO8(0x30)
+#define PSR10 0
+#define PSR2 1
+#define PUD 2
+#define ACME 3
+#define ADTS0 5
+#define ADTS1 6
+#define ADTS2 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define OCDR _SFR_IO8(0x31)
+#define OCDR0 0
+#define OCDR1 1
+#define OCDR2 2
+#define OCDR3 3
+#define OCDR4 4
+#define OCDR5 5
+#define OCDR6 6
+#define OCDR7 7
+
+#define TCNT0 _SFR_IO8(0x32)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCCR0 _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM01 3
+#define COM00 4
+#define COM01 5
+#define WGM00 6
+#define FOC0 7
+
+#define MCUCSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define JTRF 4
+#define ISC2 6
+#define JTD 7
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define SM0 4
+#define SM1 5
+#define SE 6
+#define SM2 7
+
+#define TWCR _SFR_IO8(0x36)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define RWWSB 6
+#define SPMIE 7
+
+#define TIFR _SFR_IO8(0x38)
+#define TOV0 0
+#define OCF0 1
+#define TOV1 2
+#define OCF1B 3
+#define OCF1A 4
+#define ICF1 5
+#define TOV2 6
+#define OCF2 7
+
+#define TIMSK _SFR_IO8(0x39)
+#define TOIE0 0
+#define OCIE0 1
+#define TOIE1 2
+#define OCIE1B 3
+#define OCIE1A 4
+#define TICIE1 5
+#define TOIE2 6
+#define OCIE2 7
+
+#define GIFR _SFR_IO8(0x3A)
+#define INTF2 5
+#define INTF0 6
+#define INTF1 7
+
+#define GICR _SFR_IO8(0x3B)
+#define IVCE 0
+#define IVSEL 1
+#define INT2 5
+#define INT0 6
+#define INT1 7
+
+#define OCR0 _SFR_IO8(0x3C)
+#define OCR0_0 0
+#define OCR0_1 1
+#define OCR0_2 2
+#define OCR0_3 3
+#define OCR0_4 4
+#define OCR0_5 5
+#define OCR0_6 6
+#define OCR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define TIMER2_COMP_vect_num 3
+#define TIMER2_COMP_vect _VECTOR(3) /* Timer/Counter2 Compare Match */
+#define TIMER2_OVF_vect_num 4
+#define TIMER2_OVF_vect _VECTOR(4) /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect_num 5
+#define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 6
+#define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect_num 7
+#define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */
+#define TIMER1_OVF_vect_num 8
+#define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num 9
+#define TIMER0_OVF_vect _VECTOR(9) /* Timer/Counter0 Overflow */
+#define SPISTC_vect_num 10
+#define SPISTC_vect _VECTOR(10) /* Serial Transfer Complete */
+#define USARTRXC_vect_num 11
+#define USARTRXC_vect _VECTOR(11) /* USART, Rx Complete */
+#define USARTUDRE_vect_num 12
+#define USARTUDRE_vect _VECTOR(12) /* USART Data Register Empty */
+#define USARTTXC_vect_num 13
+#define USARTTXC_vect _VECTOR(13) /* USART, Tx Complete */
+#define ADC_vect_num 14
+#define ADC_vect _VECTOR(14) /* ADC Conversion Complete */
+#define EE_RDY_vect_num 15
+#define EE_RDY_vect _VECTOR(15) /* EEPROM Ready */
+#define ANA_COMP_vect_num 16
+#define ANA_COMP_vect _VECTOR(16) /* Analog Comparator */
+#define TWI_vect_num 17
+#define TWI_vect _VECTOR(17) /* 2-wire Serial Interface */
+#define INT2_vect_num 18
+#define INT2_vect _VECTOR(18) /* External Interrupt Request 2 */
+#define TIMER0_COMP_vect_num 19
+#define TIMER0_COMP_vect _VECTOR(19) /* Timer/Counter0 Compare Match */
+#define SPM_RDY_vect_num 20
+#define SPM_RDY_vect _VECTOR(20) /* Store Program Memory Ready */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x60)
+#define RAMSIZE (1024)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x3FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */
+#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */
+#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
+#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
+#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x03
+
+
+/* Device Pin Definitions */
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 5
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 6
+
+#define PB7_SCK_DDR DDRB7_SCK
+#define PB7_SCK_PORT PORTB7_SCK
+#define PB7_SCK_PIN PINB7_SCK
+#define PB7_SCK_BIT 7_SCK
+
+#define RXD_DDR DDRD
+#define RXD_PORT PORTD
+#define RXD_PIN PIND
+#define RXD_BIT 0
+
+#define TXD_DDR DDRD
+#define TXD_PORT PORTD
+#define TXD_PIN PIND
+#define TXD_BIT 1
+
+#define INT0_DDR DDRD
+#define INT0_PORT PORTD
+#define INT0_PIN PIND
+#define INT0_BIT 2
+
+#define INT1_DDR DDRD
+#define INT1_PORT PORTD
+#define INT1_PIN PIND
+#define INT1_BIT 3
+
+#define OC1B_DDR DDRD
+#define OC1B_PORT PORTD
+#define OC1B_PIN PIND
+#define OC1B_BIT 4
+
+#define OC1A_DDR DDRD
+#define OC1A_PORT PORTD
+#define OC1A_PIN PIND
+#define OC1A_BIT 5
+
+#define ICP_DDR DDRD
+#define ICP_PORT PORTD
+#define ICP_PIN PIND
+#define ICP_BIT 6
+
+#define OC2_DDR DDRD
+#define OC2_PORT PORTD
+#define OC2_PIN PIND
+#define OC2_BIT 7
+
+#define SCL_DDR DDRC
+#define SCL_PORT PORTC
+#define SCL_PIN PINC
+#define SCL_BIT 0
+
+#define SDA_DDR DDRC
+#define SDA_PORT PORTC
+#define SDA_PIN PINC
+#define SDA_BIT 1
+
+#define PC3_DDR DDRC
+#define PC3_PORT PORTC
+#define PC3_PIN PINC
+#define PC3_BIT 3
+
+#define PC4_DDR DDRC
+#define PC4_PORT PORTC
+#define PC4_PIN PINC
+#define PC4_BIT 4
+
+#define PC5_DDR DDRC
+#define PC5_PORT PORTC
+#define PC5_PIN PINC
+#define PC5_BIT 5
+
+#define ADC7_DDR DDRA
+#define ADC7_PORT PORTA
+#define ADC7_PIN PINA
+#define ADC7_BIT 7
+
+#define ADC6_DDR DDRA
+#define ADC6_PORT PORTA
+#define ADC6_PIN PINA
+#define ADC6_BIT 6
+
+#define ADc5_DDR DDRA
+#define ADc5_PORT PORTA
+#define ADc5_PIN PINA
+#define ADc5_BIT 5
+
+#define ADC4_DDR DDRA
+#define ADC4_PORT PORTA
+#define ADC4_PIN PINA
+#define ADC4_BIT 4
+
+#define ADC3_DDR DDRA
+#define ADC3_PORT PORTA
+#define ADC3_PIN PINA
+#define ADC3_BIT 3
+
+#define ADC2_DDR DDRA
+#define ADC2_PORT PORTA
+#define ADC2_PIN PINA
+#define ADC2_BIT 2
+
+#define ADC1_DDR DDRA
+#define ADC1_PORT PORTA
+#define ADC1_PIN PINA
+#define ADC1_BIT 1
+
+#define ADC0_DDR DDRA
+#define ADC0_PORT PORTA
+#define ADC0_PIN PINA
+#define ADC0_BIT 0
+
+#define T0_DDR DDRB
+#define T0_PORT PORTB
+#define T0_PIN PINB
+#define T0_BIT 0
+
+#define T1_DDR DDRB
+#define T1_PORT PORTB
+#define T1_PIN PINB
+#define T1_BIT 1
+
+#define AIN0_DDR DDRB
+#define AIN0_PORT PORTB
+#define AIN0_PIN PINB
+#define AIN0_BIT 2
+
+#define AIN1_DDR DDRB
+#define AIN1_PORT PORTB
+#define AIN1_PIN PINB
+#define AIN1_BIT 3
+
+#define SS_DDR DDRB
+#define SS_PORT PORTB
+#define SS_PIN PINB
+#define SS_BIT 4
+
+#endif /* _AVR_ATmega16A_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom16hva.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom16hva.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom16hva.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom16hva.h Mon May 10 11:31:21 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2007, Anatoly Sokolov
+/* Copyright (c) 2007, Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom16hva2.h:1.1
--- /dev/null Mon May 10 12:10:53 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom16hva2.h Mon May 10 11:31:21 2010
@@ -0,0 +1,871 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom16hva2.h - definitions for ATmega16HVA2 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom16hva2.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega16HVA2_H_
+#define _AVR_ATmega16HVA2_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+#define ICF0 3
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 3
+
+#define OSICSR _SFR_IO8(0x17)
+#define OSIEN 0
+#define OSIST 1
+#define OSISEL0 4
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define ICS0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+
+#define TCNT0 _SFR_IO16(0x26)
+
+#define TCNT0L _SFR_IO8(0x26)
+#define TCNT0L0 0
+#define TCNT0L1 1
+#define TCNT0L2 2
+#define TCNT0L3 3
+#define TCNT0L4 4
+#define TCNT0L5 5
+#define TCNT0L6 6
+#define TCNT0L7 7
+
+#define TCNT0H _SFR_IO8(0x27)
+#define TCNT0H0 0
+#define TCNT0H1 1
+#define TCNT0H2 2
+#define TCNT0H3 3
+#define TCNT0H4 4
+#define TCNT0H5 5
+#define TCNT0H6 6
+#define TCNT0H7 7
+
+#define OCR0A _SFR_IO8(0x28)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define OCR0B _SFR_IO8(0x29)
+#define OCR0B0 0
+#define OCR0B1 1
+#define OCR0B2 2
+#define OCR0B3 3
+#define OCR0B4 4
+#define OCR0B5 5
+#define OCR0B6 6
+#define OCR0B7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define DWDR _SFR_IO8(0x31)
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BODRF 2
+#define WDRF 3
+#define OCDRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define PUD 4
+#define CKOE 5
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+#define SIGRD 5
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPCE 7
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRVADC 0
+#define PRTIM0 1
+#define PRTIM1 2
+#define PRSPI 3
+#define PRVRM 5
+
+#define FOSCCAL _SFR_MEM8(0x66)
+#define FCAL0 0
+#define FCAL1 1
+#define FCAL2 2
+#define FCAL3 3
+#define FCAL4 4
+#define FCAL5 5
+#define FCAL6 6
+#define FCAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+#define ICIE0 3
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 3
+
+#define VADC _SFR_MEM16(0x78)
+
+#define VADCL _SFR_MEM8(0x78)
+#define VADC0 0
+#define VADC1 1
+#define VADC2 2
+#define VADC3 3
+#define VADC4 4
+#define VADC5 5
+#define VADC6 6
+#define VADC7 7
+
+#define VADCH _SFR_MEM8(0x79)
+#define VADC8 0
+#define VADC9 1
+#define VADC10 2
+#define VADC11 3
+
+#define VADCSR _SFR_MEM8(0x7A)
+#define VADCCIE 0
+#define VADCCIF 1
+#define VADSC 2
+#define VADEN 3
+
+#define VADMUX _SFR_MEM8(0x7C)
+#define VADMUX0 0
+#define VADMUX1 1
+#define VADMUX2 2
+#define VADMUX3 3
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define PA0DID 0
+#define PA1DID 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define ICS1 3
+#define ICES1 4
+#define ICNC1 5
+#define ICEN1 6
+#define TCW1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define OCR1A _SFR_MEM8(0x88)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define OCR1B _SFR_MEM8(0x89)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define ROCR _SFR_MEM8(0xC8)
+#define ROCWIE 0
+#define ROCWIF 1
+#define ROCS 7
+
+#define BGCCR _SFR_MEM8(0xD0)
+#define BGCC0 0
+#define BGCC1 1
+#define BGCC2 2
+#define BGCC3 3
+#define BGCC4 4
+#define BGCC5 5
+#define BGD 7
+
+#define BGCRR _SFR_MEM8(0xD1)
+#define BGCR0 0
+#define BGCR1 1
+#define BGCR2 2
+#define BGCR3 3
+#define BGCR4 4
+#define BGCR5 5
+#define BGCR6 6
+#define BGCR7 7
+
+#define CADAC0 _SFR_MEM8(0xE0)
+#define CADAC00 0
+#define CADAC01 1
+#define CADAC02 2
+#define CADAC03 3
+#define CADAC04 4
+#define CADAC05 5
+#define CADAC06 6
+#define CADAC07 7
+
+#define CADAC1 _SFR_MEM8(0xE1)
+#define CADAC08 0
+#define CADAC09 1
+#define CADAC10 2
+#define CADAC11 3
+#define CADAC12 4
+#define CADAC13 5
+#define CADAC14 6
+#define CADAC15 7
+
+#define CADAC2 _SFR_MEM8(0xE2)
+#define CADAC16 0
+#define CADAC17 1
+#define CADAC18 2
+#define CADAC19 3
+#define CADAC20 4
+#define CADAC21 5
+#define CADAC22 6
+#define CADAC23 7
+
+#define CADAC3 _SFR_MEM8(0xE3)
+#define CADAC24 0
+#define CADAC25 1
+#define CADAC26 2
+#define CADAC27 3
+#define CADAC28 4
+#define CADAC29 5
+#define CADAC30 6
+#define CADAC31 7
+
+#define CADCSRA _SFR_MEM8(0xE4)
+#define CADSE 0
+#define CADSI0 1
+#define CADSI1 2
+#define CADAS0 3
+#define CADAS1 4
+#define CADUB 5
+#define CADPOL 6
+#define CADEN 7
+
+#define CADCSRB _SFR_MEM8(0xE5)
+#define CADICIF 0
+#define CADRCIF 1
+#define CADACIF 2
+#define CADICIE 4
+#define CADRCIE 5
+#define CADACIE 6
+
+#define CADRC _SFR_MEM8(0xE6)
+#define CADRC0 0
+#define CADRC1 1
+#define CADRC2 2
+#define CADRC3 3
+#define CADRC4 4
+#define CADRC5 5
+#define CADRC6 6
+#define CADRC7 7
+
+#define CADIC _SFR_MEM16(0xE8)
+
+#define CADICL _SFR_MEM8(0xE8)
+#define CADICL0 0
+#define CADICL1 1
+#define CADICL2 2
+#define CADICL3 3
+#define CADICL4 4
+#define CADICL5 5
+#define CADICL6 6
+#define CADICL7 7
+
+#define CADICH _SFR_MEM8(0xE9)
+#define CADICH0 0
+#define CADICH1 1
+#define CADICH2 2
+#define CADICH3 3
+#define CADICH4 4
+#define CADICH5 5
+#define CADICH6 6
+#define CADICH7 7
+
+#define FCSR _SFR_MEM8(0xF0)
+#define CFE 0
+#define DFE 1
+#define CPS 2
+#define DUVRD 3
+
+#define BPIMSK _SFR_MEM8(0xF2)
+#define CHCIE 0
+#define DHCIE 1
+#define COCIE 2
+#define DOCIE 3
+#define SCIE 4
+
+#define BPIFR _SFR_MEM8(0xF3)
+#define CHCIF 0
+#define DHCIF 1
+#define COCIF 2
+#define DOCIF 3
+#define SCIF 4
+
+#define BPSCD _SFR_MEM8(0xF5)
+#define SCDL0 0
+#define SCDL1 1
+#define SCDL2 2
+#define SCDL3 3
+#define SCDL4 4
+#define SCDL5 5
+#define SCDL6 6
+#define SCDL7 7
+
+#define BPDOCD _SFR_MEM8(0xF6)
+#define DOCDL0 0
+#define DOCDL1 1
+#define DOCDL2 2
+#define DOCDL3 3
+#define DOCDL4 4
+#define DOCDL5 5
+#define DOCDL6 6
+#define DOCDL7 7
+
+#define BPCOCD _SFR_MEM8(0xF7)
+#define COCDL0 0
+#define COCDL1 1
+#define COCDL2 2
+#define COCDL3 3
+#define COCDL4 4
+#define COCDL5 5
+#define COCDL6 6
+#define COCDL7 7
+
+#define BPDHCD _SFR_MEM8(0xF8)
+#define DHCDL0 0
+#define DHCDL1 1
+#define DHCDL2 2
+#define DHCDL3 3
+#define DHCDL4 4
+#define DHCDL5 5
+#define DHCDL6 6
+#define DHCDL7 7
+
+#define BPCHCD _SFR_MEM8(0xF9)
+#define CHCDL0 0
+#define CHCDL1 1
+#define CHCDL2 2
+#define CHCDL3 3
+#define CHCDL4 4
+#define CHCDL5 5
+#define CHCDL6 6
+#define CHCDL7 7
+
+#define BPSCTR _SFR_MEM8(0xFA)
+#define SCPT0 0
+#define SCPT1 1
+#define SCPT2 2
+#define SCPT3 3
+#define SCPT4 4
+#define SCPT5 5
+#define SCPT6 6
+
+#define BPOCTR _SFR_MEM8(0xFB)
+#define OCPT0 0
+#define OCPT1 1
+#define OCPT2 2
+#define OCPT3 3
+#define OCPT4 4
+#define OCPT5 5
+
+#define BPHCTR _SFR_MEM8(0xFC)
+#define HCPT0 0
+#define HCPT1 1
+#define HCPT2 2
+#define HCPT3 3
+#define HCPT4 4
+#define HCPT5 5
+
+#define BPCR _SFR_MEM8(0xFD)
+#define CHCD 0
+#define DHCD 1
+#define COCD 2
+#define DOCD 3
+#define SCD 4
+#define PRMD 7
+
+#define BPPLR _SFR_MEM8(0xFE)
+#define BPPL 0
+#define BPPLE 1
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define BPINT_vect_num 1
+#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */
+#define VREGMON_vect_num 2
+#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */
+#define INT0_vect_num 3
+#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */
+#define INT1_vect_num 4
+#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */
+#define INT2_vect_num 5
+#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */
+#define PCINT0_vect_num 6
+#define PCINT0_vect _VECTOR(6) /* Pin Change Interrupt Request 0 */
+#define WDT_vect_num 7
+#define WDT_vect _VECTOR(7) /* Watchdog Timeout Interrupt */
+#define TIMER1_IC_vect_num 8
+#define TIMER1_IC_vect _VECTOR(8) /* Timer 1 Input capture */
+#define TIMER1_COMPA_vect_num 9
+#define TIMER1_COMPA_vect _VECTOR(9) /* Timer 1 Compare Match A */
+#define TIMER1_COMPB_vect_num 10
+#define TIMER1_COMPB_vect _VECTOR(10) /* Timer 1 Compare Match B */
+#define TIMER1_OVF_vect_num 11
+#define TIMER1_OVF_vect _VECTOR(11) /* Timer 1 overflow */
+#define TIMER0_IC_vect_num 12
+#define TIMER0_IC_vect _VECTOR(12) /* Timer 0 Input Capture */
+#define TIMER0_COMPA_vect_num 13
+#define TIMER0_COMPA_vect _VECTOR(13) /* Timer 0 Comapre Match A */
+#define TIMER0_COMPB_vect_num 14
+#define TIMER0_COMPB_vect _VECTOR(14) /* Timer 0 Compare Match B */
+#define TIMER0_OVF_vect_num 15
+#define TIMER0_OVF_vect _VECTOR(15) /* Timer 0 Overflow */
+#define SPI;STC_vect_num 16
+#define SPI;STC_vect _VECTOR(16) /* SPI Serial transfer complete */
+#define VADC_vect_num 17
+#define VADC_vect _VECTOR(17) /* Voltage ADC Conversion Complete */
+#define CCADC_CONV_vect_num 18
+#define CCADC_CONV_vect _VECTOR(18) /* Coulomb Counter ADC Conversion Complete */
+#define CCADC_REG_CUR_vect_num 19
+#define CCADC_REG_CUR_vect _VECTOR(19) /* Coloumb Counter ADC Regular Current */
+#define CCADC_ACC_vect_num 20
+#define CCADC_ACC_vect _VECTOR(20) /* Coloumb Counter ADC Accumulator */
+#define EE_READY_vect_num 21
+#define EE_READY_vect _VECTOR(21) /* EEPROM Ready */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (22 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (1024)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (NA)
+#define XRAMEND (RAMEND)
+#define E2END (0xFF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x3FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_SUT0 (unsigned char)~_BV(0) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(1) /* Select start-up time */
+#define FUSE_SUT2 (unsigned char)~_BV(2) /* Select start-up time */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(3) /* Enable self programming */
+#define FUSE_DWEN (unsigned char)~_BV(4) /* Enable debugWIRE */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */
+#define LFUSE_DEFAULT (FUSE_SPIEN)
+
+/* High Fuse Byte */
+#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select 0 */
+#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select 1 */
+#define FUSE_COMPMODE (unsigned char)~_BV(2) /* Compatibility mode */
+#define HFUSE_DEFAULT (FUSE_COMPMODE & FUSE_OSCSEL1)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x0E
+
+
+/* Device Pin Definitions */
+#define PV2_DDR DDRV
+#define PV2_PORT PORTV
+#define PV2_PIN PINV
+#define PV2_BIT 2
+
+#define PV1_DDR DDRV
+#define PV1_PORT PORTV
+#define PV1_PIN PINV
+#define PV1_BIT 1
+
+#define NV_DDR DDRNV
+#define NV_PORT PORTNV
+#define NV_PIN PINNV
+#define NV_BIT NV
+
+#define VFET_DDR DDRVFET
+#define VFET_PORT PORTVFET
+#define VFET_PIN PINVFET
+#define VFET_BIT VFET
+
+#define CF1P_DDR DDRCF1P
+#define CF1P_PORT PORTCF1P
+#define CF1P_PIN PINCF1P
+#define CF1P_BIT CF1P
+
+#define CF1N_DDR DDRCF1N
+#define CF1N_PORT PORTCF1N
+#define CF1N_PIN PINCF1N
+#define CF1N_BIT CF1N
+
+#define CF2P_DDR DDRCF2P
+#define CF2P_PORT PORTCF2P
+#define CF2P_PIN PINCF2P
+#define CF2P_BIT CF2P
+
+#define CF2N_DDR DDRCF2N
+#define CF2N_PORT PORTCF2N
+#define CF2N_PIN PINCF2N
+#define CF2N_BIT CF2N
+
+#define VREG_DDR DDRVREG
+#define VREG_PORT PORTVREG
+#define VREG_PIN PINVREG
+#define VREG_BIT VREG
+
+#define VREF_DDR DDRVREF
+#define VREF_PORT PORTVREF
+#define VREF_PIN PINVREF
+#define VREF_BIT VREF
+
+#define VREFGND_DDR DDRVREFGND
+#define VREFGND_PORT PORTVREFGND
+#define VREFGND_PIN PINVREFGND
+#define VREFGND_BIT VREFGND
+
+#define PI_DDR DDRI
+#define PI_PORT PORTI
+#define PI_PIN PINI
+#define PI_BIT
+
+#define NI_DDR DDRNI
+#define NI_PORT PORTNI
+#define NI_PIN PINNI
+#define NI_BIT NI
+
+#define PA0_DDR DDRA
+#define PA0_PORT PORTA
+#define PA0_PIN PINA
+#define PA0_BIT 0
+
+#define PA1_DDR DDRA
+#define PA1_PORT PORTA
+#define PA1_PIN PINA
+#define PA1_BIT 1
+
+#define PA2_DDR DDRA
+#define PA2_PORT PORTA
+#define PA2_PIN PINA
+#define PA2_BIT 2
+
+#define PB0_DDR DDRB
+#define PB0_PORT PORTB
+#define PB0_PIN PINB
+#define PB0_BIT 0
+
+#define PB1_DDR DDRB
+#define PB1_PORT PORTB
+#define PB1_PIN PINB
+#define PB1_BIT 1
+
+#define PB2_DDR DDRB
+#define PB2_PORT PORTB
+#define PB2_PIN PINB
+#define PB2_BIT 2
+
+#define PB3_DDR DDRB
+#define PB3_PORT PORTB
+#define PB3_PIN PINB
+#define PB3_BIT 3
+
+#define PC0_DDR DDRC
+#define PC0_PORT PORTC
+#define PC0_PIN PINC
+#define PC0_BIT 0
+
+#define BATT_DDR DDRBATT
+#define BATT_PORT PORTBATT
+#define BATT_PIN PINBATT
+#define BATT_BIT BATT
+
+#define OC_DDR DDROC
+#define OC_PORT PORTOC
+#define OC_PIN PINOC
+#define OC_BIT OC
+
+#endif /* _AVR_ATmega16HVA2_H_ */
+
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom16hvb.h:1.1
--- /dev/null Mon May 10 12:10:53 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom16hvb.h Mon May 10 11:31:21 2010
@@ -0,0 +1,1039 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom16hvb.h - definitions for ATmega16HVB */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom16hvb.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega16HVB_H_
+#define _AVR_ATmega16HVB_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+#define ICF0 3
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 3
+
+#define OSICSR _SFR_IO8(0x17)
+#define OSIEN 0
+#define OSIST 1
+#define OSISEL0 4
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+#define INTF3 3
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+#define INT3 3
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define ICS0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+
+#define TCNT0 _SFR_IO16(0x26)
+
+#define TCNT0L _SFR_IO8(0x26)
+#define TCNT0L0 0
+#define TCNT0L1 1
+#define TCNT0L2 2
+#define TCNT0L3 3
+#define TCNT0L4 4
+#define TCNT0L5 5
+#define TCNT0L6 6
+#define TCNT0L7 7
+
+#define TCNT0H _SFR_IO8(0x27)
+#define TCNT0H0 0
+#define TCNT0H1 1
+#define TCNT0H2 2
+#define TCNT0H3 3
+#define TCNT0H4 4
+#define TCNT0H5 5
+#define TCNT0H6 6
+#define TCNT0H7 7
+
+#define OCR0A _SFR_IO8(0x28)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define OCR0B _SFR_IO8(0x29)
+#define OCR0B0 0
+#define OCR0B1 1
+#define OCR0B2 2
+#define OCR0B3 3
+#define OCR0B4 4
+#define OCR0B5 5
+#define OCR0B6 6
+#define OCR0B7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define DWDR _SFR_IO8(0x31)
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BODRF 2
+#define WDRF 3
+#define OCDRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define CKOE 5
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define LBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPCE 7
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRVADC 0
+#define PRTIM0 1
+#define PRTIM1 2
+#define PRSPI 3
+#define PRVRM 5
+#define PRTWI 6
+
+#define FOSCCAL _SFR_MEM8(0x66)
+#define FCAL0 0
+#define FCAL1 1
+#define FCAL2 2
+#define FCAL3 3
+#define FCAL4 4
+#define FCAL5 5
+#define FCAL6 6
+#define FCAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+#define ISC30 6
+#define ISC31 7
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT4 0
+#define PCINT5 1
+#define PCINT6 2
+#define PCINT7 3
+#define PCINT8 4
+#define PCINT9 5
+#define PCINT10 6
+#define PCINT11 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+#define ICIE0 3
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 3
+
+#define VADC _SFR_MEM16(0x78)
+
+#define VADCL _SFR_MEM8(0x78)
+#define VADC0 0
+#define VADC1 1
+#define VADC2 2
+#define VADC3 3
+#define VADC4 4
+#define VADC5 5
+#define VADC6 6
+#define VADC7 7
+
+#define VADCH _SFR_MEM8(0x79)
+#define VADC8 0
+#define VADC9 1
+#define VADC10 2
+#define VADC11 3
+
+#define VADCSR _SFR_MEM8(0x7A)
+#define VADCCIE 0
+#define VADCCIF 1
+#define VADSC 2
+#define VADEN 3
+
+#define VADMUX _SFR_MEM8(0x7C)
+#define VADMUX0 0
+#define VADMUX1 1
+#define VADMUX2 2
+#define VADMUX3 3
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define PA0DID 0
+#define PA1DID 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define ICS1 3
+#define ICES1 4
+#define ICNC1 5
+#define ICEN1 6
+#define TCW1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define OCR1A _SFR_MEM8(0x88)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define OCR1B _SFR_MEM8(0x89)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define TWBR _SFR_MEM8(0xB8)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_MEM8(0xB9)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_MEM8(0xBA)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_MEM8(0xBB)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#define TWCR _SFR_MEM8(0xBC)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define TWAMR _SFR_MEM8(0xBD)
+#define TWAM0 1
+#define TWAM1 2
+#define TWAM2 3
+#define TWAM3 4
+#define TWAM4 5
+#define TWAM5 6
+#define TWAM6 7
+
+#define TWBCSR _SFR_MEM8(0xBE)
+#define TWBCIP 0
+#define TWBDT0 1
+#define TWBDT1 2
+#define TWBCIE 6
+#define TWBCIF 7
+
+#define ROCR _SFR_MEM8(0xC8)
+#define ROCWIE 0
+#define ROCWIF 1
+#define ROCD 4
+#define ROCS 7
+
+#define BGCCR _SFR_MEM8(0xD0)
+#define BGCC0 0
+#define BGCC1 1
+#define BGCC2 2
+#define BGCC3 3
+#define BGCC4 4
+#define BGCC5 5
+
+#define BGCRR _SFR_MEM8(0xD1)
+#define BGCR0 0
+#define BGCR1 1
+#define BGCR2 2
+#define BGCR3 3
+#define BGCR4 4
+#define BGCR5 5
+#define BGCR6 6
+#define BGCR7 7
+
+#define BGCSR _SFR_MEM8(0xD2)
+#define BGSCDIE 0
+#define BGSCDIF 1
+#define BGSCDE 4
+#define BGD 5
+
+#define CHGDCSR _SFR_MEM8(0xD4)
+#define CHGDIE 0
+#define CHGDIF 1
+#define CHGDISC0 2
+#define CHGDISC1 3
+#define BATTPVL 4
+
+#define CADAC0 _SFR_MEM8(0xE0)
+#define CADAC00 0
+#define CADAC01 1
+#define CADAC02 2
+#define CADAC03 3
+#define CADAC04 4
+#define CADAC05 5
+#define CADAC06 6
+#define CADAC07 7
+
+#define CADAC1 _SFR_MEM8(0xE1)
+#define CADAC08 0
+#define CADAC09 1
+#define CADAC10 2
+#define CADAC11 3
+#define CADAC12 4
+#define CADAC13 5
+#define CADAC14 6
+#define CADAC15 7
+
+#define CADAC2 _SFR_MEM8(0xE2)
+#define CADAC16 0
+#define CADAC17 1
+#define CADAC18 2
+#define CADAC19 3
+#define CADAC20 4
+#define CADAC21 5
+#define CADAC22 6
+#define CADAC23 7
+
+#define CADAC3 _SFR_MEM8(0xE3)
+#define CADAC24 0
+#define CADAC25 1
+#define CADAC26 2
+#define CADAC27 3
+#define CADAC28 4
+#define CADAC29 5
+#define CADAC30 6
+#define CADAC31 7
+
+#define CADIC _SFR_MEM16(0xE4)
+
+#define CADICL _SFR_MEM8(0xE4)
+#define CADICL0 0
+#define CADICL1 1
+#define CADICL2 2
+#define CADICL3 3
+#define CADICL4 4
+#define CADICL5 5
+#define CADICL6 6
+#define CADICL7 7
+
+#define CADICH _SFR_MEM8(0xE5)
+#define CADICH0 0
+#define CADICH1 1
+#define CADICH2 2
+#define CADICH3 3
+#define CADICH4 4
+#define CADICH5 5
+#define CADICH6 6
+#define CADICH7 7
+
+#define CADCSRA _SFR_MEM8(0xE6)
+#define CADSE 0
+#define CADSI0 1
+#define CADSI1 2
+#define CADAS0 3
+#define CADAS1 4
+#define CADUB 5
+#define CADPOL 6
+#define CADEN 7
+
+#define CADCSRB _SFR_MEM8(0xE7)
+#define CADICIF 0
+#define CADRCIF 1
+#define CADACIF 2
+#define CADICIE 4
+#define CADRCIE 5
+#define CADACIE 6
+
+#define CADCSRC _SFR_MEM8(0xE8)
+#define CADVSE 0
+
+#define CADRCC _SFR_MEM8(0xE9)
+#define CADRCC0 0
+#define CADRCC1 1
+#define CADRCC2 2
+#define CADRCC3 3
+#define CADRCC4 4
+#define CADRCC5 5
+#define CADRCC6 6
+#define CADRCC7 7
+
+#define CADRDC _SFR_MEM8(0xEA)
+#define CADRDC0 0
+#define CADRDC1 1
+#define CADRDC2 2
+#define CADRDC3 3
+#define CADRDC4 4
+#define CADRDC5 5
+#define CADRDC6 6
+#define CADRDC7 7
+
+#define FCSR _SFR_MEM8(0xF0)
+#define CFE 0
+#define DFE 1
+#define CPS 2
+#define DUVRD 3
+
+#define CBCR _SFR_MEM8(0xF1)
+#define CBE1 0
+#define CBE2 1
+#define CBE3 2
+#define CBE4 3
+
+#define BPIMSK _SFR_MEM8(0xF2)
+#define CHCIE 0
+#define DHCIE 1
+#define COCIE 2
+#define DOCIE 3
+#define SCIE 4
+
+#define BPIFR _SFR_MEM8(0xF3)
+#define CHCIF 0
+#define DHCIF 1
+#define COCIF 2
+#define DOCIF 3
+#define SCIF 4
+
+#define BPSCD _SFR_MEM8(0xF5)
+#define SCDL0 0
+#define SCDL1 1
+#define SCDL2 2
+#define SCDL3 3
+#define SCDL4 4
+#define SCDL5 5
+#define SCDL6 6
+#define SCDL7 7
+
+#define BPDOCD _SFR_MEM8(0xF6)
+#define DOCDL0 0
+#define DOCDL1 1
+#define DOCDL2 2
+#define DOCDL3 3
+#define DOCDL4 4
+#define DOCDL5 5
+#define DOCDL6 6
+#define DOCDL7 7
+
+#define BPCOCD _SFR_MEM8(0xF7)
+#define COCDL0 0
+#define COCDL1 1
+#define COCDL2 2
+#define COCDL3 3
+#define COCDL4 4
+#define COCDL5 5
+#define COCDL6 6
+#define COCDL7 7
+
+#define BPDHCD _SFR_MEM8(0xF8)
+#define DHCDL0 0
+#define DHCDL1 1
+#define DHCDL2 2
+#define DHCDL3 3
+#define DHCDL4 4
+#define DHCDL5 5
+#define DHCDL6 6
+#define DHCDL7 7
+
+#define BPCHCD _SFR_MEM8(0xF9)
+#define CHCDL0 0
+#define CHCDL1 1
+#define CHCDL2 2
+#define CHCDL3 3
+#define CHCDL4 4
+#define CHCDL5 5
+#define CHCDL6 6
+#define CHCDL7 7
+
+#define BPSCTR _SFR_MEM8(0xFA)
+#define SCPT0 0
+#define SCPT1 1
+#define SCPT2 2
+#define SCPT3 3
+#define SCPT4 4
+#define SCPT5 5
+#define SCPT6 6
+
+#define BPOCTR _SFR_MEM8(0xFB)
+#define OCPT0 0
+#define OCPT1 1
+#define OCPT2 2
+#define OCPT3 3
+#define OCPT4 4
+#define OCPT5 5
+
+#define BPHCTR _SFR_MEM8(0xFC)
+#define HCPT0 0
+#define HCPT1 1
+#define HCPT2 2
+#define HCPT3 3
+#define HCPT4 4
+#define HCPT5 5
+
+#define BPCR _SFR_MEM8(0xFD)
+#define CHCD 0
+#define DHCD 1
+#define COCD 2
+#define DOCD 3
+#define SCD 4
+#define EPID 5
+
+#define BPPLR _SFR_MEM8(0xFE)
+#define BPPL 0
+#define BPPLE 1
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define BPINT_vect_num 1
+#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */
+#define VREGMON_vect_num 2
+#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */
+#define INT0_vect_num 3
+#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */
+#define INT1_vect_num 4
+#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */
+#define INT2_vect_num 5
+#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */
+#define INT3_vect_num 6
+#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */
+#define PCINT0_vect_num 7
+#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */
+#define PCINT1_vect_num 8
+#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */
+#define WDT_vect_num 9
+#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */
+#define BGSCD_vect_num 10
+#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */
+#define CHDET_vect_num 11
+#define CHDET_vect _VECTOR(11) /* Charger Detect */
+#define TIMER1_IC_vect_num 12
+#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */
+#define TIMER1_COMPA_vect_num 13
+#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */
+#define TIMER1_COMPB_vect_num 14
+#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */
+#define TIMER1_OVF_vect_num 15
+#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */
+#define TIMER0_IC_vect_num 16
+#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */
+#define TIMER0_COMPA_vect_num 17
+#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */
+#define TIMER0_COMPB_vect_num 18
+#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */
+#define TIMER0_OVF_vect_num 19
+#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */
+#define TWIBUSCD_vect_num 20
+#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */
+#define TWI_vect_num 21
+#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */
+#define SPI_STC_vect_num 22
+#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */
+#define VADC_vect_num 23
+#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */
+#define CCADC_CONV_vect_num 24
+#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */
+#define CCADC_REG_CUR_vect_num 25
+#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */
+#define CCADC_ACC_vect_num 26
+#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */
+#define EE_READY_vect_num 27
+#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */
+#define SPM_vect_num 28
+#define SPM_vect _VECTOR(28) /* SPM Ready */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (29 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (1024)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (NA)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x3FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */
+#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */
+#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */
+#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */
+#define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */
+#define HFUSE_DEFAULT (FUSE_DUVRDINIT & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x0D
+
+
+/* Device Pin Definitions */
+#define PV2_DDR DDRV
+#define PV2_PORT PORTV
+#define PV2_PIN PINV
+#define PV2_BIT 2
+
+#define PV1_DDR DDRV
+#define PV1_PORT PORTV
+#define PV1_PIN PINV
+#define PV1_BIT 1
+
+#define NV_DDR DDRNV
+#define NV_PORT PORTNV
+#define NV_PIN PINNV
+#define NV_BIT NV
+
+#define VFET_DDR DDRVFET
+#define VFET_PORT PORTVFET
+#define VFET_PIN PINVFET
+#define VFET_BIT VFET
+
+#define CF1P_DDR DDRCF1P
+#define CF1P_PORT PORTCF1P
+#define CF1P_PIN PINCF1P
+#define CF1P_BIT CF1P
+
+#define CF1N_DDR DDRCF1N
+#define CF1N_PORT PORTCF1N
+#define CF1N_PIN PINCF1N
+#define CF1N_BIT CF1N
+
+#define CF2P_DDR DDRCF2P
+#define CF2P_PORT PORTCF2P
+#define CF2P_PIN PINCF2P
+#define CF2P_BIT CF2P
+
+#define CF2N_DDR DDRCF2N
+#define CF2N_PORT PORTCF2N
+#define CF2N_PIN PINCF2N
+#define CF2N_BIT CF2N
+
+#define VREG_DDR DDRVREG
+#define VREG_PORT PORTVREG
+#define VREG_PIN PINVREG
+#define VREG_BIT VREG
+
+#define VREF_DDR DDRVREF
+#define VREF_PORT PORTVREF
+#define VREF_PIN PINVREF
+#define VREF_BIT VREF
+
+#define VREFGND_DDR DDRVREFGND
+#define VREFGND_PORT PORTVREFGND
+#define VREFGND_PIN PINVREFGND
+#define VREFGND_BIT VREFGND
+
+#define PI_DDR DDRI
+#define PI_PORT PORTI
+#define PI_PIN PINI
+#define PI_BIT
+
+#define NI_DDR DDRNI
+#define NI_PORT PORTNI
+#define NI_PIN PINNI
+#define NI_BIT NI
+
+#define PA0_DDR DDRA
+#define PA0_PORT PORTA
+#define PA0_PIN PINA
+#define PA0_BIT 0
+
+#define PA1_DDR DDRA
+#define PA1_PORT PORTA
+#define PA1_PIN PINA
+#define PA1_BIT 1
+
+#define PA2_DDR DDRA
+#define PA2_PORT PORTA
+#define PA2_PIN PINA
+#define PA2_BIT 2
+
+#define PB0_DDR DDRB
+#define PB0_PORT PORTB
+#define PB0_PIN PINB
+#define PB0_BIT 0
+
+#define PB1_DDR DDRB
+#define PB1_PORT PORTB
+#define PB1_PIN PINB
+#define PB1_BIT 1
+
+#define PB2_DDR DDRB
+#define PB2_PORT PORTB
+#define PB2_PIN PINB
+#define PB2_BIT 2
+
+#define PB3_DDR DDRB
+#define PB3_PORT PORTB
+#define PB3_PIN PINB
+#define PB3_BIT 3
+
+#define PC0_DDR DDRC
+#define PC0_PORT PORTC
+#define PC0_PIN PINC
+#define PC0_BIT 0
+
+#define BATT_DDR DDRBATT
+#define BATT_PORT PORTBATT
+#define BATT_PIN PINBATT
+#define BATT_BIT BATT
+
+#define OC_DDR DDROC
+#define OC_PORT PORTOC
+#define OC_PIN PINOC
+#define OC_BIT OC
+
+#endif /* _AVR_ATmega16HVB_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom16m1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom16m1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom16m1.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom16m1.h Mon May 10 11:31:21 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom16m1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega16M1_H_
@@ -682,6 +682,7 @@
#define DACON _SFR_MEM8(0x90)
#define DAEN 0
+#define DAOE 1
#define DALA 2
#define DATS0 4
#define DATS1 5
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom16u2.h:1.1
--- /dev/null Mon May 10 12:10:53 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom16u2.h Mon May 10 11:31:21 2010
@@ -0,0 +1,980 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom16u2.h - definitions for ATmega16U2 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom16u2.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega16U2_H_
+#define _AVR_ATmega16U2_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define OCF1C 3
+#define ICF1 5
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+#define INTF3 3
+#define INTF4 4
+#define INTF5 5
+#define INTF6 6
+#define INTF7 7
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+#define INT3 3
+#define INT4 4
+#define INT5 5
+#define INT6 6
+#define INT7 7
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+#define EEAR11 3
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PLLP0 2
+#define PLLP1 3
+#define PLLP2 4
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define DWDR _SFR_IO8(0x31)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define USBRF 5
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define EIND _SFR_IO8(0x3C)
+#define EIND0 0
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define WDTCKD _SFR_MEM8(0x62)
+#define WCLKD0 0
+#define WCLKD1 1
+#define WDEWIE 2
+#define WDEWIF 3
+
+#define REGCR _SFR_MEM8(0x63)
+#define REGDIS 0
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRSPI 2
+#define PRTIM1 3
+#define PRTIM0 5
+
+#define PRR1 _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRUSB 7
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+#define ISC30 6
+#define ISC31 7
+
+#define EICRB _SFR_MEM8(0x6A)
+#define ISC40 0
+#define ISC41 1
+#define ISC50 2
+#define ISC51 3
+#define ISC60 4
+#define ISC61 5
+#define ISC70 6
+#define ISC71 7
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define OCIE1C 3
+#define ICIE1 5
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1C0 2
+#define COM1C1 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1C 5
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1C _SFR_MEM16(0x8C)
+
+#define OCR1CL _SFR_MEM8(0x8C)
+#define OCR1CL0 0
+#define OCR1CL1 1
+#define OCR1CL2 2
+#define OCR1CL3 3
+#define OCR1CL4 4
+#define OCR1CL5 5
+#define OCR1CL6 6
+#define OCR1CL7 7
+
+#define OCR1CH _SFR_MEM8(0x8D)
+#define OCR1CH0 0
+#define OCR1CH1 1
+#define OCR1CH2 2
+#define OCR1CH3 3
+#define OCR1CH4 4
+#define OCR1CH5 5
+#define OCR1CH6 6
+#define OCR1CH7 7
+
+#define UCSR1A _SFR_MEM8(0xC8)
+#define MPCM1 0
+#define U2X1 1
+#define UPE1 2
+#define DOR1 3
+#define FE1 4
+#define UDRE1 5
+#define TXC1 6
+#define RXC1 7
+
+#define UCSR1B _SFR_MEM8(0xC9)
+#define TXB81 0
+#define RXB81 1
+#define UCSZ12 2
+#define TXEN1 3
+#define RXEN1 4
+#define UDRIE1 5
+#define TXCIE1 6
+#define RXCIE1 7
+
+#define UCSR1C _SFR_MEM8(0xCA)
+#define UCPOL1 0
+#define UCSZ10 1
+#define UCSZ11 2
+#define USBS1 3
+#define UPM10 4
+#define UPM11 5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UCSR1D _SFR_MEM8(0xCB)
+#define RTSEN 0
+#define CTSEN 1
+
+#define UBRR1 _SFR_MEM16(0xCC)
+
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1_0 0
+#define UBRR1_1 1
+#define UBRR1_2 2
+#define UBRR1_3 3
+#define UBRR1_4 4
+#define UBRR1_5 5
+#define UBRR1_6 6
+#define UBRR1_7 7
+
+#define UBRR1H _SFR_MEM8(0xCD)
+#define UBRR1_8 0
+#define UBRR1_9 1
+#define UBRR1_10 2
+#define UBRR1_11 3
+
+#define UDR1 _SFR_MEM8(0xCE)
+#define UDR1_0 0
+#define UDR1_1 1
+#define UDR1_2 2
+#define UDR1_3 3
+#define UDR1_4 4
+#define UDR1_5 5
+#define UDR1_6 6
+#define UDR1_7 7
+
+#define CLKSEL0 _SFR_MEM8(0xD0)
+#define CLKS 0
+#define EXTE 2
+#define RCE 3
+#define EXSUT0 4
+#define EXSUT1 5
+#define RCSUT0 6
+#define RCSUT1 7
+
+#define CLKSEL1 _SFR_MEM8(0xD1)
+#define EXCKSEL0 0
+#define EXCKSEL1 1
+#define EXCKSEL2 2
+#define EXCKSEL3 3
+#define RCCKSEL0 4
+#define RCCKSEL1 5
+#define RCCKSEL2 6
+#define RCCKSEL3 7
+
+#define CLKSTA _SFR_MEM8(0xD2)
+#define EXTON 0
+#define RCON 1
+
+#define USBCON _SFR_MEM8(0xD8)
+#define FRZCLK 5
+#define USBE 7
+
+#define UDCON _SFR_MEM8(0xE0)
+#define DETACH 0
+#define RMWKUP 1
+#define RSTCPU 2
+
+#define UDINT _SFR_MEM8(0xE1)
+#define SUSPI 0
+#define SOFI 2
+#define EORSTI 3
+#define WAKEUPI 4
+#define EORSMI 5
+#define UPRSMI 6
+
+#define UDIEN _SFR_MEM8(0xE2)
+#define SUSPE 0
+#define SOFE 2
+#define EORSTE 3
+#define WAKEUPE 4
+#define EORSME 5
+#define UPRSME 6
+
+#define UDADDR _SFR_MEM8(0xE3)
+#define UADD0 0
+#define UADD1 1
+#define UADD2 2
+#define UADD3 3
+#define UADD4 4
+#define UADD5 5
+#define UADD6 6
+#define ADDEN 7
+
+#define UDFNUM _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define FNUM0 0
+#define FNUM1 1
+#define FNUM2 2
+#define FNUM3 3
+#define FNUM4 4
+#define FNUM5 5
+#define FNUM6 6
+#define FNUM7 7
+
+#define UDFNUMH _SFR_MEM8(0xE5)
+#define FNUM8 0
+#define FNUM9 1
+#define FNUM10 2
+
+#define UDMFN _SFR_MEM8(0xE6)
+#define FNCERR 4
+
+#define UEINTX _SFR_MEM8(0xE8)
+#define TXINI 0
+#define STALLEDI 1
+#define RXOUTI 2
+#define RXSTPI 3
+#define NAKOUTI 4
+#define RWAL 5
+#define NAKINI 6
+#define FIFOCON 7
+
+#define UENUM _SFR_MEM8(0xE9)
+#define EPNUM0 0
+#define EPNUM1 1
+#define EPNUM2 2
+
+#define UERST _SFR_MEM8(0xEA)
+#define EPRST0 0
+#define EPRST1 1
+#define EPRST2 2
+#define EPRST3 3
+#define EPRST4 4
+
+#define UECONX _SFR_MEM8(0xEB)
+#define EPEN 0
+#define RSTDT 3
+#define STALLRQC 4
+#define STALLRQ 5
+
+#define UECFG0X _SFR_MEM8(0xEC)
+#define EPDIR 0
+#define EPTYPE0 6
+#define EPTYPE1 7
+
+#define UECFG1X _SFR_MEM8(0xED)
+#define ALLOC 1
+#define EPBK0 2
+#define EPBK1 3
+#define EPSIZE0 4
+#define EPSIZE1 5
+#define EPSIZE2 6
+
+#define UESTA0X _SFR_MEM8(0xEE)
+#define NBUSYBK0 0
+#define NBUSYBK1 1
+#define DTSEQ0 2
+#define DTSEQ1 3
+#define UNDERFI 5
+#define OVERFI 6
+#define CFGOK 7
+
+#define UESTA1X _SFR_MEM8(0xEF)
+#define CURRBK0 0
+#define CURRBK1 1
+#define CTRLDIR 2
+
+#define UEIENX _SFR_MEM8(0xF0)
+#define TXINE 0
+#define STALLEDE 1
+#define RXOUTE 2
+#define RXSTPE 3
+#define NAKOUTE 4
+#define NAKINE 6
+#define FLERRE 7
+
+#define UEDATX _SFR_MEM8(0xF1)
+#define DAT0 0
+#define DAT1 1
+#define DAT2 2
+#define DAT3 3
+#define DAT4 4
+#define DAT5 5
+#define DAT6 6
+#define DAT7 7
+
+#define UEBCLX _SFR_MEM8(0xF2)
+#define BYCT0 0
+#define BYCT1 1
+#define BYCT2 2
+#define BYCT3 3
+#define BYCT4 4
+#define BYCT5 5
+#define BYCT6 6
+#define BYCT7 7
+
+#define UEINT _SFR_MEM8(0xF4)
+#define EPINT0 0
+#define EPINT1 1
+#define EPINT2 2
+#define EPINT3 3
+#define EPINT4 4
+
+#define PS2CON _SFR_MEM8(0xFA)
+#define PS2EN 0
+
+#define UPOE _SFR_MEM8(0xFB)
+#define DMI 0
+#define DPI 1
+#define DATAI 2
+#define SCKI 3
+#define UPDRV0 4
+#define UPDRV1 5
+#define UPWE0 6
+#define UPWE1 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define INT2_vect_num 3
+#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
+#define INT3_vect_num 4
+#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */
+#define INT4_vect_num 5
+#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */
+#define INT5_vect_num 6
+#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */
+#define INT6_vect_num 7
+#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */
+#define INT7_vect_num 8
+#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */
+#define PCINT0_vect_num 9
+#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 10
+#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */
+#define USB_GEN_vect_num 11
+#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */
+#define USB_COM_vect_num 12
+#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */
+#define WDT_vect_num 13
+#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */
+#define TIMER1_CAPT_vect_num 14
+#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */
+#define TIMER1_COMPA_vect_num 15
+#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */
+#define TIMER0_COMPA_vect_num 19
+#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 20
+#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */
+#define TIMER0_OVF_vect_num 21
+#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 22
+#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */
+#define USART1_RX_vect_num 23
+#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */
+#define USART1_UDRE_vect_num 24
+#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */
+#define USART1_TX_vect_num 25
+#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */
+#define ANALOG_COMP_vect_num 26
+#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */
+#define EE_READY_vect_num 27
+#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */
+#define SPM_READY_vect_num 28
+#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */
+#define TIMER1_COMPB_vect_num 16
+#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPC_vect_num 17
+#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */
+#define TIMER1_OVF_vect_num 18
+#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (512)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x3FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */
+#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */
+#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x89
+
+
+/* Device Pin Definitions */
+#endif /* _AVR_ATmega16U2_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom16u4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom16u4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom16u4.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom16u4.h Mon May 10 11:31:21 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom16u4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega16U4_H_
diff -u rtems/cpukit/score/cpu/avr/avr/iom2560.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom2560.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom2560.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom2560.h Mon May 10 11:31:21 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005 Anatoly Sokolov
+/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom2561.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom2561.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom2561.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom2561.h Mon May 10 11:31:21 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005 Anatoly Sokolov
+/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom32.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom32.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom32.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom32.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom32.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -684,7 +684,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom323.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom323.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom323.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom323.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom323.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -676,7 +676,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom324.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom324.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom324.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom324.h Mon May 10 11:31:21 2010
@@ -82,7 +82,13 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature (ATmega324P) */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x08
#endif /* _AVR_IOM324_H_ */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom324pa.h:1.1
--- /dev/null Mon May 10 12:10:54 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom324pa.h Mon May 10 11:31:21 2010
@@ -0,0 +1,1355 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom324pa.h - definitions for ATmega324PA */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom324pa.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega324PA_H_
+#define _AVR_ATmega324PA_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIFR2 _SFR_IO8(0x17)
+#define TOV2 0
+#define OCF2A 1
+#define OCF2B 2
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+#define PCIF2 2
+#define PCIF3 3
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+#define EEAR11 3
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR0 _SFR_IO8(0x2C)
+#define SPR00 0
+#define SPR10 1
+#define CPHA0 2
+#define CPOL0 3
+#define MSTR0 4
+#define DORD0 5
+#define SPE0 6
+#define SPIE0 7
+
+#define SPSR0 _SFR_IO8(0x2D)
+#define SPI2X0 0
+#define WCOL0 6
+#define SPIF0 7
+
+#define SPDR0 _SFR_IO8(0x2E)
+#define SPDRB0 0
+#define SPDRB1 1
+#define SPDRB2 2
+#define SPDRB3 3
+#define SPDRB4 4
+#define SPDRB5 5
+#define SPDRB6 6
+#define SPDRB7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define OCDR _SFR_IO8(0x31)
+#define OCDR0 0
+#define OCDR1 1
+#define OCDR2 2
+#define OCDR3 3
+#define OCDR4 4
+#define OCDR5 5
+#define OCDR6 6
+#define OCDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define JTRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+#define JTD 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSART0 1
+#define PRSPI 2
+#define PRTIM1 3
+#define PRUSART1 4
+#define PRTIM0 5
+#define PRTIM2 6
+#define PRTWI 7
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+#define PCIE2 2
+#define PCIE3 3
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define TIMSK2 _SFR_MEM8(0x70)
+#define TOIE2 0
+#define OCIE2A 1
+#define OCIE2B 2
+
+#define PCMSK3 _SFR_MEM8(0x73)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+#define PCINT28 4
+#define PCINT29 5
+#define PCINT30 6
+#define PCINT31 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_MEM16(0x78)
+#endif
+#define ADCW _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define TCCR2A _SFR_MEM8(0xB0)
+#define WGM20 0
+#define WGM21 1
+#define COM2B0 4
+#define COM2B1 5
+#define COM2A0 6
+#define COM2A1 7
+
+#define TCCR2B _SFR_MEM8(0xB1)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM22 3
+#define FOC2B 6
+#define FOC2A 7
+
+#define TCNT2 _SFR_MEM8(0xB2)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define OCR2A _SFR_MEM8(0xB3)
+#define OCR2A_0 0
+#define OCR2A_1 1
+#define OCR2A_2 2
+#define OCR2A_3 3
+#define OCR2A_4 4
+#define OCR2A_5 5
+#define OCR2A_6 6
+#define OCR2A_7 7
+
+#define OCR2B _SFR_MEM8(0xB4)
+#define OCR2B_0 0
+#define OCR2B_1 1
+#define OCR2B_2 2
+#define OCR2B_3 3
+#define OCR2B_4 4
+#define OCR2B_5 5
+#define OCR2B_6 6
+#define OCR2B_7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB 4
+#define AS2 5
+#define EXCLK 6
+
+#define TWBR _SFR_MEM8(0xB8)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_MEM8(0xB9)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_MEM8(0xBA)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_MEM8(0xBB)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#define TWCR _SFR_MEM8(0xBC)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define TWAMR _SFR_MEM8(0xBD)
+#define TWAM0 1
+#define TWAM1 2
+#define TWAM2 3
+#define TWAM3 4
+#define TWAM4 5
+#define TWAM5 6
+#define TWAM6 7
+
+#define UCSR0A _SFR_MEM8(0xC0)
+#define MPCM0 0
+#define U2X0 1
+#define UPE0 2
+#define DOR0 3
+#define FE0 4
+#define UDRE0 5
+#define TXC0 6
+#define RXC0 7
+
+#define UCSR0B _SFR_MEM8(0xC1)
+#define TXB80 0
+#define RXB80 1
+#define UCSZ02 2
+#define TXEN0 3
+#define RXEN0 4
+#define UDRIE0 5
+#define TXCIE0 6
+#define RXCIE0 7
+
+#define UCSR0C _SFR_MEM8(0xC2)
+#define UCPOL0 0
+#define UCSZ00 1
+#define UCSZ01 2
+#define USBS0 3
+#define UPM00 4
+#define UPM01 5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UBRR0 _SFR_MEM16(0xC4)
+
+#define UBRR0L _SFR_MEM8(0xC4)
+#define _UBRR0 0
+#define _UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UBRR0H _SFR_MEM8(0xC5)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UDR0 _SFR_MEM8(0xC6)
+#define UDR0_0 0
+#define UDR0_1 1
+#define UDR0_2 2
+#define UDR0_3 3
+#define UDR0_4 4
+#define UDR0_5 5
+#define UDR0_6 6
+#define UDR0_7 7
+
+#define UCSR1A _SFR_MEM8(0xC8)
+#define MPCM1 0
+#define U2X1 1
+#define UPE1 2
+#define DOR1 3
+#define FE1 4
+#define UDRE1 5
+#define TXC1 6
+#define RXC1 7
+
+#define UCSR1B _SFR_MEM8(0xC9)
+#define TXB81 0
+#define RXB81 1
+#define UCSZ12 2
+#define TXEN1 3
+#define RXEN1 4
+#define UDRIE1 5
+#define TXCIE1 6
+#define RXCIE1 7
+
+#define UCSR1C _SFR_MEM8(0xCA)
+#define UCPOL1 0
+#define UCSZ10 1
+#define UCSZ11 2
+#define USBS1 3
+#define UPM10 4
+#define UPM11 5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UBRR1 _SFR_MEM16(0xCC)
+
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR_0 0
+#define UBRR_1 1
+#define UBRR_2 2
+#define UBRR_3 3
+#define UBRR_4 4
+#define UBRR_5 5
+#define UBRR_6 6
+#define UBRR_7 7
+
+#define UBRR1H _SFR_MEM8(0xCD)
+#define UBRR_8 0
+#define UBRR_9 1
+#define UBRR_10 2
+#define UBRR_11 3
+
+#define UDR1 _SFR_MEM8(0xCE)
+#define UDR1_0 0
+#define UDR1_1 1
+#define UDR1_2 2
+#define UDR1_3 3
+#define UDR1_4 4
+#define UDR1_5 5
+#define UDR1_6 6
+#define UDR1_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define INT2_vect_num 3
+#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
+#define PCINT0_vect_num 4
+#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 5
+#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
+#define PCINT2_vect_num 6
+#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */
+#define PCINT3_vect_num 7
+#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */
+#define WDT_vect_num 8
+#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */
+#define TIMER2_COMPA_vect_num 9
+#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect_num 10
+#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */
+#define TIMER2_OVF_vect_num 11
+#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect_num 12
+#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 13
+#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect_num 14
+#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */
+#define TIMER1_OVF_vect_num 15
+#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */
+#define TIMER0_COMPA_vect_num 16
+#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 17
+#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */
+#define TIMER0_OVF_vect_num 18
+#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 19
+#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */
+#define USART0_RX_vect_num 20
+#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */
+#define USART0_UDRE_vect_num 21
+#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */
+#define USART0_TX_vect_num 22
+#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */
+#define ANALOG_COMP_vect_num 23
+#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
+#define ADC_vect_num 24
+#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */
+#define EE_READY_vect_num 25
+#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */
+#define TWI_vect_num 26
+#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */
+#define SPM_READY_vect_num 27
+#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */
+#define USART1_RX_vect_num 28
+#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */
+#define USART1_UDRE_vect_num 29
+#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */
+#define USART1_TX_vect_num 30
+#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (2048)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (0x0)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x3FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x7FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
+#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
+#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x11
+
+
+/* Device Pin Definitions */
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 5
+
+#define PCINT13_DDR DDRB
+#define PCINT13_PORT PORTB
+#define PCINT13_PIN PINB
+#define PCINT13_BIT 5
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 6
+
+#define PCINT14_DDR DDRB
+#define PCINT14_PORT PORTB
+#define PCINT14_PIN PINB
+#define PCINT14_BIT 6
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 7
+
+#define PCINT15_DDR DDRB
+#define PCINT15_PORT PORTB
+#define PCINT15_PIN PINB
+#define PCINT15_BIT 7
+
+#define RXD_DDR DDRD
+#define RXD_PORT PORTD
+#define RXD_PIN PIND
+#define RXD_BIT 0
+
+#define PCINT24_DDR DDRD
+#define PCINT24_PORT PORTD
+#define PCINT24_PIN PIND
+#define PCINT24_BIT 0
+
+#define TXD_DDR DDRD
+#define TXD_PORT PORTD
+#define TXD_PIN PIND
+#define TXD_BIT 1
+
+#define PCINT25_DDR DDRD
+#define PCINT25_PORT PORTD
+#define PCINT25_PIN PIND
+#define PCINT25_BIT 1
+
+#define INT0_DDR DDRD
+#define INT0_PORT PORTD
+#define INT0_PIN PIND
+#define INT0_BIT 2
+
+#define PCINT26_DDR DDRD
+#define PCINT26_PORT PORTD
+#define PCINT26_PIN PIND
+#define PCINT26_BIT 2
+
+#define INT1_DDR DDRD
+#define INT1_PORT PORTD
+#define INT1_PIN PIND
+#define INT1_BIT 3
+
+#define PCINT27_DDR DDRD
+#define PCINT27_PORT PORTD
+#define PCINT27_PIN PIND
+#define PCINT27_BIT 3
+
+#define OC1B_DDR DDRD
+#define OC1B_PORT PORTD
+#define OC1B_PIN PIND
+#define OC1B_BIT 4
+
+#define PCINT28_DDR DDRD
+#define PCINT28_PORT PORTD
+#define PCINT28_PIN PIND
+#define PCINT28_BIT 4
+
+#define OC1A_DDR DDRD
+#define OC1A_PORT PORTD
+#define OC1A_PIN PIND
+#define OC1A_BIT 5
+
+#define PCINT29_DDR DDRD
+#define PCINT29_PORT PORTD
+#define PCINT29_PIN PIND
+#define PCINT29_BIT 5
+
+#define ICP_DDR DDRD
+#define ICP_PORT PORTD
+#define ICP_PIN PIND
+#define ICP_BIT 6
+
+#define OC2B_DDR DDRD
+#define OC2B_PORT PORTD
+#define OC2B_PIN PIND
+#define OC2B_BIT 6
+
+#define PCINT30_DDR DDRD
+#define PCINT30_PORT PORTD
+#define PCINT30_PIN PIND
+#define PCINT30_BIT 6
+
+#define OC2A_DDR DDRD
+#define OC2A_PORT PORTD
+#define OC2A_PIN PIND
+#define OC2A_BIT 7
+
+#define PCINT31_DDR DDRD
+#define PCINT31_PORT PORTD
+#define PCINT31_PIN PIND
+#define PCINT31_BIT 7
+
+#define SCL_DDR DDRC
+#define SCL_PORT PORTC
+#define SCL_PIN PINC
+#define SCL_BIT 0
+
+#define PCINT16_DDR DDRC
+#define PCINT16_PORT PORTC
+#define PCINT16_PIN PINC
+#define PCINT16_BIT 0
+
+#define SDA_DDR DDRC
+#define SDA_PORT PORTC
+#define SDA_PIN PINC
+#define SDA_BIT 1
+
+#define PCINT17_DDR DDRC
+#define PCINT17_PORT PORTC
+#define PCINT17_PIN PINC
+#define PCINT17_BIT 1
+
+#define PCINT18_DDR DDRC
+#define PCINT18_PORT PORTC
+#define PCINT18_PIN PINC
+#define PCINT18_BIT 2
+
+#define PCINT19_DDR DDRC
+#define PCINT19_PORT PORTC
+#define PCINT19_PIN PINC
+#define PCINT19_BIT 3
+
+#define PCINT20_DDR DDRC
+#define PCINT20_PORT PORTC
+#define PCINT20_PIN PINC
+#define PCINT20_BIT 4
+
+#define PCINT21_DDR DDRC
+#define PCINT21_PORT PORTC
+#define PCINT21_PIN PINC
+#define PCINT21_BIT 5
+
+#define PCINT22_DDR DDRC
+#define PCINT22_PORT PORTC
+#define PCINT22_PIN PINC
+#define PCINT22_BIT 6
+
+#define PCINT23_DDR DDRC
+#define PCINT23_PORT PORTC
+#define PCINT23_PIN PINC
+#define PCINT23_BIT 7
+
+#define ADC7_DDR DDRA
+#define ADC7_PORT PORTA
+#define ADC7_PIN PINA
+#define ADC7_BIT 7
+
+#define PCINT7_DDR DDRA
+#define PCINT7_PORT PORTA
+#define PCINT7_PIN PINA
+#define PCINT7_BIT 7
+
+#define ADC6_DDR DDRA
+#define ADC6_PORT PORTA
+#define ADC6_PIN PINA
+#define ADC6_BIT 6
+
+#define PCINT6_DDR DDRA
+#define PCINT6_PORT PORTA
+#define PCINT6_PIN PINA
+#define PCINT6_BIT 6
+
+#define ADC5_DDR DDRA
+#define ADC5_PORT PORTA
+#define ADC5_PIN PINA
+#define ADC5_BIT 5
+
+#define PCINT5_DDR DDRA
+#define PCINT5_PORT PORTA
+#define PCINT5_PIN PINA
+#define PCINT5_BIT 5
+
+#define ADC4_DDR DDRA
+#define ADC4_PORT PORTA
+#define ADC4_PIN PINA
+#define ADC4_BIT 4
+
+#define PCINT4_DDR DDRA
+#define PCINT4_PORT PORTA
+#define PCINT4_PIN PINA
+#define PCINT4_BIT 4
+
+#define ADC3_DDR DDRA
+#define ADC3_PORT PORTA
+#define ADC3_PIN PINA
+#define ADC3_BIT 3
+
+#define PCINT3_DDR DDRA
+#define PCINT3_PORT PORTA
+#define PCINT3_PIN PINA
+#define PCINT3_BIT 3
+
+#define ADC2_DDR DDRA
+#define ADC2_PORT PORTA
+#define ADC2_PIN PINA
+#define ADC2_BIT 2
+
+#define PCINT2_DDR DDRA
+#define PCINT2_PORT PORTA
+#define PCINT2_PIN PINA
+#define PCINT2_BIT 2
+
+#define ADC1_DDR DDRA
+#define ADC1_PORT PORTA
+#define ADC1_PIN PINA
+#define ADC1_BIT 1
+
+#define PCINT1_DDR DDRA
+#define PCINT1_PORT PORTA
+#define PCINT1_PIN PINA
+#define PCINT1_BIT 1
+
+#define ADC0_DDR DDRA
+#define ADC0_PORT PORTA
+#define ADC0_PIN PINA
+#define ADC0_BIT 0
+
+#define PCINT0_DDR DDRA
+#define PCINT0_PORT PORTA
+#define PCINT0_PIN PINA
+#define PCINT0_BIT 0
+
+#define XCK_DDR DDRB
+#define XCK_PORT PORTB
+#define XCK_PIN PINB
+#define XCK_BIT 0
+
+#define T0_DDR DDRB
+#define T0_PORT PORTB
+#define T0_PIN PINB
+#define T0_BIT 0
+
+#define PCINT8_DDR DDRB
+#define PCINT8_PORT PORTB
+#define PCINT8_PIN PINB
+#define PCINT8_BIT 0
+
+#define T1_DDR DDRB
+#define T1_PORT PORTB
+#define T1_PIN PINB
+#define T1_BIT 1
+
+#define CLKO_DDR DDRB
+#define CLKO_PORT PORTB
+#define CLKO_PIN PINB
+#define CLKO_BIT 1
+
+#define PCINT9_DDR DDRB
+#define PCINT9_PORT PORTB
+#define PCINT9_PIN PINB
+#define PCINT9_BIT 1
+
+#define AIN0_DDR DDRB
+#define AIN0_PORT PORTB
+#define AIN0_PIN PINB
+#define AIN0_BIT 2
+
+#define INT2_DDR DDRB
+#define INT2_PORT PORTB
+#define INT2_PIN PINB
+#define INT2_BIT 2
+
+#define PCINT10_DDR DDRB
+#define PCINT10_PORT PORTB
+#define PCINT10_PIN PINB
+#define PCINT10_BIT 2
+
+#define AIN1_DDR DDRB
+#define AIN1_PORT PORTB
+#define AIN1_PIN PINB
+#define AIN1_BIT 3
+
+#define OC0A_DDR DDRB
+#define OC0A_PORT PORTB
+#define OC0A_PIN PINB
+#define OC0A_BIT 3
+
+#define PCINT11_DDR DDRB
+#define PCINT11_PORT PORTB
+#define PCINT11_PIN PINB
+#define PCINT11_BIT 3
+
+#define SS_DDR DDRB
+#define SS_PORT PORTB
+#define SS_PIN PINB
+#define SS_BIT 4
+
+#define OC0B_DDR DDRB
+#define OC0B_PORT PORTB
+#define OC0B_PIN PINB
+#define OC0B_BIT 4
+
+#define PCINT12_DDR DDRB
+#define PCINT12_PORT PORTB
+#define PCINT12_PIN PINB
+#define PCINT12_BIT 4
+
+#endif /* _AVR_ATmega324PA_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom325.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom325.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom325.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom325.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom325.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -809,7 +809,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom3250.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom3250.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom3250.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom3250.h Mon May 10 11:31:21 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom3250.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -899,7 +899,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom328p.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom328p.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom328p.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom328p.h Mon May 10 11:31:21 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iom328p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOM328P_H_
@@ -797,7 +797,7 @@
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
@@ -863,7 +863,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom329.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom329.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom329.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom329.h Mon May 10 11:31:21 2010
@@ -1,5 +1,5 @@
/* Copyright (c) 2004 Eric B. Weddington
- Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
+ Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,7 @@
# define _AVR_IOXXX_H_ "iom329.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -991,7 +991,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom3290.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom3290.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom3290.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom3290.h Mon May 10 11:31:21 2010
@@ -1,5 +1,5 @@
/* Copyright (c) 2004 Eric B. Weddington
- Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
+ Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,7 @@
# define _AVR_IOXXX_H_ "iom3290.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -1143,7 +1143,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom32c1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom32c1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom32c1.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom32c1.h Mon May 10 11:31:21 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom32c1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega32C1_H_
@@ -682,6 +682,7 @@
#define DACON _SFR_MEM8(0x90)
#define DAEN 0
+#define DAOE 1
#define DALA 2
#define DATS0 4
#define DATS1 5
diff -u rtems/cpukit/score/cpu/avr/avr/iom32hvb.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom32hvb.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom32hvb.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom32hvb.h Mon May 10 11:31:22 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iom32hvb.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOM32HVB_H_
diff -u rtems/cpukit/score/cpu/avr/avr/iom32m1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom32m1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom32m1.h:1.2 Mon Nov 30 10:01:44 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom32m1.h Mon May 10 11:31:22 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom32m1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega32M1_H_
@@ -682,6 +682,7 @@
#define DACON _SFR_MEM8(0x90)
#define DAEN 0
+#define DAOE 1
#define DALA 2
#define DATS0 4
#define DATS1 5
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom32u2.h:1.1
--- /dev/null Mon May 10 12:10:55 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom32u2.h Mon May 10 11:31:22 2010
@@ -0,0 +1,980 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom32u2.h - definitions for ATmega32U2 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom32u2.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega32U2_H_
+#define _AVR_ATmega32U2_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define OCF1C 3
+#define ICF1 5
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+#define INTF3 3
+#define INTF4 4
+#define INTF5 5
+#define INTF6 6
+#define INTF7 7
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+#define INT3 3
+#define INT4 4
+#define INT5 5
+#define INT6 6
+#define INT7 7
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+#define EEAR11 3
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PLLP0 2
+#define PLLP1 3
+#define PLLP2 4
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define DWDR _SFR_IO8(0x31)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define USBRF 5
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define EIND _SFR_IO8(0x3C)
+#define EIND0 0
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define WDTCKD _SFR_MEM8(0x62)
+#define WCLKD0 0
+#define WCLKD1 1
+#define WDEWIE 2
+#define WDEWIF 3
+
+#define REGCR _SFR_MEM8(0x63)
+#define REGDIS 0
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRSPI 2
+#define PRTIM1 3
+#define PRTIM0 5
+
+#define PRR1 _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRUSB 7
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+#define ISC30 6
+#define ISC31 7
+
+#define EICRB _SFR_MEM8(0x6A)
+#define ISC40 0
+#define ISC41 1
+#define ISC50 2
+#define ISC51 3
+#define ISC60 4
+#define ISC61 5
+#define ISC70 6
+#define ISC71 7
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define OCIE1C 3
+#define ICIE1 5
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1C0 2
+#define COM1C1 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1C 5
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1C _SFR_MEM16(0x8C)
+
+#define OCR1CL _SFR_MEM8(0x8C)
+#define OCR1CL0 0
+#define OCR1CL1 1
+#define OCR1CL2 2
+#define OCR1CL3 3
+#define OCR1CL4 4
+#define OCR1CL5 5
+#define OCR1CL6 6
+#define OCR1CL7 7
+
+#define OCR1CH _SFR_MEM8(0x8D)
+#define OCR1CH0 0
+#define OCR1CH1 1
+#define OCR1CH2 2
+#define OCR1CH3 3
+#define OCR1CH4 4
+#define OCR1CH5 5
+#define OCR1CH6 6
+#define OCR1CH7 7
+
+#define UCSR1A _SFR_MEM8(0xC8)
+#define MPCM1 0
+#define U2X1 1
+#define UPE1 2
+#define DOR1 3
+#define FE1 4
+#define UDRE1 5
+#define TXC1 6
+#define RXC1 7
+
+#define UCSR1B _SFR_MEM8(0xC9)
+#define TXB81 0
+#define RXB81 1
+#define UCSZ12 2
+#define TXEN1 3
+#define RXEN1 4
+#define UDRIE1 5
+#define TXCIE1 6
+#define RXCIE1 7
+
+#define UCSR1C _SFR_MEM8(0xCA)
+#define UCPOL1 0
+#define UCSZ10 1
+#define UCSZ11 2
+#define USBS1 3
+#define UPM10 4
+#define UPM11 5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UCSR1D _SFR_MEM8(0xCB)
+#define RTSEN 0
+#define CTSEN 1
+
+#define UBRR1 _SFR_MEM16(0xCC)
+
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1_0 0
+#define UBRR1_1 1
+#define UBRR1_2 2
+#define UBRR1_3 3
+#define UBRR1_4 4
+#define UBRR1_5 5
+#define UBRR1_6 6
+#define UBRR1_7 7
+
+#define UBRR1H _SFR_MEM8(0xCD)
+#define UBRR1_8 0
+#define UBRR1_9 1
+#define UBRR1_10 2
+#define UBRR1_11 3
+
+#define UDR1 _SFR_MEM8(0xCE)
+#define UDR1_0 0
+#define UDR1_1 1
+#define UDR1_2 2
+#define UDR1_3 3
+#define UDR1_4 4
+#define UDR1_5 5
+#define UDR1_6 6
+#define UDR1_7 7
+
+#define CLKSEL0 _SFR_MEM8(0xD0)
+#define CLKS 0
+#define EXTE 2
+#define RCE 3
+#define EXSUT0 4
+#define EXSUT1 5
+#define RCSUT0 6
+#define RCSUT1 7
+
+#define CLKSEL1 _SFR_MEM8(0xD1)
+#define EXCKSEL0 0
+#define EXCKSEL1 1
+#define EXCKSEL2 2
+#define EXCKSEL3 3
+#define RCCKSEL0 4
+#define RCCKSEL1 5
+#define RCCKSEL2 6
+#define RCCKSEL3 7
+
+#define CLKSTA _SFR_MEM8(0xD2)
+#define EXTON 0
+#define RCON 1
+
+#define USBCON _SFR_MEM8(0xD8)
+#define FRZCLK 5
+#define USBE 7
+
+#define UDCON _SFR_MEM8(0xE0)
+#define DETACH 0
+#define RMWKUP 1
+#define RSTCPU 2
+
+#define UDINT _SFR_MEM8(0xE1)
+#define SUSPI 0
+#define SOFI 2
+#define EORSTI 3
+#define WAKEUPI 4
+#define EORSMI 5
+#define UPRSMI 6
+
+#define UDIEN _SFR_MEM8(0xE2)
+#define SUSPE 0
+#define SOFE 2
+#define EORSTE 3
+#define WAKEUPE 4
+#define EORSME 5
+#define UPRSME 6
+
+#define UDADDR _SFR_MEM8(0xE3)
+#define UADD0 0
+#define UADD1 1
+#define UADD2 2
+#define UADD3 3
+#define UADD4 4
+#define UADD5 5
+#define UADD6 6
+#define ADDEN 7
+
+#define UDFNUM _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define FNUM0 0
+#define FNUM1 1
+#define FNUM2 2
+#define FNUM3 3
+#define FNUM4 4
+#define FNUM5 5
+#define FNUM6 6
+#define FNUM7 7
+
+#define UDFNUMH _SFR_MEM8(0xE5)
+#define FNUM8 0
+#define FNUM9 1
+#define FNUM10 2
+
+#define UDMFN _SFR_MEM8(0xE6)
+#define FNCERR 4
+
+#define UEINTX _SFR_MEM8(0xE8)
+#define TXINI 0
+#define STALLEDI 1
+#define RXOUTI 2
+#define RXSTPI 3
+#define NAKOUTI 4
+#define RWAL 5
+#define NAKINI 6
+#define FIFOCON 7
+
+#define UENUM _SFR_MEM8(0xE9)
+#define EPNUM0 0
+#define EPNUM1 1
+#define EPNUM2 2
+
+#define UERST _SFR_MEM8(0xEA)
+#define EPRST0 0
+#define EPRST1 1
+#define EPRST2 2
+#define EPRST3 3
+#define EPRST4 4
+
+#define UECONX _SFR_MEM8(0xEB)
+#define EPEN 0
+#define RSTDT 3
+#define STALLRQC 4
+#define STALLRQ 5
+
+#define UECFG0X _SFR_MEM8(0xEC)
+#define EPDIR 0
+#define EPTYPE0 6
+#define EPTYPE1 7
+
+#define UECFG1X _SFR_MEM8(0xED)
+#define ALLOC 1
+#define EPBK0 2
+#define EPBK1 3
+#define EPSIZE0 4
+#define EPSIZE1 5
+#define EPSIZE2 6
+
+#define UESTA0X _SFR_MEM8(0xEE)
+#define NBUSYBK0 0
+#define NBUSYBK1 1
+#define DTSEQ0 2
+#define DTSEQ1 3
+#define UNDERFI 5
+#define OVERFI 6
+#define CFGOK 7
+
+#define UESTA1X _SFR_MEM8(0xEF)
+#define CURRBK0 0
+#define CURRBK1 1
+#define CTRLDIR 2
+
+#define UEIENX _SFR_MEM8(0xF0)
+#define TXINE 0
+#define STALLEDE 1
+#define RXOUTE 2
+#define RXSTPE 3
+#define NAKOUTE 4
+#define NAKINE 6
+#define FLERRE 7
+
+#define UEDATX _SFR_MEM8(0xF1)
+#define DAT0 0
+#define DAT1 1
+#define DAT2 2
+#define DAT3 3
+#define DAT4 4
+#define DAT5 5
+#define DAT6 6
+#define DAT7 7
+
+#define UEBCLX _SFR_MEM8(0xF2)
+#define BYCT0 0
+#define BYCT1 1
+#define BYCT2 2
+#define BYCT3 3
+#define BYCT4 4
+#define BYCT5 5
+#define BYCT6 6
+#define BYCT7 7
+
+#define UEINT _SFR_MEM8(0xF4)
+#define EPINT0 0
+#define EPINT1 1
+#define EPINT2 2
+#define EPINT3 3
+#define EPINT4 4
+
+#define PS2CON _SFR_MEM8(0xFA)
+#define PS2EN 0
+
+#define UPOE _SFR_MEM8(0xFB)
+#define DMI 0
+#define DPI 1
+#define DATAI 2
+#define SCKI 3
+#define UPDRV0 4
+#define UPDRV1 5
+#define UPWE0 6
+#define UPWE1 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define INT2_vect_num 3
+#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
+#define INT3_vect_num 4
+#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */
+#define INT4_vect_num 5
+#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */
+#define INT5_vect_num 6
+#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */
+#define INT6_vect_num 7
+#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */
+#define INT7_vect_num 8
+#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */
+#define PCINT0_vect_num 9
+#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 10
+#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */
+#define USB_GEN_vect_num 11
+#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */
+#define USB_COM_vect_num 12
+#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */
+#define WDT_vect_num 13
+#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */
+#define TIMER1_CAPT_vect_num 14
+#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */
+#define TIMER1_COMPA_vect_num 15
+#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */
+#define TIMER0_COMPA_vect_num 19
+#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 20
+#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */
+#define TIMER0_OVF_vect_num 21
+#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 22
+#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */
+#define USART1_RX_vect_num 23
+#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */
+#define USART1_UDRE_vect_num 24
+#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */
+#define USART1_TX_vect_num 25
+#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */
+#define ANALOG_COMP_vect_num 26
+#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */
+#define EE_READY_vect_num 27
+#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */
+#define SPM_READY_vect_num 28
+#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */
+#define TIMER1_COMPB_vect_num 16
+#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPC_vect_num 17
+#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */
+#define TIMER1_OVF_vect_num 18
+#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (1024)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x3FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x7FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */
+#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */
+#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x8A
+
+
+/* Device Pin Definitions */
+#endif /* _AVR_ATmega32U2_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom32u4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom32u4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom32u4.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom32u4.h Mon May 10 11:31:22 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iom32u4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOM32U4_H_
@@ -633,9 +633,9 @@
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1C 5
-#define FOC1B 6
-#define FOC1A 7
+#define FOC1C 5
+#define FOC1B 6
+#define FOC1A 7
#define TCNT1 _SFR_MEM16(0x84)
@@ -1448,7 +1448,7 @@
#define XRAMSIZE (0x10000)
#define XRAMEND (XRAMSIZE - 1)
#define E2END (0x3FF)
-#define E2PAGESIZE (4)
+#define E2PAGESIZE (4)
#define FLASHEND (0x7FFF)
@@ -1490,7 +1490,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
diff -u rtems/cpukit/score/cpu/avr/avr/iom32u6.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom32u6.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom32u6.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom32u6.h Mon May 10 11:31:22 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom32u6.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega32U6_H_
diff -u rtems/cpukit/score/cpu/avr/avr/iom406.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom406.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom406.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom406.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom406.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -349,13 +349,13 @@
/* Pin Change Mask Register 1 */
#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT15 7
-#define PCINT14 6
-#define PCINT13 5
-#define PCINT12 4
-#define PCINT11 3
-#define PCINT10 2
-#define PCINT9 1
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9 1
#define PCINT8 0
/* Reserved [0x6D] */
@@ -756,7 +756,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom48p.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom48p.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom48p.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom48p.h Mon May 10 11:31:22 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iom48p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOM48P_H_
@@ -792,7 +792,7 @@
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
@@ -856,7 +856,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom64.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom64.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom64.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom64.h Mon May 10 11:31:22 2010
@@ -30,7 +30,7 @@
/* $Id$ */
-/* avr/iom64.h - defines for ATmega64
+/* avr/iom64.h - defines for ATmega64
As of 2002-11-23:
- This should be up to date with data sheet Rev. 2490C-AVR-09/02 */
@@ -48,7 +48,7 @@
# define _AVR_IOXXX_H_ "iom64.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -74,7 +74,7 @@
/* ADC Control and Status Register A */
#define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */
-#define ADCSRA _SFR_IO8(0x06)
+#define ADCSRA _SFR_IO8(0x06)
/* ADC Multiplexer select */
#define ADMUX _SFR_IO8(0x07)
@@ -208,7 +208,7 @@
/* MCU Status Register */
#define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */
-#define MCUCSR _SFR_IO8(0x34)
+#define MCUCSR _SFR_IO8(0x34)
/* MCU general Control Register */
#define MCUCR _SFR_IO8(0x35)
@@ -253,7 +253,7 @@
#define PORTG _SFR_MEM8(0x65)
/* Store Program Memory Control and Status Register */
-#define SPMCR _SFR_MEM8(0x68)
+#define SPMCR _SFR_MEM8(0x68)
#define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/
/* External Interrupt Control Register A */
@@ -783,9 +783,9 @@
#define WDP1 1
#define WDP0 0
-/*
- The ADHSM bit has been removed from all documentation,
- as being not needed at all since the comparator has proven
+/*
+ The ADHSM bit has been removed from all documentation,
+ as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
@@ -990,7 +990,7 @@
#define PINA5 5
#define PINA4 4
#define PINA3 3
-#define PINA2 2
+#define PINA2 2
#define PINA1 1
#define PINA0 0
@@ -1020,7 +1020,7 @@
#define PINB5 5
#define PINB4 4
#define PINB3 3
-#define PINB2 2
+#define PINB2 2
#define PINB1 1
#define PINB0 0
@@ -1050,7 +1050,7 @@
#define PINC5 5
#define PINC4 4
#define PINC3 3
-#define PINC2 2
+#define PINC2 2
#define PINC1 1
#define PINC0 0
@@ -1080,7 +1080,7 @@
#define PIND5 5
#define PIND4 4
#define PIND3 3
-#define PIND2 2
+#define PIND2 2
#define PIND1 1
#define PIND0 0
@@ -1110,7 +1110,7 @@
#define PINE5 5
#define PINE4 4
#define PINE3 3
-#define PINE2 2
+#define PINE2 2
#define PINE1 1
#define PINE0 0
@@ -1140,7 +1140,7 @@
#define PINF5 5
#define PINF4 4
#define PINF3 3
-#define PINF2 2
+#define PINF2 2
#define PINF1 1
#define PINF0 0
@@ -1161,7 +1161,7 @@
/* Port G Input Pins - PING */
#define PING4 4
#define PING3 3
-#define PING2 2
+#define PING2 2
#define PING1 1
#define PING0 0
@@ -1215,7 +1215,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom640.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom640.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom640.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom640.h Mon May 10 11:31:22 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005 Anatoly Sokolov
+/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom644.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom644.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom644.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom644.h Mon May 10 11:31:22 2010
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom644p.h:1.1
--- /dev/null Mon May 10 12:10:56 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom644p.h Mon May 10 11:31:22 2010
@@ -0,0 +1,94 @@
+/* Copyright (c) 2005 Anatoly Sokolov
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* avr/iom644p.h - definitions for ATmega644P */
+
+/* $Id$ */
+
+#ifndef _AVR_IOM644P_H_
+#define _AVR_IOM644P_H_ 1
+
+#include <avr/iomxx4.h>
+
+/* Constants */
+#define SPM_PAGESIZE 256
+#define RAMEND 0x10FF
+#define XRAMEND RAMEND
+#define E2END 0x7FF
+#define E2PAGESIZE 8
+#define FLASHEND 0xFFFF
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0)
+#define FUSE_CKSEL1 (unsigned char)~_BV(1)
+#define FUSE_CKSEL2 (unsigned char)~_BV(2)
+#define FUSE_CKSEL3 (unsigned char)~_BV(3)
+#define FUSE_SUT0 (unsigned char)~_BV(4)
+#define FUSE_SUT1 (unsigned char)~_BV(5)
+#define FUSE_CKOUT (unsigned char)~_BV(6)
+#define FUSE_CKDIV8 (unsigned char)~_BV(7)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
+#define FUSE_EESAVE (unsigned char)~_BV(3)
+#define FUSE_WDTON (unsigned char)~_BV(4)
+#define FUSE_SPIEN (unsigned char)~_BV(5)
+#define FUSE_JTAGEN (unsigned char)~_BV(6)
+#define FUSE_OCDEN (unsigned char)~_BV(7)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x0A
+
+
+#endif /* _AVR_IOM644P_H_ */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom644pa.h:1.1
--- /dev/null Mon May 10 12:10:56 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom644pa.h Mon May 10 11:31:22 2010
@@ -0,0 +1,1370 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom644PA.h - definitions for ATmega644PA */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom644PA.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega644PA_H_
+#define _AVR_ATmega644PA_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIFR2 _SFR_IO8(0x17)
+#define TOV2 0
+#define OCF2A 1
+#define OCF2B 2
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+#define PCIF2 2
+#define PCIF3 3
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+#define EEAR11 3
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define OCDR _SFR_IO8(0x31)
+#define OCDR0 0
+#define OCDR1 1
+#define OCDR2 2
+#define OCDR3 3
+#define OCDR4 4
+#define OCDR5 5
+#define OCDR6 6
+#define OCDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define JTRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+#define JTD 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSART0 1
+#define PRSPI 2
+#define PRTIM1 3
+#define PRUSART1 4
+#define PRTIM0 5
+#define PRTIM2 6
+#define PRTWI 7
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+#define PCIE2 2
+#define PCIE3 3
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define TIMSK2 _SFR_MEM8(0x70)
+#define TOIE2 0
+#define OCIE2A 1
+#define OCIE2B 2
+
+#define PCMSK3 _SFR_MEM8(0x73)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+#define PCINT28 4
+#define PCINT29 5
+#define PCINT30 6
+#define PCINT31 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_MEM16(0x78)
+#endif
+#define ADCW _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define TCCR2A _SFR_MEM8(0xB0)
+#define WGM20 0
+#define WGM21 1
+#define COM2B0 4
+#define COM2B1 5
+#define COM2A0 6
+#define COM2A1 7
+
+#define TCCR2B _SFR_MEM8(0xB1)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM22 3
+#define FOC2B 6
+#define FOC2A 7
+
+#define TCNT2 _SFR_MEM8(0xB2)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define OCR2A _SFR_MEM8(0xB3)
+#define OCR2A_0 0
+#define OCR2A_1 1
+#define OCR2A_2 2
+#define OCR2A_3 3
+#define OCR2A_4 4
+#define OCR2A_5 5
+#define OCR2A_6 6
+#define OCR2A_7 7
+
+#define OCR2B _SFR_MEM8(0xB4)
+#define OCR2B_0 0
+#define OCR2B_1 1
+#define OCR2B_2 2
+#define OCR2B_3 3
+#define OCR2B_4 4
+#define OCR2B_5 5
+#define OCR2B_6 6
+#define OCR2B_7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB 4
+#define AS2 5
+#define EXCLK 6
+
+#define TWBR _SFR_MEM8(0xB8)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_MEM8(0xB9)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_MEM8(0xBA)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_MEM8(0xBB)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#define TWCR _SFR_MEM8(0xBC)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define TWAMR _SFR_MEM8(0xBD)
+#define TWAM0 1
+#define TWAM1 2
+#define TWAM2 3
+#define TWAM3 4
+#define TWAM4 5
+#define TWAM5 6
+#define TWAM6 7
+
+#define UCSR0A _SFR_MEM8(0xC0)
+#define MPCM0 0
+#define U2X0 1
+#define UPE0 2
+#define DOR0 3
+#define FE0 4
+#define UDRE0 5
+#define TXC0 6
+#define RXC0 7
+
+#define UCSR0B _SFR_MEM8(0xC1)
+#define TXB80 0
+#define RXB80 1
+#define UCSZ02 2
+#define TXEN0 3
+#define RXEN0 4
+#define UDRIE0 5
+#define TXCIE0 6
+#define RXCIE0 7
+
+#define UCSR0C _SFR_MEM8(0xC2)
+#define UCPOL0 0
+#define UCSZ00 1
+#define UCSZ01 2
+#define USBS0 3
+#define UPM00 4
+#define UPM01 5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UBRR0 _SFR_MEM16(0xC4)
+
+#define UBRR0L _SFR_MEM8(0xC4)
+#define _UBRR0 0
+#define _UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UBRR0H _SFR_MEM8(0xC5)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UDR0 _SFR_MEM8(0xC6)
+#define UDR0_0 0
+#define UDR0_1 1
+#define UDR0_2 2
+#define UDR0_3 3
+#define UDR0_4 4
+#define UDR0_5 5
+#define UDR0_6 6
+#define UDR0_7 7
+
+#define UCSR1A _SFR_MEM8(0xC8)
+#define MPCM1 0
+#define U2X1 1
+#define UPE1 2
+#define DOR1 3
+#define FE1 4
+#define UDRE1 5
+#define TXC1 6
+#define RXC1 7
+
+#define UCSR1B _SFR_MEM8(0xC9)
+#define TXB81 0
+#define RXB81 1
+#define UCSZ12 2
+#define TXEN1 3
+#define RXEN1 4
+#define UDRIE1 5
+#define TXCIE1 6
+#define RXCIE1 7
+
+#define UCSR1C _SFR_MEM8(0xCA)
+#define UCPOL1 0
+#define UCSZ10 1
+#define UCSZ11 2
+#define USBS1 3
+#define UPM10 4
+#define UPM11 5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UBRR1 _SFR_MEM16(0xCC)
+
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR_0 0
+#define UBRR_1 1
+#define UBRR_2 2
+#define UBRR_3 3
+#define UBRR_4 4
+#define UBRR_5 5
+#define UBRR_6 6
+#define UBRR_7 7
+
+#define UBRR1H _SFR_MEM8(0xCD)
+#define UBRR_8 0
+#define UBRR_9 1
+#define UBRR_10 2
+#define UBRR_11 3
+
+#define UDR1 _SFR_MEM8(0xCE)
+#define UDR1_0 0
+#define UDR1_1 1
+#define UDR1_2 2
+#define UDR1_3 3
+#define UDR1_4 4
+#define UDR1_5 5
+#define UDR1_6 6
+#define UDR1_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define INT2_vect_num 3
+#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
+#define PCINT0_vect_num 4
+#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 5
+#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
+#define PCINT2_vect_num 6
+#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */
+#define PCINT3_vect_num 7
+#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */
+#define WDT_vect_num 8
+#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */
+#define TIMER2_COMPA_vect_num 9
+#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect_num 10
+#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */
+#define TIMER2_OVF_vect_num 11
+#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect_num 12
+#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 13
+#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect_num 14
+#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */
+#define TIMER1_OVF_vect_num 15
+#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */
+#define TIMER0_COMPA_vect_num 16
+#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 17
+#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */
+#define TIMER0_OVF_vect_num 18
+#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 19
+#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */
+#define USART0_RX_vect_num 20
+#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */
+#define USART0_UDRE_vect_num 21
+#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */
+#define USART0_TX_vect_num 22
+#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */
+#define ANALOG_COMP_vect_num 23
+#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
+#define ADC_vect_num 24
+#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */
+#define EE_READY_vect_num 25
+#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */
+#define TWI_vect_num 26
+#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */
+#define SPM_READY_vect_num 27
+#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */
+#define USART1_RX_vect_num 28
+#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */
+#define USART1_UDRE_vect_num 29
+#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */
+#define USART1_TX_vect_num 30
+#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (256)
+#define RAMSTART (0x100)
+#define RAMSIZE (4096)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (0x0)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x7FF)
+#define E2PAGESIZE (8)
+#define FLASHEND (0xFFFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
+#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
+#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x0A
+
+
+/* Device Pin Definitions */
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 5
+
+#define PCINT13_DDR DDRB
+#define PCINT13_PORT PORTB
+#define PCINT13_PIN PINB
+#define PCINT13_BIT 5
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 6
+
+#define PCINT14_DDR DDRB
+#define PCINT14_PORT PORTB
+#define PCINT14_PIN PINB
+#define PCINT14_BIT 6
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 7
+
+#define PCINT15_DDR DDRB
+#define PCINT15_PORT PORTB
+#define PCINT15_PIN PINB
+#define PCINT15_BIT 7
+
+#define RXD_DDR DDRD
+#define RXD_PORT PORTD
+#define RXD_PIN PIND
+#define RXD_BIT 0
+
+#define PCINT24_DDR DDRD
+#define PCINT24_PORT PORTD
+#define PCINT24_PIN PIND
+#define PCINT24_BIT 0
+
+#define TXD_DDR DDRD
+#define TXD_PORT PORTD
+#define TXD_PIN PIND
+#define TXD_BIT 1
+
+#define PCINT25_DDR DDRD
+#define PCINT25_PORT PORTD
+#define PCINT25_PIN PIND
+#define PCINT25_BIT 1
+
+#define INT0_DDR DDRD
+#define INT0_PORT PORTD
+#define INT0_PIN PIND
+#define INT0_BIT 2
+
+#define RDX1_DDR DDRD
+#define RDX1_PORT PORTD
+#define RDX1_PIN PIND
+#define RDX1_BIT 2
+
+#define PCINT26_DDR DDRD
+#define PCINT26_PORT PORTD
+#define PCINT26_PIN PIND
+#define PCINT26_BIT 2
+
+#define INT1_DDR DDRD
+#define INT1_PORT PORTD
+#define INT1_PIN PIND
+#define INT1_BIT 3
+
+#define TXD1_DDR DDRD
+#define TXD1_PORT PORTD
+#define TXD1_PIN PIND
+#define TXD1_BIT 3
+
+#define PCINT27_DDR DDRD
+#define PCINT27_PORT PORTD
+#define PCINT27_PIN PIND
+#define PCINT27_BIT 3
+
+#define OC1B_DDR DDRD
+#define OC1B_PORT PORTD
+#define OC1B_PIN PIND
+#define OC1B_BIT 4
+
+#define XCK1_DDR DDRD
+#define XCK1_PORT PORTD
+#define XCK1_PIN PIND
+#define XCK1_BIT 4
+
+#define PCINT28_DDR DDRD
+#define PCINT28_PORT PORTD
+#define PCINT28_PIN PIND
+#define PCINT28_BIT 4
+
+#define OC1A_DDR DDRD
+#define OC1A_PORT PORTD
+#define OC1A_PIN PIND
+#define OC1A_BIT 5
+
+#define PCINT29_DDR DDRD
+#define PCINT29_PORT PORTD
+#define PCINT29_PIN PIND
+#define PCINT29_BIT 5
+
+#define ICP_DDR DDRD
+#define ICP_PORT PORTD
+#define ICP_PIN PIND
+#define ICP_BIT 6
+
+#define OC2B_DDR DDRD
+#define OC2B_PORT PORTD
+#define OC2B_PIN PIND
+#define OC2B_BIT 6
+
+#define PCINT30_DDR DDRD
+#define PCINT30_PORT PORTD
+#define PCINT30_PIN PIND
+#define PCINT30_BIT 6
+
+#define OC2A_DDR DDRD
+#define OC2A_PORT PORTD
+#define OC2A_PIN PIND
+#define OC2A_BIT 7
+
+#define PCINT31_DDR DDRD
+#define PCINT31_PORT PORTD
+#define PCINT31_PIN PIND
+#define PCINT31_BIT 7
+
+#define SCL_DDR DDRC
+#define SCL_PORT PORTC
+#define SCL_PIN PINC
+#define SCL_BIT 0
+
+#define PCINT16_DDR DDRC
+#define PCINT16_PORT PORTC
+#define PCINT16_PIN PINC
+#define PCINT16_BIT 0
+
+#define SDA_DDR DDRC
+#define SDA_PORT PORTC
+#define SDA_PIN PINC
+#define SDA_BIT 1
+
+#define PCINT17_DDR DDRC
+#define PCINT17_PORT PORTC
+#define PCINT17_PIN PINC
+#define PCINT17_BIT 1
+
+#define PCINT18_DDR DDRC
+#define PCINT18_PORT PORTC
+#define PCINT18_PIN PINC
+#define PCINT18_BIT 2
+
+#define PCINT19_DDR DDRC
+#define PCINT19_PORT PORTC
+#define PCINT19_PIN PINC
+#define PCINT19_BIT 3
+
+#define PCINT20_DDR DDRC
+#define PCINT20_PORT PORTC
+#define PCINT20_PIN PINC
+#define PCINT20_BIT 4
+
+#define PCINT21_DDR DDRC
+#define PCINT21_PORT PORTC
+#define PCINT21_PIN PINC
+#define PCINT21_BIT 5
+
+#define PCINT22_DDR DDRC
+#define PCINT22_PORT PORTC
+#define PCINT22_PIN PINC
+#define PCINT22_BIT 6
+
+#define PCINT23_DDR DDRC
+#define PCINT23_PORT PORTC
+#define PCINT23_PIN PINC
+#define PCINT23_BIT 7
+
+#define ADC7_DDR DDRA
+#define ADC7_PORT PORTA
+#define ADC7_PIN PINA
+#define ADC7_BIT 7
+
+#define PCINT7_DDR DDRA
+#define PCINT7_PORT PORTA
+#define PCINT7_PIN PINA
+#define PCINT7_BIT 7
+
+#define ADC6_DDR DDRA
+#define ADC6_PORT PORTA
+#define ADC6_PIN PINA
+#define ADC6_BIT 6
+
+#define PCINT6_DDR DDRA
+#define PCINT6_PORT PORTA
+#define PCINT6_PIN PINA
+#define PCINT6_BIT 6
+
+#define ADC5_DDR DDRA
+#define ADC5_PORT PORTA
+#define ADC5_PIN PINA
+#define ADC5_BIT 5
+
+#define PCINT5_DDR DDRA
+#define PCINT5_PORT PORTA
+#define PCINT5_PIN PINA
+#define PCINT5_BIT 5
+
+#define ADC4_DDR DDRA
+#define ADC4_PORT PORTA
+#define ADC4_PIN PINA
+#define ADC4_BIT 4
+
+#define PCINT4_DDR DDRA
+#define PCINT4_PORT PORTA
+#define PCINT4_PIN PINA
+#define PCINT4_BIT 4
+
+#define ADC3_DDR DDRA
+#define ADC3_PORT PORTA
+#define ADC3_PIN PINA
+#define ADC3_BIT 3
+
+#define PCINT3_DDR DDRA
+#define PCINT3_PORT PORTA
+#define PCINT3_PIN PINA
+#define PCINT3_BIT 3
+
+#define ADC2_DDR DDRA
+#define ADC2_PORT PORTA
+#define ADC2_PIN PINA
+#define ADC2_BIT 2
+
+#define PCINT2_DDR DDRA
+#define PCINT2_PORT PORTA
+#define PCINT2_PIN PINA
+#define PCINT2_BIT 2
+
+#define ADC1_DDR DDRA
+#define ADC1_PORT PORTA
+#define ADC1_PIN PINA
+#define ADC1_BIT 1
+
+#define PCINT1_DDR DDRA
+#define PCINT1_PORT PORTA
+#define PCINT1_PIN PINA
+#define PCINT1_BIT 1
+
+#define ADC0_DDR DDRA
+#define ADC0_PORT PORTA
+#define ADC0_PIN PINA
+#define ADC0_BIT 0
+
+#define PCINT0_DDR DDRA
+#define PCINT0_PORT PORTA
+#define PCINT0_PIN PINA
+#define PCINT0_BIT 0
+
+#define XCK_DDR DDRB
+#define XCK_PORT PORTB
+#define XCK_PIN PINB
+#define XCK_BIT 0
+
+#define T0_DDR DDRB
+#define T0_PORT PORTB
+#define T0_PIN PINB
+#define T0_BIT 0
+
+#define PCINT8_DDR DDRB
+#define PCINT8_PORT PORTB
+#define PCINT8_PIN PINB
+#define PCINT8_BIT 0
+
+#define T1_DDR DDRB
+#define T1_PORT PORTB
+#define T1_PIN PINB
+#define T1_BIT 1
+
+#define CLKO_DDR DDRB
+#define CLKO_PORT PORTB
+#define CLKO_PIN PINB
+#define CLKO_BIT 1
+
+#define PCINT9_DDR DDRB
+#define PCINT9_PORT PORTB
+#define PCINT9_PIN PINB
+#define PCINT9_BIT 1
+
+#define AIN0_DDR DDRB
+#define AIN0_PORT PORTB
+#define AIN0_PIN PINB
+#define AIN0_BIT 2
+
+#define INT2_DDR DDRB
+#define INT2_PORT PORTB
+#define INT2_PIN PINB
+#define INT2_BIT 2
+
+#define PCINT10_DDR DDRB
+#define PCINT10_PORT PORTB
+#define PCINT10_PIN PINB
+#define PCINT10_BIT 2
+
+#define AIN1_DDR DDRB
+#define AIN1_PORT PORTB
+#define AIN1_PIN PINB
+#define AIN1_BIT 3
+
+#define OC0A_DDR DDRB
+#define OC0A_PORT PORTB
+#define OC0A_PIN PINB
+#define OC0A_BIT 3
+
+#define PCINT11_DDR DDRB
+#define PCINT11_PORT PORTB
+#define PCINT11_PIN PINB
+#define PCINT11_BIT 3
+
+#define SS_DDR DDRB
+#define SS_PORT PORTB
+#define SS_PIN PINB
+#define SS_BIT 4
+
+#define OC0B_DDR DDRB
+#define OC0B_PORT PORTB
+#define OC0B_PIN PINB
+#define OC0B_BIT 4
+
+#define PCINT12_DDR DDRB
+#define PCINT12_PORT PORTB
+#define PCINT12_PIN PINB
+#define PCINT12_BIT 4
+
+#endif /* _AVR_ATmega644PA_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom645.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom645.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom645.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom645.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom645.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -804,7 +804,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom6450.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom6450.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom6450.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom6450.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom6450.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -895,7 +895,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom649.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom649.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom649.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom649.h Mon May 10 11:31:22 2010
@@ -1,5 +1,5 @@
/* Copyright (c) 2004 Eric B. Weddington
- Copyright (c) 2005,2006 Anatoly Sokolov
+ Copyright (c) 2005,2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,7 @@
# define _AVR_IOXXX_H_ "iom649.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -980,7 +980,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom6490.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom6490.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom6490.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom6490.h Mon May 10 11:31:22 2010
@@ -1,5 +1,5 @@
/* Copyright (c) 2004 Eric B. Weddington
- Copyright (c) 2005,2006 Anatoly Sokolov
+ Copyright (c) 2005,2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,7 @@
# define _AVR_IOXXX_H_ "iom6490.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -1132,7 +1132,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom649p.h:1.1
--- /dev/null Mon May 10 12:10:56 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom649p.h Mon May 10 11:31:22 2010
@@ -0,0 +1,1477 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom649p.h - definitions for ATmega649 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom649p.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega649_H_
+#define _AVR_ATmega649_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define PINE _SFR_IO8(0x0C)
+#define PINE0 0
+#define PINE1 1
+#define PINE2 2
+#define PINE3 3
+#define PINE4 4
+#define PINE5 5
+#define PINE6 6
+#define PINE7 7
+
+#define DDRE _SFR_IO8(0x0D)
+#define DDE0 0
+#define DDE1 1
+#define DDE2 2
+#define DDE3 3
+#define DDE4 4
+#define DDE5 5
+#define DDE6 6
+#define DDE7 7
+
+#define PORTE _SFR_IO8(0x0E)
+#define PORTE0 0
+#define PORTE1 1
+#define PORTE2 2
+#define PORTE3 3
+#define PORTE4 4
+#define PORTE5 5
+#define PORTE6 6
+#define PORTE7 7
+
+#define PINF _SFR_IO8(0x0F)
+#define PINF0 0
+#define PINF1 1
+#define PINF2 2
+#define PINF3 3
+#define PINF4 4
+#define PINF5 5
+#define PINF6 6
+#define PINF7 7
+
+#define DDRF _SFR_IO8(0x10)
+#define DDF0 0
+#define DDF1 1
+#define DDF2 2
+#define DDF3 3
+#define DDF4 4
+#define DDF5 5
+#define DDF6 6
+#define DDF7 7
+
+#define PORTF _SFR_IO8(0x11)
+#define PORTF0 0
+#define PORTF1 1
+#define PORTF2 2
+#define PORTF3 3
+#define PORTF4 4
+#define PORTF5 5
+#define PORTF6 6
+#define PORTF7 7
+
+#define PING _SFR_IO8(0x12)
+#define PING0 0
+#define PING1 1
+#define PING2 2
+#define PING3 3
+#define PING4 4
+#define PING5 5
+
+#define DDRG _SFR_IO8(0x13)
+#define DDG0 0
+#define DDG1 1
+#define DDG2 2
+#define DDG3 3
+#define DDG4 4
+
+#define PORTG _SFR_IO8(0x14)
+#define PORTG0 0
+#define PORTG1 1
+#define PORTG2 2
+#define PORTG3 3
+#define PORTG4 4
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIFR2 _SFR_IO8(0x17)
+#define TOV2 0
+#define OCF2A 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define PCIF0 4
+#define PCIF1 5
+#define PCIF2 6
+#define PCIF3 7
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define PCIE0 4
+#define PCIE1 5
+#define PCIE2 6
+#define PCIE3 7
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEWE 1
+#define EEMWE 2
+#define EERIE 3
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEARL0 0
+#define EEARL1 1
+#define EEARL2 2
+#define EEARL3 3
+#define EEARL4 4
+#define EEARL5 5
+#define EEARL6 6
+#define EEARL7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSR310 0
+#define PSR2 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM01 3
+#define COM0A0 4
+#define COM0A1 5
+#define WGM00 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define OCDR _SFR_IO8(0x31)
+#define OCDR0 0
+#define OCDR1 1
+#define OCDR2 2
+#define OCDR3 3
+#define OCDR4 4
+#define OCDR5 5
+#define OCDR6 6
+#define OCDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define JTRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define JTD 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSART0 1
+#define PRSPI 2
+#define PRTIM1 3
+#define PRLCD 4
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define TIMSK2 _SFR_MEM8(0x70)
+#define TOIE2 0
+#define OCIE2A 1
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_MEM16(0x78)
+#endif
+#define ADCW _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define TCCR2A _SFR_MEM8(0xB0)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM21 3
+#define COM2A0 4
+#define COM2A1 5
+#define WGM20 6
+#define FOC2A 7
+
+#define TCNT2 _SFR_MEM8(0xB2)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define OCR2A _SFR_MEM8(0xB3)
+#define OCR2A0 0
+#define OCR2A1 1
+#define OCR2A2 2
+#define OCR2A3 3
+#define OCR2A4 4
+#define OCR2A5 5
+#define OCR2A6 6
+#define OCR2A7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR2UB 0
+#define OCR2UB 1
+#define TCN2UB 2
+#define AS2 3
+#define EXCLK 4
+
+#define USICR _SFR_MEM8(0xB8)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_MEM8(0xBA)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define UCSR0A _SFR_MEM8(0xC0)
+#define MPCM0 0
+#define U2X0 1
+#define UPE0 2
+#define DOR0 3
+#define FE0 4
+#define UDRE0 5
+#define TXC0 6
+#define RXC0 7
+
+#define UCSR0B _SFR_MEM8(0xC1)
+#define TXB80 0
+#define RXB80 1
+#define UCSZ02 2
+#define TXEN0 3
+#define RXEN0 4
+#define UDRIE0 5
+#define TXCIE0 6
+#define RXCIE0 7
+
+#define UCSR0C _SFR_MEM8(0xC2)
+#define UCPOL0 0
+#define UCSZ00 1
+#define UCSZ01 2
+#define USBS0 3
+#define UPM00 4
+#define UPM01 5
+#define UMSEL0 6
+
+#define UBRR0 _SFR_MEM16(0xC4)
+
+#define UBRR0L _SFR_MEM8(0xC4)
+#define UBRR0_0 0
+#define UBRR0_1 1
+#define UBRR0_2 2
+#define UBRR0_3 3
+#define UBRR0_4 4
+#define UBRR0_5 5
+#define UBRR0_6 6
+#define UBRR0_7 7
+
+#define UBRR0H _SFR_MEM8(0xC5)
+#define UBRR0_8 0
+#define UBRR0_9 1
+#define UBRR0_10 2
+#define UBRR0_11 3
+
+#define UDR0 _SFR_MEM8(0xC6)
+#define UDR00 0
+#define UDR01 1
+#define UDR02 2
+#define UDR03 3
+#define UDR04 4
+#define UDR05 5
+#define UDR06 6
+#define UDR07 7
+
+#define LCDCRA _SFR_MEM8(0xE4)
+#define LCDBL 0
+#define LCDIE 3
+#define LCDIF 4
+#define LCDAB 6
+#define LCDEN 7
+
+#define LCDCRB _SFR_MEM8(0xE5)
+#define LCDPM0 0
+#define LCDPM1 1
+#define LCDPM2 2
+#define LCDPM3 3
+#define LCDMUX0 4
+#define LCDMUX1 5
+#define LCD2B 6
+#define LCDCS 7
+
+#define LCDFRR _SFR_MEM8(0xE6)
+#define LCDCD0 0
+#define LCDCD1 1
+#define LCDCD2 2
+#define LCDPS0 4
+#define LCDPS1 5
+#define LCDPS2 6
+
+#define LCDCCR _SFR_MEM8(0xE7)
+#define LCDCC0 0
+#define LCDCC1 1
+#define LCDCC2 2
+#define LCDCC3 3
+#define LCDDC0 5
+#define LCDDC1 6
+#define LCDDC2 7
+
+#define LCDDR0 _SFR_MEM8(0xEC)
+#define SEG000 0
+#define SEG001 1
+#define SEG002 2
+#define SEG003 3
+#define SEG004 4
+#define SEG005 5
+#define SEG006 6
+#define SEG007 7
+
+#define LCDDR1 _SFR_MEM8(0xED)
+#define SEG008 0
+#define SEG009 1
+#define SEG010 2
+#define SEG011 3
+#define SEG012 4
+#define SEG013 5
+#define SEG014 6
+#define SEG015 7
+
+#define LCDDR2 _SFR_MEM8(0xEE)
+#define SEG016 0
+#define SEG017 1
+#define SEG018 2
+#define SEG019 3
+#define SEG020 4
+#define SEG021 5
+#define SEG022 6
+#define SEG023 7
+
+#define LCDDR3 _SFR_MEM8(0xEF)
+#define SEG024 0
+
+#define LCDDR4 _SFR_MEM8(0xF0)
+
+#define LCDDR5 _SFR_MEM8(0xF1)
+#define SEG100 0
+#define SEG101 1
+#define SEG102 2
+#define SEG103 3
+#define SEG104 4
+#define SEG105 5
+#define SEG106 6
+#define SEG107 7
+
+#define LCDDR6 _SFR_MEM8(0xF2)
+#define SEG108 0
+#define SEG109 1
+#define SEG110 2
+#define SEG111 3
+#define SEG112 4
+#define SEG113 5
+#define SEG114 6
+#define SEG115 7
+
+#define LCDDR7 _SFR_MEM8(0xF3)
+#define SEG116 0
+#define SEG117 1
+#define SEG118 2
+#define SEG119 3
+#define SEG120 4
+#define SEG121 5
+#define SEG122 6
+#define SEG123 7
+
+#define LCDDR8 _SFR_MEM8(0xF4)
+#define SEG124 0
+
+#define LCDDR9 _SFR_MEM8(0xF5)
+
+#define LCDDR10 _SFR_MEM8(0xF6)
+#define SEG200 0
+#define SEG201 1
+#define SEG202 2
+#define SEG203 3
+#define SEG204 4
+#define SEG205 5
+#define SEG206 6
+#define SEG207 7
+
+#define LCDDR11 _SFR_MEM8(0xF7)
+#define SEG208 0
+#define SEG209 1
+#define SEG210 2
+#define SEG211 3
+#define SEG212 4
+#define SEG213 5
+#define SEG214 6
+#define SEG215 7
+
+#define LCDDR12 _SFR_MEM8(0xF8)
+#define SEG216 0
+#define SEG217 1
+#define SEG218 2
+#define SEG219 3
+#define SEG220 4
+#define SEG221 5
+#define SEG222 6
+#define SEG223 7
+
+#define LCDDR13 _SFR_MEM8(0xF9)
+#define SEG224 0
+
+#define LCDDR14 _SFR_MEM8(0xFA)
+
+#define LCDDR15 _SFR_MEM8(0xFB)
+#define SEG300 0
+#define SEG301 1
+#define SEG302 2
+#define SEG303 3
+#define SEG304 4
+#define SEG305 5
+#define SEG306 6
+#define SEG307 7
+
+#define LCDDR16 _SFR_MEM8(0xFC)
+#define SEG308 0
+#define SEG309 1
+#define SEG310 2
+#define SEG311 3
+#define SEG312 4
+#define SEG313 5
+#define SEG314 6
+#define SEG315 7
+
+#define LCDDR17 _SFR_MEM8(0xFD)
+#define SEG316 0
+#define SEG317 1
+#define SEG318 2
+#define SEG319 3
+#define SEG320 4
+#define SEG321 5
+#define SEG322 6
+#define SEG323 7
+
+#define LCDDR18 _SFR_MEM8(0xFE)
+#define SEG324 0
+
+#define LCDDR19 _SFR_MEM8(0xFF)
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define PCINT0_vect_num 2
+#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 3
+#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */
+#define TIMER2_COMP_vect_num 4
+#define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */
+#define TIMER2_OVF_vect_num 5
+#define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect_num 6
+#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 7
+#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect_num 8
+#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */
+#define TIMER1_OVF_vect_num 9
+#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */
+#define TIMER0_COMP_vect_num 10
+#define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */
+#define TIMER0_OVF_vect_num 11
+#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 12
+#define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */
+#define USART0_RX_vect_num 13
+#define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */
+#define USART0_UDRE_vect_num 14
+#define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */
+#define USART0_TX_vect_num 15
+#define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */
+#define USI_START_vect_num 16
+#define USI_START_vect _VECTOR(16) /* USI Start Condition */
+#define USI_OVERFLOW_vect_num 17
+#define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */
+#define ANALOG_COMP_vect_num 18
+#define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */
+#define ADC_vect_num 19
+#define ADC_vect _VECTOR(19) /* ADC Conversion Complete */
+#define EE_READY_vect_num 20
+#define EE_READY_vect _VECTOR(20) /* EEPROM Ready */
+#define SPM_READY_vect_num 21
+#define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */
+#define LCD_vect_num 22
+#define LCD_vect _VECTOR(22) /* LCD Start of Frame */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (23 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (256)
+#define RAMSTART (0x100)
+#define RAMSIZE (4096)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x7FF)
+#define E2PAGESIZE (8)
+#define FLASHEND (0xFFFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */
+#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */
+#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_RESERVED (unsigned char)~_BV(0) /* Reserved fuse bit, do not program */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x0B
+
+
+/* Device Pin Definitions */
+#define RXD_DDR DDRE
+#define RXD_PORT PORTE
+#define RXD_PIN PINE
+#define RXD_BIT 0
+
+#define PCINT0_DDR DDRE
+#define PCINT0_PORT PORTE
+#define PCINT0_PIN PINE
+#define PCINT0_BIT 0
+
+#define TXD_DDR DDRE
+#define TXD_PORT PORTE
+#define TXD_PIN PINE
+#define TXD_BIT 1
+
+#define PCINT1_DDR DDRE
+#define PCINT1_PORT PORTE
+#define PCINT1_PIN PINE
+#define PCINT1_BIT 1
+
+#define XCK_DDR DDRE
+#define XCK_PORT PORTE
+#define XCK_PIN PINE
+#define XCK_BIT 2
+
+#define AIN0_DDR DDRE
+#define AIN0_PORT PORTE
+#define AIN0_PIN PINE
+#define AIN0_BIT 2
+
+#define PCINT2_DDR DDRE
+#define PCINT2_PORT PORTE
+#define PCINT2_PIN PINE
+#define PCINT2_BIT 2
+
+#define AIN1_DDR DDRE
+#define AIN1_PORT PORTE
+#define AIN1_PIN PINE
+#define AIN1_BIT 3
+
+#define PCINT3_DDR DDRE
+#define PCINT3_PORT PORTE
+#define PCINT3_PIN PINE
+#define PCINT3_BIT 3
+
+#define USCK_DDR DDRE
+#define USCK_PORT PORTE
+#define USCK_PIN PINE
+#define USCK_BIT 4
+
+#define SCL_DDR DDRE
+#define SCL_PORT PORTE
+#define SCL_PIN PINE
+#define SCL_BIT 4
+
+#define PCINT4_DDR DDRE
+#define PCINT4_PORT PORTE
+#define PCINT4_PIN PINE
+#define PCINT4_BIT 4
+
+#define DI_DDR DDRE
+#define DI_PORT PORTE
+#define DI_PIN PINE
+#define DI_BIT 5
+
+#define SDA_DDR DDRE
+#define SDA_PORT PORTE
+#define SDA_PIN PINE
+#define SDA_BIT 5
+
+#define PCINT5_DDR DDRE
+#define PCINT5_PORT PORTE
+#define PCINT5_PIN PINE
+#define PCINT5_BIT 5
+
+#define DO_DDR DDRE
+#define DO_PORT PORTE
+#define DO_PIN PINE
+#define DO_BIT 6
+
+#define PCINT6_DDR DDRE
+#define PCINT6_PORT PORTE
+#define PCINT6_PIN PINE
+#define PCINT6_BIT 6
+
+#define PCINT7_DDR DDRE
+#define PCINT7_PORT PORTE
+#define PCINT7_PIN PINE
+#define PCINT7_BIT 7
+
+#define SS_DDR DDRB
+#define SS_PORT PORTB
+#define SS_PIN PINB
+#define SS_BIT 0
+
+#define PCINT8_DDR DDRB
+#define PCINT8_PORT PORTB
+#define PCINT8_PIN PINB
+#define PCINT8_BIT 0
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 1
+
+#define PCINT9_DDR DDRB
+#define PCINT9_PORT PORTB
+#define PCINT9_PIN PINB
+#define PCINT9_BIT 1
+
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 2
+
+#define PCINT10_DDR DDRB
+#define PCINT10_PORT PORTB
+#define PCINT10_PIN PINB
+#define PCINT10_BIT 2
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 3
+
+#define PCINT11_DDR DDRB
+#define PCINT11_PORT PORTB
+#define PCINT11_PIN PINB
+#define PCINT11_BIT 3
+
+#define OC0_DDR DDRB
+#define OC0_PORT PORTB
+#define OC0_PIN PINB
+#define OC0_BIT 4
+
+#define PCINT12_DDR DDRB
+#define PCINT12_PORT PORTB
+#define PCINT12_PIN PINB
+#define PCINT12_BIT 4
+
+#define OC1A_DDR DDRB
+#define OC1A_PORT PORTB
+#define OC1A_PIN PINB
+#define OC1A_BIT 5
+
+#define PCINT13_DDR DDRB
+#define PCINT13_PORT PORTB
+#define PCINT13_PIN PINB
+#define PCINT13_BIT 5
+
+#define OC1B_DDR DDRB
+#define OC1B_PORT PORTB
+#define OC1B_PIN PINB
+#define OC1B_BIT 6
+
+#define PCINT14_DDR DDRB
+#define PCINT14_PORT PORTB
+#define PCINT14_PIN PINB
+#define PCINT14_BIT 6
+
+#define OC2_DDR DDRB
+#define OC2_PORT PORTB
+#define OC2_PIN PINB
+#define OC2_BIT 7
+
+#define PCINT15_DDR DDRB
+#define PCINT15_PORT PORTB
+#define PCINT15_PIN PINB
+#define PCINT15_BIT 7
+
+#define T1_DDR DDRG
+#define T1_PORT PORTG
+#define T1_PIN PING
+#define T1_BIT 3
+
+#define SEG24_DDR DDRG
+#define SEG24_PORT PORTG
+#define SEG24_PIN PING
+#define SEG24_BIT 3
+
+#define T0_DDR DDRG
+#define T0_PORT PORTG
+#define T0_PIN PING
+#define T0_BIT 4
+
+#define SEG23_DDR DDRG
+#define SEG23_PORT PORTG
+#define SEG23_PIN PING
+#define SEG23_BIT 4
+
+#define ICP/SEG22_DDR DDRD
+#define ICP/SEG22_PORT PORTD
+#define ICP/SEG22_PIN PIND
+#define ICP/SEG22_BIT 0
+
+#define INT0/SEG21_DDR DDRD
+#define INT0/SEG21_PORT PORTD
+#define INT0/SEG21_PIN PIND
+#define INT0/SEG21_BIT 1
+
+#define SEG20_DDR DDRD
+#define SEG20_PORT PORTD
+#define SEG20_PIN PIND
+#define SEG20_BIT 2
+
+#define SEG19_DDR DDRD
+#define SEG19_PORT PORTD
+#define SEG19_PIN PIND
+#define SEG19_BIT 3
+
+#define SEG18_DDR DDRD
+#define SEG18_PORT PORTD
+#define SEG18_PIN PIND
+#define SEG18_BIT 4
+
+#define SEG17_DDR DDRD
+#define SEG17_PORT PORTD
+#define SEG17_PIN PIND
+#define SEG17_BIT 5
+
+#define SEG16_DDR DDRD
+#define SEG16_PORT PORTD
+#define SEG16_PIN PIND
+#define SEG16_BIT 6
+
+#define SEG15_DDR DDRD
+#define SEG15_PORT PORTD
+#define SEG15_PIN PIND
+#define SEG15_BIT 7
+
+#define SEG14_DDR DDRG
+#define SEG14_PORT PORTG
+#define SEG14_PIN PING
+#define SEG14_BIT 0
+
+#define SEG13_DDR DDRG
+#define SEG13_PORT PORTG
+#define SEG13_PIN PING
+#define SEG13_BIT 1
+
+#define SEG12_DDR DDRC
+#define SEG12_PORT PORTC
+#define SEG12_PIN PINC
+#define SEG12_BIT 0
+
+#define SEG11_DDR DDRC
+#define SEG11_PORT PORTC
+#define SEG11_PIN PINC
+#define SEG11_BIT 1
+
+#define SEG10_DDR DDRC
+#define SEG10_PORT PORTC
+#define SEG10_PIN PINC
+#define SEG10_BIT 2
+
+#define SEG9_DDR DDRC
+#define SEG9_PORT PORTC
+#define SEG9_PIN PINC
+#define SEG9_BIT 3
+
+#define SEG8_DDR DDRC
+#define SEG8_PORT PORTC
+#define SEG8_PIN PINC
+#define SEG8_BIT 4
+
+#define SEG7_DDR DDRC
+#define SEG7_PORT PORTC
+#define SEG7_PIN PINC
+#define SEG7_BIT 5
+
+#define SEG6_DDR DDRC
+#define SEG6_PORT PORTC
+#define SEG6_PIN PINC
+#define SEG6_BIT 6
+
+#define SEG5_DDR DDRC
+#define SEG5_PORT PORTC
+#define SEG5_PIN PINC
+#define SEG5_BIT 7
+
+#define SEG4_DDR DDRG
+#define SEG4_PORT PORTG
+#define SEG4_PIN PING
+#define SEG4_BIT 2
+
+#define SEG3_DDR DDRA
+#define SEG3_PORT PORTA
+#define SEG3_PIN PINA
+#define SEG3_BIT 7
+
+#define SEG2_DDR DDRA
+#define SEG2_PORT PORTA
+#define SEG2_PIN PINA
+#define SEG2_BIT 6
+
+#define SEG1_DDR DDRA
+#define SEG1_PORT PORTA
+#define SEG1_PIN PINA
+#define SEG1_BIT 5
+
+#define SEG0_DDR DDRA
+#define SEG0_PORT PORTA
+#define SEG0_PIN PINA
+#define SEG0_BIT 4
+
+#define COM3_DDR DDRA
+#define COM3_PORT PORTA
+#define COM3_PIN PINA
+#define COM3_BIT 3
+
+#define COM2_DDR DDRA
+#define COM2_PORT PORTA
+#define COM2_PIN PINA
+#define COM2_BIT 2
+
+#define COM1_DDR DDRA
+#define COM1_PORT PORTA
+#define COM1_PIN PINA
+#define COM1_BIT 1
+
+#define COM0_DDR DDRA
+#define COM0_PORT PORTA
+#define COM0_PIN PINA
+#define COM0_BIT 0
+
+#define ADC7_DDR DDRF
+#define ADC7_PORT PORTF
+#define ADC7_PIN PINF
+#define ADC7_BIT 7
+
+#define ADC6_DDR DDRF
+#define ADC6_PORT PORTF
+#define ADC6_PIN PINF
+#define ADC6_BIT 6
+
+#define TD0_DDR DDRF
+#define TD0_PORT PORTF
+#define TD0_PIN PINF
+#define TD0_BIT 6
+
+#define ADC5_DDR DDRF
+#define ADC5_PORT PORTF
+#define ADC5_PIN PINF
+#define ADC5_BIT 5
+
+#define ADC4_DDR DDRF
+#define ADC4_PORT PORTF
+#define ADC4_PIN PINF
+#define ADC4_BIT 4
+
+#define ADC3_DDR DDRF
+#define ADC3_PORT PORTF
+#define ADC3_PIN PINF
+#define ADC3_BIT 3
+
+#define ADC2_DDR DDRF
+#define ADC2_PORT PORTF
+#define ADC2_PIN PINF
+#define ADC2_BIT 2
+
+#define ADC1_DDR DDRF
+#define ADC1_PORT PORTF
+#define ADC1_PIN PINF
+#define ADC1_BIT 1
+
+#define ADC0_DDR DDRF
+#define ADC0_PORT PORTF
+#define ADC0_PIN PINF
+#define ADC0_BIT 0
+
+#endif /* _AVR_ATmega649_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom64c1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom64c1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom64c1.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom64c1.h Mon May 10 11:31:22 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom64c1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega64C1_H_
@@ -683,6 +683,7 @@
#define DACON _SFR_MEM8(0x90)
#define DAEN 0
+#define DAOE 1
#define DALA 2
#define DATS0 4
#define DATS1 5
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom64hve.h:1.1
--- /dev/null Mon May 10 12:10:56 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom64hve.h Mon May 10 11:31:22 2010
@@ -0,0 +1,1020 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom64hve.h - definitions for ATmega64HVE */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom64hve.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega64HVE_H_
+#define _AVR_ATmega64HVE_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+#define ICF0 3
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 3
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define ICS0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+
+#define TCNT0 _SFR_IO16(0x26)
+
+#define TCNT0L _SFR_IO8(0x26)
+#define TCNT0L0 0
+#define TCNT0L1 1
+#define TCNT0L2 2
+#define TCNT0L3 3
+#define TCNT0L4 4
+#define TCNT0L5 5
+#define TCNT0L6 6
+#define TCNT0L7 7
+
+#define TCNT0H _SFR_IO8(0x27)
+#define TCNT0H0 0
+#define TCNT0H1 1
+#define TCNT0H2 2
+#define TCNT0H3 3
+#define TCNT0H4 4
+#define TCNT0H5 5
+#define TCNT0H6 6
+#define TCNT0H7 7
+
+#define OCR0A _SFR_IO8(0x28)
+#define OCR0A0 0
+#define OCR0A1 1
+#define OCR0A2 2
+#define OCR0A3 3
+#define OCR0A4 4
+#define OCR0A5 5
+#define OCR0A6 6
+#define OCR0A7 7
+
+#define OCR0B _SFR_IO8(0x29)
+#define OCR0B0 0
+#define OCR0B1 1
+#define OCR0B2 2
+#define OCR0B3 3
+#define OCR0B4 4
+#define OCR0B5 5
+#define OCR0B6 6
+#define OCR0B7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define TCCR0C _SFR_IO8(0x2F)
+
+#define OCDR _SFR_IO8(0x31)
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BODRF 2
+#define WDRF 3
+#define OCDRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define CKOE 5
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define LBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPCE 7
+
+#define WUTCSR _SFR_MEM8(0x62)
+#define WUTP0 0
+#define WUTP1 1
+#define WUTP2 2
+#define WUTE 3
+#define WUTR 4
+#define WUTIE 6
+#define WUTIF 7
+
+#define WDTCLR _SFR_MEM8(0x63)
+#define WDCLE 0
+#define WDCL0 1
+#define WDCL1 2
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRTIM0 0
+#define PRTIM1 1
+#define PRSPI 2
+#define PRLIN 3
+
+#define SOSCCALA _SFR_MEM8(0x66)
+#define SCALA0 0
+#define SCALA1 1
+#define SCALA2 2
+#define SCALA3 3
+#define SCALA4 4
+#define SCALA5 5
+#define SCALA6 6
+#define SCALA7 7
+
+#define SOSCCALB _SFR_MEM8(0x67)
+#define SCALB0 0
+#define SCALB1 1
+#define SCALB2 2
+#define SCALB3 3
+#define SCALB4 4
+#define SCALB5 5
+#define SCALB6 6
+#define SCALB7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT2 0
+#define PCINT3 1
+#define PCINT4 2
+#define PCINT5 3
+#define PCINT6 4
+#define PCINT7 5
+#define PCINT8 6
+#define PCINT9 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+#define ICIE0 3
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 3
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define PA0DID 0
+#define PA1DID 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define ICS1 3
+#define ICES1 4
+#define ICNC1 5
+#define ICEN1 6
+#define TCW1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+
+#define TCCR1C _SFR_MEM8(0x82)
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define OCR1A _SFR_MEM8(0x88)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define OCR1B _SFR_MEM8(0x89)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define LINCR _SFR_MEM8(0xC0)
+#define LCMD0 0
+#define LCMD1 1
+#define LCMD2 2
+#define LENA 3
+#define LCONF0 4
+#define LCONF1 5
+#define LIN13 6
+#define LSWRES 7
+
+#define LINSIR _SFR_MEM8(0xC1)
+#define LRXOK 0
+#define LTXOK 1
+#define LIDOK 2
+#define LERR 3
+#define LBUSY 4
+#define LIDST0 5
+#define LIDST1 6
+#define LIDST2 7
+
+#define LINENIR _SFR_MEM8(0xC2)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR 3
+
+#define LINERR _SFR_MEM8(0xC3)
+#define LBERR 0
+#define LCERR 1
+#define LPERR 2
+#define LSERR 3
+#define LFERR 4
+#define LOVERR 5
+#define LTOERR 6
+#define LABORT 7
+
+#define LINBTR _SFR_MEM8(0xC4)
+#define LBT0 0
+#define LBT1 1
+#define LBT2 2
+#define LBT3 3
+#define LBT4 4
+#define LBT5 5
+#define LDISR 7
+
+#define LINBRR _SFR_MEM16(0xC5)
+
+#define LINBRRL _SFR_MEM8(0xC5)
+#define LDIV0 0
+#define LDIV1 1
+#define LDIV2 2
+#define LDIV3 3
+#define LDIV4 4
+#define LDIV5 5
+#define LDIV6 6
+#define LDIV7 7
+
+#define LINBRRH _SFR_MEM8(0xC6)
+#define LDIV8 0
+#define LDIV9 1
+#define LDIV10 2
+#define LDIV11 3
+
+#define LINDLR _SFR_MEM8(0xC7)
+#define LRXDL0 0
+#define LRXDL1 1
+#define LRXDL2 2
+#define LRXDL3 3
+#define LTXDL0 4
+#define LTXDL1 5
+#define LTXDL2 6
+#define LTXDL3 7
+
+#define LINIDR _SFR_MEM8(0xC8)
+#define LID0 0
+#define LID1 1
+#define LID2 2
+#define LID3 3
+#define LID4 4
+#define LID5 5
+#define LP0 6
+#define LP1 7
+
+#define LINSEL _SFR_MEM8(0xC9)
+#define LINDX0 0
+#define LINDX1 1
+#define LINDX2 2
+#define LAINC 3
+
+#define LINDAT _SFR_MEM8(0xCA)
+#define LDATA0 0
+#define LDATA1 1
+#define LDATA2 2
+#define LDATA3 3
+#define LDATA4 4
+#define LDATA5 5
+#define LDATA6 6
+#define LDATA7 7
+
+#define BGCSRA _SFR_MEM8(0xD1)
+#define BGSC0 0
+#define BGSC1 1
+#define BGSC2 2
+
+#define BGCRB _SFR_MEM8(0xD2)
+#define BGCL0 0
+#define BGCL1 1
+#define BGCL2 2
+#define BGCL3 3
+#define BGCL4 4
+#define BGCL5 5
+#define BGCL6 6
+#define BGCL7 7
+
+#define BGCRA _SFR_MEM8(0xD3)
+#define BGCN0 0
+#define BGCN1 1
+#define BGCN2 2
+#define BGCN3 3
+#define BGCN4 4
+#define BGCN5 5
+#define BGCN6 6
+#define BGCN7 7
+
+#define BGLR _SFR_MEM8(0xD4)
+#define BGPL 0
+#define BGPLE 1
+
+#define PLLCSR _SFR_MEM8(0xD8)
+#define PLLCIE 0
+#define PLLCIF 1
+#define LOCK 4
+#define SWEN 5
+
+#define PBOV _SFR_MEM8(0xDC)
+#define PBOE0 0
+#define PBOE3 3
+#define PBOVCE 7
+
+#define ADSCSRA _SFR_MEM8(0xE0)
+#define SCMD0 0
+#define SCMD1 1
+#define SBSY 2
+
+#define ADSCSRB _SFR_MEM8(0xE1)
+#define CADICRB 0
+#define CADACRB 1
+#define CADICPS 2
+#define VADICRB 4
+#define VADACRB 5
+#define VADICPS 6
+
+#define ADCRA _SFR_MEM8(0xE2)
+#define CKSEL 0
+#define ADCMS0 1
+#define ADCMS1 2
+#define ADPSEL 3
+
+#define ADCRB _SFR_MEM8(0xE3)
+#define ADADES0 0
+#define ADADES1 1
+#define ADADES2 2
+#define ADIDES0 3
+#define ADIDES1 4
+
+#define ADCRC _SFR_MEM8(0xE4)
+#define CADRCT0 0
+#define CADRCT1 1
+#define CADRCT2 2
+#define CADRCT3 3
+#define CADRCM0 4
+#define CADRCM1 5
+#define CADEN 7
+
+#define ADCRD _SFR_MEM8(0xE5)
+#define CADDSEL 0
+#define CADPDM0 1
+#define CADPDM1 2
+#define CADG0 3
+#define CADG1 4
+#define CADG2 5
+
+#define ADCRE _SFR_MEM8(0xE6)
+#define VADMUX0 0
+#define VADMUX1 1
+#define VADMUX2 2
+#define VADPDM0 3
+#define VADPDM1 4
+#define VADREFS 5
+#define VADEN 7
+
+#define ADIFR _SFR_MEM8(0xE7)
+#define CADICIF 0
+#define CADACIF 1
+#define CADRCIF 2
+#define VADICIF 4
+#define VADACIF 5
+
+#define ADIMR _SFR_MEM8(0xE8)
+#define CADICIE 0
+#define CADACIE 1
+#define CADRCIE 2
+#define VADICIE 4
+#define VADACIE 5
+
+#define CADRCL _SFR_MEM16(0xE9)
+
+#define CADRCLL _SFR_MEM8(0xE9)
+#define CADRCL0 0
+#define CADRCL1 1
+#define CADRCL2 2
+#define CADRCL3 3
+#define CADRCL4 4
+#define CADRCL5 5
+#define CADRCL6 6
+#define CADRCL7 7
+
+#define CADRCLH _SFR_MEM8(0xEA)
+#define CADRCL8 0
+#define CADRCL9 1
+#define CADRCL10 2
+#define CADRCL11 3
+#define CADRCL12 4
+#define CADRCL13 5
+#define CADRCL14 6
+#define CADRCL15 7
+
+#define CADIC _SFR_MEM16(0xEB)
+
+#define CADICL _SFR_MEM8(0xEB)
+#define CADIC0 0
+#define CADIC1 1
+#define CADIC2 2
+#define CADIC3 3
+#define CADIC4 4
+#define CADIC5 5
+#define CADIC6 6
+#define CADIC7 7
+
+#define CADICH _SFR_MEM8(0xEC)
+#define CADIC8 0
+#define CADIC9 1
+#define CADIC10 2
+#define CADIC11 3
+#define CADIC12 4
+#define CADIC13 5
+#define CADIC14 6
+#define CADIC15 7
+
+#define CADAC0 _SFR_MEM8(0xED)
+#define CADAC00 0
+#define CADAC01 1
+#define CADAC02 2
+#define CADAC03 3
+#define CADAC04 4
+#define CADAC05 5
+#define CADAC06 6
+#define CADAC07 7
+
+#define CADAC1 _SFR_MEM8(0xEE)
+#define CADAC08 0
+#define CADAC09 1
+#define CADAC10 2
+#define CADAC11 3
+#define CADAC12 4
+#define CADAC13 5
+#define CADAC14 6
+#define CADAC15 7
+
+#define CADAC2 _SFR_MEM8(0xEF)
+#define CADAC16 0
+#define CADAC17 1
+#define CADAC18 2
+#define CADAC19 3
+#define CADAC20 4
+#define CADAC21 5
+#define CADAC22 6
+#define CADAC23 7
+
+#define CADAC3 _SFR_MEM8(0xF0)
+#define CADAC24 0
+#define CADAC25 1
+#define CADAC26 2
+#define CADAC27 3
+#define CADAC28 4
+#define CADAC29 5
+#define CADAC30 6
+#define CADAC31 7
+
+#define VADIC _SFR_MEM16(0xF1)
+
+#define VADICL _SFR_MEM8(0xF1)
+#define VADIC0 0
+#define VADIC1 1
+#define VADIC2 2
+#define VADIC3 3
+#define VADIC4 4
+#define VADIC5 5
+#define VADIC6 6
+#define VADIC7 7
+
+#define VADICH _SFR_MEM8(0xF2)
+#define VADIC8 0
+#define VADIC9 1
+#define VADIC10 2
+#define VADIC11 3
+#define VADIC12 4
+#define VADIC13 5
+#define VADIC14 6
+#define VADIC15 7
+
+#define VADAC0 _SFR_MEM8(0xF3)
+#define VADAC00 0
+#define VADAC01 1
+#define VADAC02 2
+#define VADAC03 3
+#define VADAC04 4
+#define VADAC05 5
+#define VADAC06 6
+#define VADAC07 7
+
+#define VADAC1 _SFR_MEM8(0xF4)
+#define VADAC08 0
+#define VADAC09 1
+#define VADAC10 2
+#define VADAC11 3
+#define VADAC12 4
+#define VADAC13 5
+#define VADAC14 6
+#define VADAC15 7
+
+#define VADAC2 _SFR_MEM8(0xF5)
+#define VADAC16 0
+#define VADAC17 1
+#define VADAC18 2
+#define VADAC19 3
+#define VADAC20 4
+#define VADAC21 5
+#define VADAC22 6
+#define VADAC23 7
+
+#define VADAC3 _SFR_MEM8(0xF6)
+#define VADAC24 0
+#define VADAC25 1
+#define VADAC26 2
+#define VADAC27 3
+#define VADAC28 4
+#define VADAC29 5
+#define VADAC30 6
+#define VADAC31 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
+#define PCINT0_vect_num 2
+#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt 0 */
+#define PCINT1_vect_num 3
+#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt 1 */
+#define WDT_vect_num 4
+#define WDT_vect _VECTOR(4) /* Watchdog Timeout Interrupt */
+#define WAKEUP_vect_num 5
+#define WAKEUP_vect _VECTOR(5) /* Wakeup Timer Overflow */
+#define TIMER1_IC_vect_num 6
+#define TIMER1_IC_vect _VECTOR(6) /* Timer 1 Input capture */
+#define TIMER1_COMPA_vect_num 7
+#define TIMER1_COMPA_vect _VECTOR(7) /* Timer 1 Compare Match A */
+#define TIMER1_COMPB_vect_num 8
+#define TIMER1_COMPB_vect _VECTOR(8) /* Timer 1 Compare Match B */
+#define TIMER1_OVF_vect_num 9
+#define TIMER1_OVF_vect _VECTOR(9) /* Timer 1 overflow */
+#define TIMER0_IC_vect_num 10
+#define TIMER0_IC_vect _VECTOR(10) /* Timer 0 Input Capture */
+#define TIMER0_COMPA_vect_num 11
+#define TIMER0_COMPA_vect _VECTOR(11) /* Timer 0 Comapre Match A */
+#define TIMER0_COMPB_vect_num 12
+#define TIMER0_COMPB_vect _VECTOR(12) /* Timer 0 Compare Match B */
+#define TIMER0_OVF_vect_num 13
+#define TIMER0_OVF_vect _VECTOR(13) /* Timer 0 Overflow */
+#define LIN_STATUS_vect_num 14
+#define LIN_STATUS_vect _VECTOR(14) /* LIN Status Interrupt */
+#define LIN_ERROR_vect_num 15
+#define LIN_ERROR_vect _VECTOR(15) /* LIN Error Interrupt */
+#define SPI_STC_vect_num 16
+#define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */
+#define VADC_CONV_vect_num 17
+#define VADC_CONV_vect _VECTOR(17) /* Voltage ADC Instantaneous Conversion Complete */
+#define VADC_ACC_vect_num 18
+#define VADC_ACC_vect _VECTOR(18) /* Voltage ADC Accumulated Conversion Complete */
+#define CADC_CONV_vect_num 19
+#define CADC_CONV_vect _VECTOR(19) /* C-ADC Instantaneous Conversion Complete */
+#define CADC_REG_CUR_vect_num 20
+#define CADC_REG_CUR_vect _VECTOR(20) /* C-ADC Regular Current */
+#define CADC_ACC_vect_num 21
+#define CADC_ACC_vect _VECTOR(21) /* C-ADC Accumulated Conversion Complete */
+#define EE_READY_vect_num 22
+#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
+#define SPM_vect_num 23
+#define SPM_vect _VECTOR(23) /* SPM Ready */
+#define PLL_vect_num 24
+#define PLL_vect _VECTOR(24) /* PLL Lock Change Interrupt */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (25 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (4096)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (NA)
+#define XRAMEND (RAMEND)
+#define E2END (0x3FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0xFFFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */
+#define FUSE_SUT0 (unsigned char)~_BV(1) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(2) /* Select start-up time */
+#define FUSE_CKDIV8 (unsigned char)~_BV(3) /* Divide clock by 8 */
+#define FUSE_BODEN (unsigned char)~_BV(4) /* Enable BOD */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */
+#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_OSCSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */
+#define HFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x10
+
+
+/* Device Pin Definitions */
+#define PV2_DDR DDRV
+#define PV2_PORT PORTV
+#define PV2_PIN PINV
+#define PV2_BIT 2
+
+#define PV1_DDR DDRV
+#define PV1_PORT PORTV
+#define PV1_PIN PINV
+#define PV1_BIT 1
+
+#define NV_DDR DDRNV
+#define NV_PORT PORTNV
+#define NV_PIN PINNV
+#define NV_BIT NV
+
+#define VFET_DDR DDRVFET
+#define VFET_PORT PORTVFET
+#define VFET_PIN PINVFET
+#define VFET_BIT VFET
+
+#define CF1P_DDR DDRCF1P
+#define CF1P_PORT PORTCF1P
+#define CF1P_PIN PINCF1P
+#define CF1P_BIT CF1P
+
+#define CF1N_DDR DDRCF1N
+#define CF1N_PORT PORTCF1N
+#define CF1N_PIN PINCF1N
+#define CF1N_BIT CF1N
+
+#define CF2P_DDR DDRCF2P
+#define CF2P_PORT PORTCF2P
+#define CF2P_PIN PINCF2P
+#define CF2P_BIT CF2P
+
+#define CF2N_DDR DDRCF2N
+#define CF2N_PORT PORTCF2N
+#define CF2N_PIN PINCF2N
+#define CF2N_BIT CF2N
+
+#define VREG_DDR DDRVREG
+#define VREG_PORT PORTVREG
+#define VREG_PIN PINVREG
+#define VREG_BIT VREG
+
+#define VREF_DDR DDRVREF
+#define VREF_PORT PORTVREF
+#define VREF_PIN PINVREF
+#define VREF_BIT VREF
+
+#define VREFGND_DDR DDRVREFGND
+#define VREFGND_PORT PORTVREFGND
+#define VREFGND_PIN PINVREFGND
+#define VREFGND_BIT VREFGND
+
+#define PI_DDR DDRI
+#define PI_PORT PORTI
+#define PI_PIN PINI
+#define PI_BIT
+
+#define NI_DDR DDRNI
+#define NI_PORT PORTNI
+#define NI_PIN PINNI
+#define NI_BIT NI
+
+#define PA0_DDR DDRA
+#define PA0_PORT PORTA
+#define PA0_PIN PINA
+#define PA0_BIT 0
+
+#define PA1_DDR DDRA
+#define PA1_PORT PORTA
+#define PA1_PIN PINA
+#define PA1_BIT 1
+
+#define PA2_DDR DDRA
+#define PA2_PORT PORTA
+#define PA2_PIN PINA
+#define PA2_BIT 2
+
+#define PB0_DDR DDRB
+#define PB0_PORT PORTB
+#define PB0_PIN PINB
+#define PB0_BIT 0
+
+#define PB1_DDR DDRB
+#define PB1_PORT PORTB
+#define PB1_PIN PINB
+#define PB1_BIT 1
+
+#define PB2_DDR DDRB
+#define PB2_PORT PORTB
+#define PB2_PIN PINB
+#define PB2_BIT 2
+
+#define PB3_DDR DDRB
+#define PB3_PORT PORTB
+#define PB3_PIN PINB
+#define PB3_BIT 3
+
+#define PC0_DDR DDRC
+#define PC0_PORT PORTC
+#define PC0_PIN PINC
+#define PC0_BIT 0
+
+#define BATT_DDR DDRBATT
+#define BATT_PORT PORTBATT
+#define BATT_PIN PINBATT
+#define BATT_BIT BATT
+
+#define OC_DDR DDROC
+#define OC_PORT PORTOC
+#define OC_PIN PINOC
+#define OC_BIT OC
+
+#endif /* _AVR_ATmega64HVE_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom64m1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom64m1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom64m1.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom64m1.h Mon May 10 11:31:22 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iom64m1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATmega64M1_H_
@@ -683,6 +683,7 @@
#define DACON _SFR_MEM8(0x90)
#define DAEN 0
+#define DAOE 1
#define DALA 2
#define DATS0 4
#define DATS1 5
diff -u rtems/cpukit/score/cpu/avr/avr/iom8.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom8.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom8.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom8.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom8.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -328,9 +328,9 @@
#define EXTRF 1
#define PORF 0
-/*
- The ADHSM bit has been removed from all documentation,
- as being not needed at all since the comparator has proven
+/*
+ The ADHSM bit has been removed from all documentation,
+ as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
@@ -602,7 +602,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom8515.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom8515.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom8515.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom8515.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom8515.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -624,7 +624,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom8535.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom8535.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom8535.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom8535.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iom8535.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -394,9 +394,9 @@
#define CS01 1
#define CS00 0
-/*
- The ADHSM bit has been removed from all documentation,
- as being not needed at all since the comparator has proven
+/*
+ The ADHSM bit has been removed from all documentation,
+ as being not needed at all since the comparator has proven
to be fast enough even without feeding it more power.
*/
@@ -703,7 +703,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom88.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom88.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom88.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom88.h Mon May 10 11:31:22 2010
@@ -79,7 +79,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iom88p.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom88p.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom88p.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom88p.h Mon May 10 11:31:22 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iom88p.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOM88P_H_
@@ -331,7 +331,7 @@
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
+#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
@@ -796,7 +796,7 @@
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
@@ -862,7 +862,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom88pa.h:1.1
--- /dev/null Mon May 10 12:10:57 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom88pa.h Mon May 10 11:31:22 2010
@@ -0,0 +1,1167 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom88pa.h - definitions for ATmega88PA */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom88pa.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega88PA_H_
+#define _AVR_ATmega88PA_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIFR2 _SFR_IO8(0x17)
+#define TOV2 0
+#define OCF2A 1
+#define OCF2B 2
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+#define PCIF2 2
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define RWWSB 6
+#define SPMIE 7
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSART0 1
+#define PRSPI 2
+#define PRTIM1 3
+#define PRTIM0 5
+#define PRTIM2 6
+#define PRTWI 7
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+#define PCIE2 2
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define TIMSK2 _SFR_MEM8(0x70)
+#define TOIE2 0
+#define OCIE2A 1
+#define OCIE2B 2
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_MEM16(0x78)
+#endif
+#define ADCW _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define TCCR2A _SFR_MEM8(0xB0)
+#define WGM20 0
+#define WGM21 1
+#define COM2B0 4
+#define COM2B1 5
+#define COM2A0 6
+#define COM2A1 7
+
+#define TCCR2B _SFR_MEM8(0xB1)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM22 3
+#define FOC2B 6
+#define FOC2A 7
+
+#define TCNT2 _SFR_MEM8(0xB2)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define OCR2A _SFR_MEM8(0xB3)
+#define OCR2A_0 0
+#define OCR2A_1 1
+#define OCR2A_2 2
+#define OCR2A_3 3
+#define OCR2A_4 4
+#define OCR2A_5 5
+#define OCR2A_6 6
+#define OCR2A_7 7
+
+#define OCR2B _SFR_MEM8(0xB4)
+#define OCR2B_0 0
+#define OCR2B_1 1
+#define OCR2B_2 2
+#define OCR2B_3 3
+#define OCR2B_4 4
+#define OCR2B_5 5
+#define OCR2B_6 6
+#define OCR2B_7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB 4
+#define AS2 5
+#define EXCLK 6
+
+#define TWBR _SFR_MEM8(0xB8)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_MEM8(0xB9)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_MEM8(0xBA)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_MEM8(0xBB)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#define TWCR _SFR_MEM8(0xBC)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define TWAMR _SFR_MEM8(0xBD)
+#define TWAM0 1
+#define TWAM1 2
+#define TWAM2 3
+#define TWAM3 4
+#define TWAM4 5
+#define TWAM5 6
+#define TWAM6 7
+
+#define UCSR0A _SFR_MEM8(0xC0)
+#define MPCM0 0
+#define U2X0 1
+#define UPE0 2
+#define DOR0 3
+#define FE0 4
+#define UDRE0 5
+#define TXC0 6
+#define RXC0 7
+
+#define UCSR0B _SFR_MEM8(0xC1)
+#define TXB80 0
+#define RXB80 1
+#define UCSZ02 2
+#define TXEN0 3
+#define RXEN0 4
+#define UDRIE0 5
+#define TXCIE0 6
+#define RXCIE0 7
+
+#define UCSR0C _SFR_MEM8(0xC2)
+#define UCPOL0 0
+#define UCSZ00 1
+#define UCSZ01 2
+#define USBS0 3
+#define UPM00 4
+#define UPM01 5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UBRR0 _SFR_MEM16(0xC4)
+
+#define UBRR0L _SFR_MEM8(0xC4)
+#define _UBRR0 0
+#define _UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UBRR0H _SFR_MEM8(0xC5)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UDR0 _SFR_MEM8(0xC6)
+#define UDR0_0 0
+#define UDR0_1 1
+#define UDR0_2 2
+#define UDR0_3 3
+#define UDR0_4 4
+#define UDR0_5 5
+#define UDR0_6 6
+#define UDR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define PCINT0_vect_num 3
+#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 4
+#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
+#define PCINT2_vect_num 5
+#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
+#define WDT_vect_num 6
+#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
+#define TIMER2_COMPA_vect_num 7
+#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect_num 8
+#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
+#define TIMER2_OVF_vect_num 9
+#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect_num 10
+#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 11
+#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect_num 12
+#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
+#define TIMER1_OVF_vect_num 13
+#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
+#define TIMER0_COMPA_vect_num 14
+#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 15
+#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
+#define TIMER0_OVF_vect_num 16
+#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
+#define SPI_STC_vect_num 17
+#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
+#define USART_RX_vect_num 18
+#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */
+#define USART_UDRE_vect_num 19
+#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
+#define USART_TX_vect_num 20
+#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */
+#define ADC_vect_num 21
+#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
+#define EE_READY_vect_num 22
+#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
+#define ANALOG_COMP_vect_num 23
+#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
+#define TWI_vect_num 24
+#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
+#define SPM_Ready_vect_num 25
+#define SPM_Ready_vect _VECTOR(25) /* Store Program Memory Read */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (26 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART (0x100)
+#define RAMSIZE (1024)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x1FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select reset vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select boot size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select boot size */
+#define EFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0F
+
+
+/* Device Pin Definitions */
+#define PCINT19_DDR DDRD
+#define PCINT19_PORT PORTD
+#define PCINT19_PIN PIND
+#define PCINT19_BIT 3
+
+#define OC2B_DDR DDRD
+#define OC2B_PORT PORTD
+#define OC2B_PIN PIND
+#define OC2B_BIT 3
+
+#define INT1_DDR DDRD
+#define INT1_PORT PORTD
+#define INT1_PIN PIND
+#define INT1_BIT 3
+
+#define XCK_DDR DDRD
+#define XCK_PORT PORTD
+#define XCK_PIN PIND
+#define XCK_BIT 4
+
+#define T0_DDR DDRD
+#define T0_PORT PORTD
+#define T0_PIN PIND
+#define T0_BIT 4
+
+#define PCINT20_DDR DDRD
+#define PCINT20_PORT PORTD
+#define PCINT20_PIN PIND
+#define PCINT20_BIT 4
+
+#define PCINT6_DDR DDRB
+#define PCINT6_PORT PORTB
+#define PCINT6_PIN PINB
+#define PCINT6_BIT 6
+
+#define PCINT7_DDR DDRB
+#define PCINT7_PORT PORTB
+#define PCINT7_PIN PINB
+#define PCINT7_BIT 7
+
+#define T1_DDR DDRD
+#define T1_PORT PORTD
+#define T1_PIN PIND
+#define T1_BIT 5
+
+#define OC0B_DDR DDRD
+#define OC0B_PORT PORTD
+#define OC0B_PIN PIND
+#define OC0B_BIT 5
+
+#define PCINT21_DDR DDRD
+#define PCINT21_PORT PORTD
+#define PCINT21_PIN PIND
+#define PCINT21_BIT 5
+
+#define AIN0_DDR DDRD
+#define AIN0_PORT PORTD
+#define AIN0_PIN PIND
+#define AIN0_BIT 6
+
+#define OC0A_DDR DDRD
+#define OC0A_PORT PORTD
+#define OC0A_PIN PIND
+#define OC0A_BIT 6
+
+#define PCINT22_DDR DDRD
+#define PCINT22_PORT PORTD
+#define PCINT22_PIN PIND
+#define PCINT22_BIT 6
+
+#define AIN1_DDR DDRD
+#define AIN1_PORT PORTD
+#define AIN1_PIN PIND
+#define AIN1_BIT 7
+
+#define PCINT23_DDR DDRD
+#define PCINT23_PORT PORTD
+#define PCINT23_PIN PIND
+#define PCINT23_BIT 7
+
+#define ICP1_DDR DDRB
+#define ICP1_PORT PORTB
+#define ICP1_PIN PINB
+#define ICP1_BIT 0
+
+#define CLKO_DDR DDRB
+#define CLKO_PORT PORTB
+#define CLKO_PIN PINB
+#define CLKO_BIT 0
+
+#define PCINT0_DDR DDRB
+#define PCINT0_PORT PORTB
+#define PCINT0_PIN PINB
+#define PCINT0_BIT 0
+
+#define OC1A_DDR DDRB
+#define OC1A_PORT PORTB
+#define OC1A_PIN PINB
+#define OC1A_BIT 1
+
+#define PCINT1_DDR DDRB
+#define PCINT1_PORT PORTB
+#define PCINT1_PIN PINB
+#define PCINT1_BIT 1
+
+#define SS_DDR DDRB
+#define SS_PORT PORTB
+#define SS_PIN PINB
+#define SS_BIT 2
+
+#define OC1B_DDR DDRB
+#define OC1B_PORT PORTB
+#define OC1B_PIN PINB
+#define OC1B_BIT 2
+
+#define PCINT2_DDR DDRB
+#define PCINT2_PORT PORTB
+#define PCINT2_PIN PINB
+#define PCINT2_BIT 2
+
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 3
+
+#define OC2A_DDR DDRB
+#define OC2A_PORT PORTB
+#define OC2A_PIN PINB
+#define OC2A_BIT 3
+
+#define PCINT3_DDR DDRB
+#define PCINT3_PORT PORTB
+#define PCINT3_PIN PINB
+#define PCINT3_BIT 3
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 4
+
+#define PCINT4_DDR DDRB
+#define PCINT4_PORT PORTB
+#define PCINT4_PIN PINB
+#define PCINT4_BIT 4
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 5
+
+#define PCINT5_DDR DDRB
+#define PCINT5_PORT PORTB
+#define PCINT5_PIN PINB
+#define PCINT5_BIT 5
+
+#define ADC6_DDR DDRADC
+#define ADC6_PORT PORTADC
+#define ADC6_PIN PINADC
+#define ADC6_BIT ADC6
+
+#define ADC7_DDR DDRADC
+#define ADC7_PORT PORTADC
+#define ADC7_PIN PINADC
+#define ADC7_BIT ADC7
+
+#define ADC0_DDR DDRC
+#define ADC0_PORT PORTC
+#define ADC0_PIN PINC
+#define ADC0_BIT 0
+
+#define PCINT8_DDR DDRC
+#define PCINT8_PORT PORTC
+#define PCINT8_PIN PINC
+#define PCINT8_BIT 0
+
+#define ADC1_DDR DDRC
+#define ADC1_PORT PORTC
+#define ADC1_PIN PINC
+#define ADC1_BIT 1
+
+#define PCINT9_DDR DDRC
+#define PCINT9_PORT PORTC
+#define PCINT9_PIN PINC
+#define PCINT9_BIT 1
+
+#define ADC2_DDR DDRC
+#define ADC2_PORT PORTC
+#define ADC2_PIN PINC
+#define ADC2_BIT 2
+
+#define PCINT10_DDR DDRC
+#define PCINT10_PORT PORTC
+#define PCINT10_PIN PINC
+#define PCINT10_BIT 2
+
+#define ADC3_DDR DDRC
+#define ADC3_PORT PORTC
+#define ADC3_PIN PINC
+#define ADC3_BIT 3
+
+#define PCINT11_DDR DDRC
+#define PCINT11_PORT PORTC
+#define PCINT11_PIN PINC
+#define PCINT11_BIT 3
+
+#define ADC4_DDR DDRC
+#define ADC4_PORT PORTC
+#define ADC4_PIN PINC
+#define ADC4_BIT 4
+
+#define SDA_DDR DDRC
+#define SDA_PORT PORTC
+#define SDA_PIN PINC
+#define SDA_BIT 4
+
+#define PCINT12_DDR DDRC
+#define PCINT12_PORT PORTC
+#define PCINT12_PIN PINC
+#define PCINT12_BIT 4
+
+#define ADC5_DDR DDRC
+#define ADC5_PORT PORTC
+#define ADC5_PIN PINC
+#define ADC5_BIT 5
+
+#define SCL_DDR DDRC
+#define SCL_PORT PORTC
+#define SCL_PIN PINC
+#define SCL_BIT 5
+
+#define PCINT13_DDR DDRC
+#define PCINT13_PORT PORTC
+#define PCINT13_PIN PINC
+#define PCINT13_BIT 5
+
+#define PCINT14_DDR DDRC
+#define PCINT14_PORT PORTC
+#define PCINT14_PIN PINC
+#define PCINT14_BIT 6
+
+#define RXD_DDR DDRD
+#define RXD_PORT PORTD
+#define RXD_PIN PIND
+#define RXD_BIT 0
+
+#define PCINT16_DDR DDRD
+#define PCINT16_PORT PORTD
+#define PCINT16_PIN PIND
+#define PCINT16_BIT 0
+
+#define TXD_DDR DDRD
+#define TXD_PORT PORTD
+#define TXD_PIN PIND
+#define TXD_BIT 1
+
+#define PCINT17_DDR DDRD
+#define PCINT17_PORT PORTD
+#define PCINT17_PIN PIND
+#define PCINT17_BIT 1
+
+#define INT0_DDR DDRD
+#define INT0_PORT PORTD
+#define INT0_PIN PIND
+#define INT0_BIT 2
+
+#define PCINT18_DDR DDRD
+#define PCINT18_PORT PORTD
+#define PCINT18_PIN PIND
+#define PCINT18_BIT 2
+
+#endif /* _AVR_ATmega88PA_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iom8hva.h:1.2 rtems/cpukit/score/cpu/avr/avr/iom8hva.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iom8hva.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iom8hva.h Mon May 10 11:31:22 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2007, Anatoly Sokolov
+/* Copyright (c) 2007, Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iom8u2.h:1.1
--- /dev/null Mon May 10 12:10:57 2010
+++ rtems/cpukit/score/cpu/avr/avr/iom8u2.h Mon May 10 11:31:22 2010
@@ -0,0 +1,967 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iom8u2.h - definitions for ATmega8U2 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iom8u2.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATmega8U2_H_
+#define _AVR_ATmega8U2_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define OCF1C 3
+#define ICF1 5
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+#define INTF3 3
+#define INTF4 4
+#define INTF5 5
+#define INTF6 6
+#define INTF7 7
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+#define INT3 3
+#define INT4 4
+#define INT5 5
+#define INT6 6
+#define INT7 7
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+#define EEAR11 3
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PLLP0 2
+#define PLLP1 3
+#define PLLP2 4
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define DWDR _SFR_IO8(0x31)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define USBRF 5
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define EIND _SFR_IO8(0x3C)
+#define EIND0 0
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define WDTCKD _SFR_MEM8(0x62)
+#define WCLKD0 0
+#define WCLKD1 1
+#define WDEWIE 2
+#define WDEWIF 3
+
+#define REGCR _SFR_MEM8(0x63)
+#define REGDIS 0
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRSPI 2
+#define PRTIM1 3
+#define PRTIM0 5
+
+#define PRR1 _SFR_MEM8(0x65)
+#define PRUSART1 0
+#define PRUSB 7
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+#define ISC30 6
+#define ISC31 7
+
+#define EICRB _SFR_MEM8(0x6A)
+#define ISC40 0
+#define ISC41 1
+#define ISC50 2
+#define ISC51 3
+#define ISC60 4
+#define ISC61 5
+#define ISC70 6
+#define ISC71 7
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define OCIE1C 3
+#define ICIE1 5
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1C0 2
+#define COM1C1 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1C 5
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1C _SFR_MEM16(0x8C)
+
+#define OCR1CL _SFR_MEM8(0x8C)
+#define OCR1CL0 0
+#define OCR1CL1 1
+#define OCR1CL2 2
+#define OCR1CL3 3
+#define OCR1CL4 4
+#define OCR1CL5 5
+#define OCR1CL6 6
+#define OCR1CL7 7
+
+#define OCR1CH _SFR_MEM8(0x8D)
+#define OCR1CH0 0
+#define OCR1CH1 1
+#define OCR1CH2 2
+#define OCR1CH3 3
+#define OCR1CH4 4
+#define OCR1CH5 5
+#define OCR1CH6 6
+#define OCR1CH7 7
+
+#define UCSR1A _SFR_MEM8(0xC8)
+#define MPCM1 0
+#define U2X1 1
+#define UPE1 2
+#define DOR1 3
+#define FE1 4
+#define UDRE1 5
+#define TXC1 6
+#define RXC1 7
+
+#define UCSR1B _SFR_MEM8(0xC9)
+#define TXB81 0
+#define RXB81 1
+#define UCSZ12 2
+#define TXEN1 3
+#define RXEN1 4
+#define UDRIE1 5
+#define TXCIE1 6
+#define RXCIE1 7
+
+#define UCSR1C _SFR_MEM8(0xCA)
+#define UCPOL1 0
+#define UCSZ10 1
+#define UCSZ11 2
+#define USBS1 3
+#define UPM10 4
+#define UPM11 5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UCSR1D _SFR_MEM8(0xCB)
+#define RTSEN 0
+#define CTSEN 1
+
+#define UBRR1 _SFR_MEM16(0xCC)
+
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1_0 0
+#define UBRR1_1 1
+#define UBRR1_2 2
+#define UBRR1_3 3
+#define UBRR1_4 4
+#define UBRR1_5 5
+#define UBRR1_6 6
+#define UBRR1_7 7
+
+#define UBRR1H _SFR_MEM8(0xCD)
+#define UBRR1_8 0
+#define UBRR1_9 1
+#define UBRR1_10 2
+#define UBRR1_11 3
+
+#define UDR1 _SFR_MEM8(0xCE)
+#define UDR1_0 0
+#define UDR1_1 1
+#define UDR1_2 2
+#define UDR1_3 3
+#define UDR1_4 4
+#define UDR1_5 5
+#define UDR1_6 6
+#define UDR1_7 7
+
+#define CLKSEL0 _SFR_MEM8(0xD0)
+#define CLKS 0
+#define EXTE 2
+#define RCE 3
+#define EXSUT0 4
+#define EXSUT1 5
+#define RCSUT0 6
+#define RCSUT1 7
+
+#define CLKSEL1 _SFR_MEM8(0xD1)
+#define EXCKSEL0 0
+#define EXCKSEL1 1
+#define EXCKSEL2 2
+#define EXCKSEL3 3
+#define RCCKSEL0 4
+#define RCCKSEL1 5
+#define RCCKSEL2 6
+#define RCCKSEL3 7
+
+#define CLKSTA _SFR_MEM8(0xD2)
+#define EXTON 0
+#define RCON 1
+
+#define USBCON _SFR_MEM8(0xD8)
+#define FRZCLK 5
+#define USBE 7
+
+#define UDCON _SFR_MEM8(0xE0)
+#define DETACH 0
+#define RMWKUP 1
+#define RSTCPU 2
+
+#define UDINT _SFR_MEM8(0xE1)
+#define SUSPI 0
+#define SOFI 2
+#define EORSTI 3
+#define WAKEUPI 4
+#define EORSMI 5
+#define UPRSMI 6
+
+#define UDIEN _SFR_MEM8(0xE2)
+#define SUSPE 0
+#define SOFE 2
+#define EORSTE 3
+#define WAKEUPE 4
+#define EORSME 5
+#define UPRSME 6
+
+#define UDADDR _SFR_MEM8(0xE3)
+#define UADD0 0
+#define UADD1 1
+#define UADD2 2
+#define UADD3 3
+#define UADD4 4
+#define UADD5 5
+#define UADD6 6
+#define ADDEN 7
+
+#define UDFNUM _SFR_MEM16(0xE4)
+
+#define UDFNUML _SFR_MEM8(0xE4)
+#define FNUM0 0
+#define FNUM1 1
+#define FNUM2 2
+#define FNUM3 3
+#define FNUM4 4
+#define FNUM5 5
+#define FNUM6 6
+#define FNUM7 7
+
+#define UDFNUMH _SFR_MEM8(0xE5)
+#define FNUM8 0
+#define FNUM9 1
+#define FNUM10 2
+
+#define UDMFN _SFR_MEM8(0xE6)
+#define FNCERR 4
+
+#define UEINTX _SFR_MEM8(0xE8)
+#define TXINI 0
+#define STALLEDI 1
+#define RXOUTI 2
+#define RXSTPI 3
+#define NAKOUTI 4
+#define RWAL 5
+#define NAKINI 6
+#define FIFOCON 7
+
+#define UENUM _SFR_MEM8(0xE9)
+#define EPNUM0 0
+#define EPNUM1 1
+#define EPNUM2 2
+
+#define UERST _SFR_MEM8(0xEA)
+#define EPRST0 0
+#define EPRST1 1
+#define EPRST2 2
+#define EPRST3 3
+#define EPRST4 4
+
+#define UECONX _SFR_MEM8(0xEB)
+#define EPEN 0
+#define RSTDT 3
+#define STALLRQC 4
+#define STALLRQ 5
+
+#define UECFG0X _SFR_MEM8(0xEC)
+#define EPDIR 0
+#define EPTYPE0 6
+#define EPTYPE1 7
+
+#define UECFG1X _SFR_MEM8(0xED)
+#define ALLOC 1
+#define EPBK0 2
+#define EPBK1 3
+#define EPSIZE0 4
+#define EPSIZE1 5
+#define EPSIZE2 6
+
+#define UESTA0X _SFR_MEM8(0xEE)
+#define NBUSYBK0 0
+#define NBUSYBK1 1
+#define DTSEQ0 2
+#define DTSEQ1 3
+#define UNDERFI 5
+#define OVERFI 6
+#define CFGOK 7
+
+#define UESTA1X _SFR_MEM8(0xEF)
+#define CURRBK0 0
+#define CURRBK1 1
+#define CTRLDIR 2
+
+#define UEIENX _SFR_MEM8(0xF0)
+#define TXINE 0
+#define STALLEDE 1
+#define RXOUTE 2
+#define RXSTPE 3
+#define NAKOUTE 4
+#define NAKINE 6
+#define FLERRE 7
+
+#define UEDATX _SFR_MEM8(0xF1)
+#define DAT0 0
+#define DAT1 1
+#define DAT2 2
+#define DAT3 3
+#define DAT4 4
+#define DAT5 5
+#define DAT6 6
+#define DAT7 7
+
+#define UEBCLX _SFR_MEM8(0xF2)
+#define BYCT0 0
+#define BYCT1 1
+#define BYCT2 2
+#define BYCT3 3
+#define BYCT4 4
+#define BYCT5 5
+#define BYCT6 6
+#define BYCT7 7
+
+#define UEINT _SFR_MEM8(0xF4)
+#define EPINT0 0
+#define EPINT1 1
+#define EPINT2 2
+#define EPINT3 3
+#define EPINT4 4
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define INT2_vect_num 3
+#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */
+#define INT3_vect_num 4
+#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */
+#define INT4_vect_num 5
+#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */
+#define INT5_vect_num 6
+#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */
+#define INT6_vect_num 7
+#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */
+#define INT7_vect_num 8
+#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */
+#define PCINT0_vect_num 9
+#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 10
+#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */
+#define USB_GEN_vect_num 11
+#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */
+#define USB_COM_vect_num 12
+#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */
+#define WDT_vect_num 13
+#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */
+#define TIMER1_CAPT_vect_num 14
+#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */
+#define TIMER1_COMPA_vect_num 15
+#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */
+#define TIMER0_COMPA_vect_num 19
+#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 20
+#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */
+#define TIMER0_OVF_vect_num 21
+#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */
+#define SPI_STC_vect_num 22
+#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */
+#define USART1_RX_vect_num 23
+#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */
+#define USART1_UDRE_vect_num 24
+#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */
+#define USART1_TX_vect_num 25
+#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */
+#define ANALOG_COMP_vect_num 26
+#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */
+#define EE_READY_vect_num 27
+#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */
+#define SPM_READY_vect_num 28
+#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */
+#define TIMER1_COMPB_vect_num 16
+#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPC_vect_num 17
+#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */
+#define TIMER1_OVF_vect_num 18
+#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (128)
+#define RAMSTART (0x100)
+#define RAMSIZE (512)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x1FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */
+#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */
+#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x89
+
+
+/* Device Pin Definitions */
+#endif /* _AVR_ATmega8U2_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iomx8.h:1.2 rtems/cpukit/score/cpu/avr/avr/iomx8.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iomx8.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iomx8.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iomx8.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -203,7 +203,7 @@
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEARH _SFR_IO8(0X22)
-/*
+/*
Even though EEARH is not used by the mega48, the EEAR8 bit in the register
must be written to 0, according to the datasheet, hence the EEARH register
must be defined for the mega48.
@@ -297,7 +297,7 @@
#define MCUCR _SFR_IO8 (0x35)
/* MCUCR */
#define PUD 4
-#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)
+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)
#define IVSEL 1
#define IVCE 0
#endif
diff -u rtems/cpukit/score/cpu/avr/avr/iomxx0_1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iomxx0_1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iomxx0_1.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iomxx0_1.h Mon May 10 11:31:22 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2005 Anatoly Sokolov
+/* Copyright (c) 2005 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -46,7 +46,7 @@
# define _AVR_IOXXX_H_ "iomxx0_1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
# define __ATmegaxx0__
@@ -299,7 +299,7 @@
#define TOV5 0
#define PCIFR _SFR_IO8(0x1B)
-#if defined(__ATmegaxx0__)
+#if defined(__ATmegaxx0__)
# define PCIF2 2
#endif /* __ATmegaxx0__ */
#define PCIF1 1
@@ -322,7 +322,7 @@
#define INT4 4
#define INT3 3
#define INT2 2
-#define INT1 1
+#define INT1 1
#define INT0 0
#define GPIOR0 _SFR_IO8(0x1E)
@@ -556,7 +556,7 @@
#define PCINT9 1
#define PCINT8 0
-#if defined(__ATmegaxx0__)
+#if defined(__ATmegaxx0__)
# define PCMSK2 _SFR_MEM8(0x6D)
# define PCINT23 7
# define PCINT22 6
@@ -1251,7 +1251,7 @@
/* Reserved [0x12E..0x12F] */
-#if defined(__ATmegaxx0__)
+#if defined(__ATmegaxx0__)
# define UCSR3A _SFR_MEM8(0x130)
# define RXC3 7
diff -u rtems/cpukit/score/cpu/avr/avr/iomxxhva.h:1.2 rtems/cpukit/score/cpu/avr/avr/iomxxhva.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iomxxhva.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iomxxhva.h Mon May 10 11:31:22 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2007, Anatoly Sokolov
+/* Copyright (c) 2007, Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iomxxhva.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -115,7 +115,7 @@
#define EIMSK _SFR_IO8(0x1D)
#define INT2 2
-#define INT1 1
+#define INT1 1
#define INT0 0
#define GPIOR0 _SFR_IO8(0x1E)
diff -u rtems/cpukit/score/cpu/avr/avr/iotn11.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn11.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn11.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn11.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotn11.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef __ASSEMBLER__
# warning "MCU not supported by the C compiler"
diff -u rtems/cpukit/score/cpu/avr/avr/iotn12.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn12.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn12.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn12.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotn12.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef __ASSEMBLER__
# warning "MCU not supported by the C compiler"
diff -u rtems/cpukit/score/cpu/avr/avr/iotn13.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn13.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn13.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn13.h Mon May 10 11:31:22 2010
@@ -47,7 +47,7 @@
# define _AVR_IOXXX_H_ "iotn13.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers and bit names */
diff -u rtems/cpukit/score/cpu/avr/avr/iotn13a.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn13a.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn13a.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn13a.h Mon May 10 11:31:22 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iotn13a.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATTINY13A_H_
@@ -187,8 +187,7 @@
#define PRR _SFR_IO8(0x25)
#define PRADC 0
-#define PRSPI 1
-#define PRTIM0 2
+#define PRTIM0 1
#define CLKPR _SFR_IO8(0x26)
#define CLKPS0 0
diff -u rtems/cpukit/score/cpu/avr/avr/iotn15.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn15.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn15.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn15.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotn15.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef __ASSEMBLER__
# warning "MCU not supported by the C compiler"
diff -u rtems/cpukit/score/cpu/avr/avr/iotn167.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn167.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn167.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn167.h Mon May 10 11:31:22 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iotn167.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOTN167_H_
@@ -781,7 +781,7 @@
#define XRAMSIZE (0)
#define XRAMEND RAMEND
#define E2END (0x1FF)
-#define E2PAGESIZE (4)
+#define E2PAGESIZE (4)
#define FLASHEND (0x3FFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iotn22.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn22.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn22.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn22.h Mon May 10 11:31:22 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotn22.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn2313a.h:1.1
--- /dev/null Mon May 10 12:10:58 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn2313a.h Mon May 10 11:31:22 2010
@@ -0,0 +1,769 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn2313a.h - definitions for ATtiny2313A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn2313a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny2313A_H_
+#define _AVR_ATtiny2313A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define DIDR _SFR_IO8(0x001)
+#define AIN0D 0
+#define AIN1D 1
+
+#define UBRRH _SFR_IO8(0x002)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UCSRC _SFR_IO8(0x003)
+#define UCPOL 0
+#define UCSZ0 1
+#define UCSZ1 2
+#define USBS 3
+#define UPM0 4
+#define UPM1 5
+#define UMSEL 6
+
+#define PCMSK1 _SFR_IO8(0x004)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+
+#define PCMSK2 _SFR_IO8(0x005)
+#define PCINT11 0
+#define PCINT12 1
+#define PCINT13 2
+#define PCINT14 3
+#define PCINT15 4
+#define PCINT16 5
+#define PCINT17 6
+
+#define PRR _SFR_IO8(0x006)
+#define PRUSART 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define BODCR _SFR_IO8(0x007)
+#define BPDSE 0
+#define BPDS 1
+
+#define ACSR _SFR_IO8(0x008)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define UBRRL _SFR_IO8(0x009)
+#define UBRR0 0
+#define UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UCSRB _SFR_IO8(0x00A)
+#define TXB8 0
+#define RXB8 1
+#define UCSZ2 2
+#define TXEN 3
+#define RXEN 4
+#define UDRIE 5
+#define TXCIE 6
+#define RXCIE 7
+
+#define UCSRA _SFR_IO8(0x00B)
+#define MPCM 0
+#define U2X 1
+#define UPE 2
+#define DOR 3
+#define FE 4
+#define UDRE 5
+#define TXC 6
+#define RXC 7
+
+#define UDR _SFR_IO8(0x00C)
+#define UDR0 0
+#define UDR1 1
+#define UDR2 2
+#define UDR3 3
+#define UDR4 4
+#define UDR5 5
+#define UDR6 6
+#define UDR7 7
+
+#define USICR _SFR_IO8(0x00D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x00E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x00F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define PIND _SFR_IO8(0x010)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+
+#define DDRD _SFR_IO8(0x011)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+
+#define PORTD _SFR_IO8(0x012)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+
+#define GPIOR0 _SFR_IO8(0x013)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x014)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x015)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define PINB _SFR_IO8(0x016)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x017)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x018)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x019)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+
+#define DDRA _SFR_IO8(0x01A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+
+#define PORTA _SFR_IO8(0x01B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+
+#define EECR _SFR_IO8(0x01C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x01D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO8(0x01E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+
+#define PCMSK _SFR_IO8(0x020)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define WDTCR _SFR_IO8(0x021)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define TCCR1C _SFR_IO8(0x022)
+#define FOC1B 6
+#define FOC1A 7
+
+#define GTCCR _SFR_IO8(0x023)
+#define PSR10 0
+
+#define ICR1 _SFR_IO16(0x024)
+
+#define ICR1L _SFR_IO8(0x024)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_IO8(0x025)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define CLKPR _SFR_IO8(0x026)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define OCR1B _SFR_IO16(0x028)
+
+#define OCR1BL _SFR_IO8(0x028)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_IO8(0x029)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1A _SFR_IO16(0x02A)
+
+#define OCR1AL _SFR_IO8(0x02A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_IO8(0x02B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCNT1 _SFR_IO16(0x02C)
+
+#define TCNT1L _SFR_IO8(0x02C)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_IO8(0x02D)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define TCCR1B _SFR_IO8(0x02E)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1A _SFR_IO8(0x02F)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR0A _SFR_IO8(0x030)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define OSCCAL _SFR_IO8(0x031)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+
+#define TCNT0 _SFR_IO8(0x032)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCCR0B _SFR_IO8(0x033)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define MCUSR _SFR_IO8(0x034)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x035)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define SM0 4
+#define SE 5
+#define SM1 6
+#define PUD 7
+
+#define OCR0A _SFR_IO8(0x036)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define SPMCSR _SFR_IO8(0x037)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR _SFR_IO8(0x038)
+#define OCF0A 0
+#define TOV0 1
+#define OCF0B 2
+#define ICF1 3
+#define OCF1B 5
+#define OCF1A 6
+#define TOV1 7
+
+#define TIMSK _SFR_IO8(0x039)
+#define OCIE0A 0
+#define TOIE0 1
+#define OCIE0B 2
+#define ICIE1 3
+#define OCIE1B 5
+#define OCIE1A 6
+#define TOIE1 7
+
+#define EIFR _SFR_IO8(0x03A)
+#define PCIF 5
+#define INTF0 6
+#define INTF1 7
+
+#define GIMSK _SFR_IO8(0x03B)
+#define PCIE 5
+#define INT0 6
+#define INT1 7
+
+#define OCR0B _SFR_IO8(0x03C)
+#define OCR0_0 0
+#define OCR0_1 1
+#define OCR0_2 2
+#define OCR0_3 3
+#define OCR0_4 4
+#define OCR0_5 5
+#define OCR0_6 6
+#define OCR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define TIMER1_CAPT_vect_num 3
+#define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 4
+#define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */
+#define TIMER1_OVF_vect_num 5
+#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num 6
+#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */
+#define USART_RX_vect_num 7
+#define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */
+#define USART_UDRE_vect_num 8
+#define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */
+#define USART_TX_vect_num 9
+#define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */
+#define ANA_COMP_vect_num 10
+#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */
+#define PCINT_B_vect_num 11
+#define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */
+#define TIMER1_COMPB_vect_num 12
+#define TIMER1_COMPB_vect _VECTOR(12) /* */
+#define TIMER0_COMPA_vect_num 13
+#define TIMER0_COMPA_vect _VECTOR(13) /* */
+#define TIMER0_COMPB_vect_num 14
+#define TIMER0_COMPB_vect _VECTOR(14) /* */
+#define USI_START_vect_num 15
+#define USI_START_vect _VECTOR(15) /* USI Start Condition */
+#define USI_OVERFLOW_vect_num 16
+#define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */
+#define WDT_OVERFLOW_vect_num 18
+#define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */
+#define PCINT_D_vect_num 20
+#define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */
+#define EEPROM_Ready_vect_num 17
+#define EEPROM_Ready_vect _VECTOR(17) /* */
+#define PCINT_A_vect_num 19
+#define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (32)
+#define RAMSTART (0x60)
+#define RAMSIZE (128)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x7F)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x7FF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x91
+#define SIGNATURE_2 0x0A
+
+
+/* Device Pin Definitions */
+#define RXD_DDR DDRD
+#define RXD_PORT PORTD
+#define RXD_PIN PIND
+#define RXD_BIT 0
+
+#define TXD_DDR DDRD
+#define TXD_PORT PORTD
+#define TXD_PIN PIND
+#define TXD_BIT 1
+
+#define PA1_DDR DDRXTAL
+#define PA1_PORT PORTXTAL
+#define PA1_PIN PINXTAL
+#define PA1_BIT XTAL2
+
+#define PA0_DDR DDRXTAL
+#define PA0_PORT PORTXTAL
+#define PA0_PIN PINXTAL
+#define PA0_BIT XTAL1
+
+#define INT0_DDR DDRD
+#define INT0_PORT PORTD
+#define INT0_PIN PIND
+#define INT0_BIT 2
+
+#define XCK_DDR DDRD
+#define XCK_PORT PORTD
+#define XCK_PIN PIND
+#define XCK_BIT 2
+
+#define CKOUT_DDR DDRD
+#define CKOUT_PORT PORTD
+#define CKOUT_PIN PIND
+#define CKOUT_BIT 2
+
+#define INT1_DDR DDRD
+#define INT1_PORT PORTD
+#define INT1_PIN PIND
+#define INT1_BIT 3
+
+#define T0_DDR DDRD
+#define T0_PORT PORTD
+#define T0_PIN PIND
+#define T0_BIT 4
+
+#define T1_DDR DDRD
+#define T1_PORT PORTD
+#define T1_PIN PIND
+#define T1_BIT 5
+
+#define OC0B_DDR DDRD
+#define OC0B_PORT PORTD
+#define OC0B_PIN PIND
+#define OC0B_BIT 5
+
+#define ICP_DDR DDRD
+#define ICP_PORT PORTD
+#define ICP_PIN PIND
+#define ICP_BIT 6
+
+#define AIN0_DDR DDRB
+#define AIN0_PORT PORTB
+#define AIN0_PIN PINB
+#define AIN0_BIT 0
+
+#define AIN1_DDR DDRB
+#define AIN1_PORT PORTB
+#define AIN1_PIN PINB
+#define AIN1_BIT 1
+
+#define OC0A_DDR DDRB
+#define OC0A_PORT PORTB
+#define OC0A_PIN PINB
+#define OC0A_BIT 2
+
+#define OC1A_DDR DDRB
+#define OC1A_PORT PORTB
+#define OC1A_PIN PINB
+#define OC1A_BIT 3
+
+#define OC1B_DDR DDRB
+#define OC1B_PORT PORTB
+#define OC1B_PIN PINB
+#define OC1B_BIT 4
+
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 5
+
+#define DI_DDR DDRB
+#define DI_PORT PORTB
+#define DI_PIN PINB
+#define DI_BIT 5
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 6
+
+#define DO_DDR DDRB
+#define DO_PORT PORTB
+#define DO_PIN PINB
+#define DO_BIT 6
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 7
+
+#define SCL_DDR DDRB
+#define SCL_PORT PORTB
+#define SCL_PIN PINB
+#define SCL_BIT 7
+
+#endif /* _AVR_ATtiny2313A_H_ */
+
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn24a.h:1.1
--- /dev/null Mon May 10 12:10:58 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn24a.h Mon May 10 11:31:23 2010
@@ -0,0 +1,831 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn24a.h - definitions for ATtiny24A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn24a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny24A_H_
+#define _AVR_ATtiny24A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PRR _SFR_IO8(0x00)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ADLAR 4
+#define ACME 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define MUX5 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSR _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define TIFR1 _SFR_IO8(0x0B)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIMSK1 _SFR_IO8(0x0C)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define PCMSK0 _SFR_IO8(0x12)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define GPIOR0 _SFR_IO8(0x13)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x14)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x15)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define PCMSK1 _SFR_IO8(0x20)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define TCCR1C _SFR_IO8(0x22)
+#define FOC1B 6
+#define FOC1A 7
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSR10 0
+#define TSM 7
+
+#define ICR1 _SFR_IO16(0x24)
+
+#define ICR1L _SFR_IO8(0x24)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_IO8(0x25)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define CLKPR _SFR_IO8(0x26)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define DWDR _SFR_IO8(0x27)
+
+#define OCR1B _SFR_IO16(0x28)
+
+#define OCR1BL _SFR_IO8(0x28)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_IO8(0x29)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1A _SFR_IO16(0x2A)
+
+#define OCR1AL _SFR_IO8(0x2A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_IO8(0x2B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCNT1 _SFR_IO16(0x2C)
+
+#define TCNT1L _SFR_IO8(0x2C)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_IO8(0x2D)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define TCCR1B _SFR_IO8(0x2E)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1A _SFR_IO8(0x2F)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR0A _SFR_IO8(0x30)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0 _SFR_IO8(0x32)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+
+#define OCR0A _SFR_IO8(0x36)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR0 _SFR_IO8(0x38)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIMSK0 _SFR_IO8(0x39)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF0 4
+#define PCIF1 5
+#define INTF0 6
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+
+#define OCR0B _SFR_IO8(0x3C)
+#define OCR0_0 0
+#define OCR0_1 1
+#define OCR0_2 2
+#define OCR0_3 3
+#define OCR0_4 4
+#define OCR0_5 5
+#define OCR0_6 6
+#define OCR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define EXT_INT0_vect_num 1
+#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define PCINT0_vect_num 2
+#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 3
+#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */
+#define WATCHDOG_vect_num 4
+#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */
+#define TIM1_CAPT_vect_num 5
+#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */
+#define TIM1_COMPA_vect_num 6
+#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */
+#define TIM1_COMPB_vect_num 7
+#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */
+#define TIM1_OVF_vect_num 8
+#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */
+#define TIM0_COMPA_vect_num 9
+#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */
+#define TIM0_COMPB_vect_num 10
+#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */
+#define TIM0_OVF_vect_num 11
+#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */
+#define ANA_COMP_vect_num 12
+#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */
+#define ADC_vect_num 13
+#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */
+#define EE_RDY_vect_num 14
+#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */
+#define USI_STR_vect_num 15
+#define USI_STR_vect _VECTOR(15) /* USI START */
+#define USI_OVF_vect_num 16
+#define USI_OVF_vect _VECTOR(16) /* USI Overflow */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (17 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (32)
+#define RAMSTART (0x60)
+#define RAMSIZE (128)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x7F)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x7FF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x91
+#define SIGNATURE_2 0x0B
+
+
+/* Device Pin Definitions */
+#define ADC4_DDR DDRA
+#define ADC4_PORT PORTA
+#define ADC4_PIN PINA
+#define ADC4_BIT 4
+
+#define USCK_DDR DDRA
+#define USCK_PORT PORTA
+#define USCK_PIN PINA
+#define USCK_BIT 4
+
+#define SCL_DDR DDRA
+#define SCL_PORT PORTA
+#define SCL_PIN PINA
+#define SCL_BIT 4
+
+#define T1_DDR DDRA
+#define T1_PORT PORTA
+#define T1_PIN PINA
+#define T1_BIT 4
+
+#define PCINT4_DDR DDRA
+#define PCINT4_PORT PORTA
+#define PCINT4_PIN PINA
+#define PCINT4_BIT 4
+
+#define ADC3_DDR DDRA
+#define ADC3_PORT PORTA
+#define ADC3_PIN PINA
+#define ADC3_BIT 3
+
+#define T0_DDR DDRA
+#define T0_PORT PORTA
+#define T0_PIN PINA
+#define T0_BIT 3
+
+#define PCINT3_DDR DDRA
+#define PCINT3_PORT PORTA
+#define PCINT3_PIN PINA
+#define PCINT3_BIT 3
+
+#define ADC2_DDR DDRA
+#define ADC2_PORT PORTA
+#define ADC2_PIN PINA
+#define ADC2_BIT 2
+
+#define AIN1_DDR DDRA
+#define AIN1_PORT PORTA
+#define AIN1_PIN PINA
+#define AIN1_BIT 2
+
+#define PCINT2_DDR DDRA
+#define PCINT2_PORT PORTA
+#define PCINT2_PIN PINA
+#define PCINT2_BIT 2
+
+#define ADC1_DDR DDRA
+#define ADC1_PORT PORTA
+#define ADC1_PIN PINA
+#define ADC1_BIT 1
+
+#define AIN0_DDR DDRA
+#define AIN0_PORT PORTA
+#define AIN0_PIN PINA
+#define AIN0_BIT 1
+
+#define PCINT1_DDR DDRA
+#define PCINT1_PORT PORTA
+#define PCINT1_PIN PINA
+#define PCINT1_BIT 1
+
+#define ADC0_DDR DDRA
+#define ADC0_PORT PORTA
+#define ADC0_PIN PINA
+#define ADC0_BIT 0
+
+#define PCINT0_DDR DDRA
+#define PCINT0_PORT PORTA
+#define PCINT0_PIN PINA
+#define PCINT0_BIT 0
+
+#define PCINT8_DDR DDRB
+#define PCINT8_PORT PORTB
+#define PCINT8_PIN PINB
+#define PCINT8_BIT 0
+
+#define PCINT9_DDR DDRB
+#define PCINT9_PORT PORTB
+#define PCINT9_PIN PINB
+#define PCINT9_BIT 1
+
+#define PCINT11_DDR DDRB
+#define PCINT11_PORT PORTB
+#define PCINT11_PIN PINB
+#define PCINT11_BIT 3
+
+#define dW_DDR DDRB
+#define dW_PORT PORTB
+#define dW_PIN PINB
+#define dW_BIT 3
+
+#define PCINT10_DDR DDRB
+#define PCINT10_PORT PORTB
+#define PCINT10_PIN PINB
+#define PCINT10_BIT 2
+
+#define INT0_DDR DDRB
+#define INT0_PORT PORTB
+#define INT0_PIN PINB
+#define INT0_BIT 2
+
+#define OC0A_DDR DDRB
+#define OC0A_PORT PORTB
+#define OC0A_PIN PINB
+#define OC0A_BIT 2
+
+#define CKOUT_DDR DDRB
+#define CKOUT_PORT PORTB
+#define CKOUT_PIN PINB
+#define CKOUT_BIT 2
+
+#define PCINT7_DDR DDRA
+#define PCINT7_PORT PORTA
+#define PCINT7_PIN PINA
+#define PCINT7_BIT 7
+
+#define ICP1_DDR DDRA
+#define ICP1_PORT PORTA
+#define ICP1_PIN PINA
+#define ICP1_BIT 7
+
+#define OC0B_DDR DDRA
+#define OC0B_PORT PORTA
+#define OC0B_PIN PINA
+#define OC0B_BIT 7
+
+#define ADC7_DDR DDRA
+#define ADC7_PORT PORTA
+#define ADC7_PIN PINA
+#define ADC7_BIT 7
+
+#define PCINT6_DDR DDRA
+#define PCINT6_PORT PORTA
+#define PCINT6_PIN PINA
+#define PCINT6_BIT 6
+
+#define OC1A_DDR DDRA
+#define OC1A_PORT PORTA
+#define OC1A_PIN PINA
+#define OC1A_BIT 6
+
+#define DI_DDR DDRA
+#define DI_PORT PORTA
+#define DI_PIN PINA
+#define DI_BIT 6
+
+#define SDA_DDR DDRA
+#define SDA_PORT PORTA
+#define SDA_PIN PINA
+#define SDA_BIT 6
+
+#define MOSI_DDR DDRA
+#define MOSI_PORT PORTA
+#define MOSI_PIN PINA
+#define MOSI_BIT 6
+
+#define ADC6_DDR DDRA
+#define ADC6_PORT PORTA
+#define ADC6_PIN PINA
+#define ADC6_BIT 6
+
+#define ADC5_DDR DDRA
+#define ADC5_PORT PORTA
+#define ADC5_PIN PINA
+#define ADC5_BIT 5
+
+#define DO_DDR DDRA
+#define DO_PORT PORTA
+#define DO_PIN PINA
+#define DO_BIT 5
+
+#define MISO_DDR DDRA
+#define MISO_PORT PORTA
+#define MISO_PIN PINA
+#define MISO_BIT 5
+
+#define OC1B_DDR DDRA
+#define OC1B_PORT PORTA
+#define OC1B_PIN PINA
+#define OC1B_BIT 5
+
+#define PCINT5_DDR DDRA
+#define PCINT5_PORT PORTA
+#define PCINT5_PIN PINA
+#define PCINT5_BIT 5
+
+#endif /* _AVR_ATtiny24A_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iotn26.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn26.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn26.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn26.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iotn26.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOTN26_H_
#define _AVR_IOTN26_H_ 1
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn261a.h:1.1
--- /dev/null Mon May 10 12:10:59 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn261a.h Mon May 10 11:31:23 2010
@@ -0,0 +1,976 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn261a.h - definitions for ATtiny261A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn261a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny261A_H_
+#define _AVR_ATtiny261A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define TCCR1E _SFR_IO8(0x00)
+#define OC1OE0 0
+#define OC1OE1 1
+#define OC1OE2 2
+#define OC1OE3 3
+#define OC1OE4 4
+#define OC1OE5 5
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define AREFD 3
+#define ADC3D 4
+#define ADC4D 5
+#define ADC5D 6
+#define ADC6D 7
+
+#define DIDR1 _SFR_IO8(0x02)
+#define ADC7D 4
+#define ADC8D 5
+#define ADC9D 6
+#define ADC10D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define MUX5 3
+#define REFS2 4
+#define IPR 5
+#define GSEL 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSRA _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACME 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define ACSRB _SFR_IO8(0x09)
+#define ACM0 0
+#define ACM1 1
+#define ACM2 2
+#define HLEV 6
+#define HSEL 7
+
+#define GPIOR0 _SFR_IO8(0x0A)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x0B)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x0C)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define USIPP _SFR_IO8(0x11)
+#define USIPOS 0
+
+#define OCR0B _SFR_IO8(0x12)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define OCR0A _SFR_IO8(0x13)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define TCNT0H _SFR_IO8(0x14)
+#define TCNT0H_0 0
+#define TCNT0H_1 1
+#define TCNT0H_2 2
+#define TCNT0H_3 3
+#define TCNT0H_4 4
+#define TCNT0H_5 5
+#define TCNT0H_6 6
+#define TCNT0H_7 7
+
+#define TCCR0A _SFR_IO8(0x15)
+#define WGM00 0
+#define ACIC0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define DWDR _SFR_IO8(0x20)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define WDTCR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define PCMSK1 _SFR_IO8(0x22)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0 _SFR_IO8(0x23)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define DT1 _SFR_IO8(0x24)
+#define DT1L0 0
+#define DT1L1 1
+#define DT1L2 2
+#define DT1L3 3
+#define DT1H0 4
+#define DT1H1 5
+#define DT1H2 6
+#define DT1H3 7
+
+#define TC1H _SFR_IO8(0x25)
+#define TC18 0
+#define TC19 1
+
+#define TCCR1D _SFR_IO8(0x26)
+#define WGM10 0
+#define WGM11 1
+#define FPF1 2
+#define FPAC1 3
+#define FPES1 4
+#define FPNC1 5
+#define FPEN1 6
+#define FPIE1 7
+
+#define TCCR1C _SFR_IO8(0x27)
+#define PWM1D 0
+#define FOC1D 1
+#define COM1D0 2
+#define COM1D1 3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR _SFR_IO8(0x28)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PCKE 2
+#define LSM 7
+
+#define OCR1D _SFR_IO8(0x2A)
+#define OCR1D0 0
+#define OCR1D1 1
+#define OCR1D2 2
+#define OCR1D3 3
+#define OCR1D4 4
+#define OCR1D5 5
+#define OCR1D6 6
+#define OCR1D7 7
+
+#define OCR1C _SFR_IO8(0x2B)
+#define OCR1C0 0
+#define OCR1C1 1
+#define OCR1C2 2
+#define OCR1C3 3
+#define OCR1C4 4
+#define OCR1C5 5
+#define OCR1C6 6
+#define OCR1C7 7
+
+#define OCR1B _SFR_IO8(0x2C)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define OCR1A _SFR_IO8(0x2D)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define TCNT1 _SFR_IO8(0x2E)
+#define TC1H_0 0
+#define TC1H_1 1
+#define TC1H_2 2
+#define TC1H_3 3
+#define TC1H_4 4
+#define TC1H_5 5
+#define TC1H_6 6
+#define TC1H_7 7
+
+#define TCCR1B _SFR_IO8(0x2F)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define CS13 3
+#define DTPS10 4
+#define DTPS11 5
+#define PSR1 6
+
+#define TCCR1A _SFR_IO8(0x30)
+#define PWM1B 0
+#define PWM1A 1
+#define FOC1B 2
+#define FOC1A 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0L _SFR_IO8(0x32)
+#define TCNT0L_0 0
+#define TCNT0L_1 1
+#define TCNT0L_2 2
+#define TCNT0L_3 3
+#define TCNT0L_4 4
+#define TCNT0L_5 5
+#define TCNT0L_6 6
+#define TCNT0L_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define PSR0 3
+#define TSM 4
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define BODSE 2
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+#define BODS 7
+
+#define PRR _SFR_IO8(0x36)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR _SFR_IO8(0x38)
+#define ICF0 0
+#define TOV0 1
+#define TOV1 2
+#define OCF0B 3
+#define OCF0A 4
+#define OCF1B 5
+#define OCF1A 6
+#define OCF1D 7
+
+#define TIMSK _SFR_IO8(0x39)
+#define TICIE0 0
+#define TOIE0 1
+#define TOIE1 2
+#define OCIE0B 3
+#define OCIE0A 4
+#define OCIE1B 5
+#define OCIE1A 6
+#define OCIE1D 7
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF 5
+#define INTF0 6
+#define INTF1 7
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+#define INT1 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
+#define PCINT_vect_num 2
+#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */
+#define TIMER1_COMPA_vect_num 3
+#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPB_vect_num 4
+#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */
+#define TIMER1_OVF_vect_num 5
+#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num 6
+#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */
+#define USI_START_vect_num 7
+#define USI_START_vect _VECTOR(7) /* USI Start */
+#define USI_OVF_vect_num 8
+#define USI_OVF_vect _VECTOR(8) /* USI Overflow */
+#define EE_RDY_vect_num 9
+#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */
+#define ANA_COMP_vect_num 10
+#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */
+#define ADC_vect_num 11
+#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */
+#define WDT_vect_num 12
+#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */
+#define INT1_vect_num 13
+#define INT1_vect _VECTOR(13) /* External Interrupt 1 */
+#define TIMER0_COMPA_vect_num 14
+#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 15
+#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */
+#define TIMER0_CAPT_vect_num 16
+#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */
+#define TIMER1_COMPD_vect_num 17
+#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */
+#define FAULT_PROTECTION_vect_num 18
+#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (32)
+#define RAMSTART (0x60)
+#define RAMSIZE (128)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x7F)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x7FF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x91
+#define SIGNATURE_2 0x0C
+
+
+/* Device Pin Definitions */
+#define DI_B_DDR DDRMOSI
+#define DI_B_PORT PORTMOSI
+#define DI_B_PIN PINMOSI
+#define DI_B_BIT MOSI
+
+#define SDA_B_DDR DDRMOSI
+#define SDA_B_PORT PORTMOSI
+#define SDA_B_PIN PINMOSI
+#define SDA_B_BIT MOSI
+
+#define _OC1A_DDR DDRMOSI
+#define _OC1A_PORT PORTMOSI
+#define _OC1A_PIN PINMOSI
+#define _OC1A_BIT MOSI
+
+#define PCINT8_DDR DDRMOSI
+#define PCINT8_PORT PORTMOSI
+#define PCINT8_PIN PINMOSI
+#define PCINT8_BIT MOSI
+
+#define PB0_DDR DDRMOSI
+#define PB0_PORT PORTMOSI
+#define PB0_PIN PINMOSI
+#define PB0_BIT MOSI
+
+#define DO_B_DDR DDRMISO
+#define DO_B_PORT PORTMISO
+#define DO_B_PIN PINMISO
+#define DO_B_BIT MISO
+
+#define OC1A_DDR DDRMISO
+#define OC1A_PORT PORTMISO
+#define OC1A_PIN PINMISO
+#define OC1A_BIT MISO
+
+#define PCINT9_DDR DDRMISO
+#define PCINT9_PORT PORTMISO
+#define PCINT9_PIN PINMISO
+#define PCINT9_BIT MISO
+
+#define PB1_DDR DDRMISO
+#define PB1_PORT PORTMISO
+#define PB1_PIN PINMISO
+#define PB1_BIT MISO
+
+#define USCK_B_DDR DDRSCK
+#define USCK_B_PORT PORTSCK
+#define USCK_B_PIN PINSCK
+#define USCK_B_BIT SCK
+
+#define SCL_B_DDR DDRSCK
+#define SCL_B_PORT PORTSCK
+#define SCL_B_PIN PINSCK
+#define SCL_B_BIT SCK
+
+#define OC1B_DDR DDRSCK
+#define OC1B_PORT PORTSCK
+#define OC1B_PIN PINSCK
+#define OC1B_BIT SCK
+
+#define PCINT10_DDR DDRSCK
+#define PCINT10_PORT PORTSCK
+#define PCINT10_PIN PINSCK
+#define PCINT10_BIT SCK
+
+#define PB2_DDR DDRSCK
+#define PB2_PORT PORTSCK
+#define PB2_PIN PINSCK
+#define PB2_BIT SCK
+
+#define PCINT11_DDR DDROC1B
+#define PCINT11_PORT PORTOC1B
+#define PCINT11_PIN PINOC1B
+#define PCINT11_BIT OC1B
+
+#define PB3_DDR DDROC1B
+#define PB3_PORT PORTOC1B
+#define PB3_PIN PINOC1B
+#define PB3_BIT OC1B
+
+#define PCINT12_DDR DDRADC
+#define PCINT12_PORT PORTADC
+#define PCINT12_PIN PINADC
+#define PCINT12_BIT ADC7
+
+#define _OC1D_DDR DDRADC
+#define _OC1D_PORT PORTADC
+#define _OC1D_PIN PINADC
+#define _OC1D_BIT ADC7
+
+#define CLKI_DDR DDRADC
+#define CLKI_PORT PORTADC
+#define CLKI_PIN PINADC
+#define CLKI_BIT ADC7
+
+#define PB4_DDR DDRADC
+#define PB4_PORT PORTADC
+#define PB4_PIN PINADC
+#define PB4_BIT ADC7
+
+#define PCINT13_DDR DDRADC
+#define PCINT13_PORT PORTADC
+#define PCINT13_PIN PINADC
+#define PCINT13_BIT ADC8
+
+#define OC1D_DDR DDRADC
+#define OC1D_PORT PORTADC
+#define OC1D_PIN PINADC
+#define OC1D_BIT ADC8
+
+#define CKLO_DDR DDRADC
+#define CKLO_PORT PORTADC
+#define CKLO_PIN PINADC
+#define CKLO_BIT ADC8
+
+#define PB5_DDR DDRADC
+#define PB5_PORT PORTADC
+#define PB5_PIN PINADC
+#define PB5_BIT ADC8
+
+#define INT0_DDR DDRADC
+#define INT0_PORT PORTADC
+#define INT0_PIN PINADC
+#define INT0_BIT ADC9
+
+#define T0_DDR DDRADC
+#define T0_PORT PORTADC
+#define T0_PIN PINADC
+#define T0_BIT ADC9
+
+#define PCINT14_DDR DDRADC
+#define PCINT14_PORT PORTADC
+#define PCINT14_PIN PINADC
+#define PCINT14_BIT ADC9
+
+#define PB6_DDR DDRADC
+#define PB6_PORT PORTADC
+#define PB6_PIN PINADC
+#define PB6_BIT ADC9
+
+#define PCINT15_DDR DDRADC1
+#define PCINT15_PORT PORTADC1
+#define PCINT15_PIN PINADC1
+#define PCINT15_BIT ADC10
+
+#define PB7_DDR DDRADC1
+#define PB7_PORT PORTADC1
+#define PB7_PIN PINADC1
+#define PB7_BIT ADC10
+
+#define AIN1_DDR DDRADC
+#define AIN1_PORT PORTADC
+#define AIN1_PIN PINADC
+#define AIN1_BIT ADC6
+
+#define PCINT7_DDR DDRADC
+#define PCINT7_PORT PORTADC
+#define PCINT7_PIN PINADC
+#define PCINT7_BIT ADC6
+
+#define PA7_DDR DDRADC
+#define PA7_PORT PORTADC
+#define PA7_PIN PINADC
+#define PA7_BIT ADC6
+
+#define AIN0_DDR DDRADC
+#define AIN0_PORT PORTADC
+#define AIN0_PIN PINADC
+#define AIN0_BIT ADC5
+
+#define PCINT6_DDR DDRADC
+#define PCINT6_PORT PORTADC
+#define PCINT6_PIN PINADC
+#define PCINT6_BIT ADC5
+
+#define PA6_DDR DDRADC
+#define PA6_PORT PORTADC
+#define PA6_PIN PINADC
+#define PA6_BIT ADC5
+
+#define AIN2_DDR DDRADC
+#define AIN2_PORT PORTADC
+#define AIN2_PIN PINADC
+#define AIN2_BIT ADC4
+
+#define PCINT5_DDR DDRADC
+#define PCINT5_PORT PORTADC
+#define PCINT5_PIN PINADC
+#define PCINT5_BIT ADC4
+
+#define PA5_DDR DDRADC
+#define PA5_PORT PORTADC
+#define PA5_PIN PINADC
+#define PA5_BIT ADC4
+
+#define ICP0_DDR DDRADC
+#define ICP0_PORT PORTADC
+#define ICP0_PIN PINADC
+#define ICP0_BIT ADC3
+
+#define PCINT4_DDR DDRADC
+#define PCINT4_PORT PORTADC
+#define PCINT4_PIN PINADC
+#define PCINT4_BIT ADC3
+
+#define PA4_DDR DDRADC
+#define PA4_PORT PORTADC
+#define PA4_PIN PINADC
+#define PA4_BIT ADC3
+
+#define PCINT3_DDR DDRAREF
+#define PCINT3_PORT PORTAREF
+#define PCINT3_PIN PINAREF
+#define PCINT3_BIT AREF
+
+#define PA3_DDR DDRAREF
+#define PA3_PORT PORTAREF
+#define PA3_PIN PINAREF
+#define PA3_BIT AREF
+
+#define INT1_DDR DDRADC
+#define INT1_PORT PORTADC
+#define INT1_PIN PINADC
+#define INT1_BIT ADC2
+
+#define USCK_A_DDR DDRADC
+#define USCK_A_PORT PORTADC
+#define USCK_A_PIN PINADC
+#define USCK_A_BIT ADC2
+
+#define SCL_A_DDR DDRADC
+#define SCL_A_PORT PORTADC
+#define SCL_A_PIN PINADC
+#define SCL_A_BIT ADC2
+
+#define PCINT2_DDR DDRADC
+#define PCINT2_PORT PORTADC
+#define PCINT2_PIN PINADC
+#define PCINT2_BIT ADC2
+
+#define PA2_DDR DDRADC
+#define PA2_PORT PORTADC
+#define PA2_PIN PINADC
+#define PA2_BIT ADC2
+
+#define DO_A_DDR DDRADC
+#define DO_A_PORT PORTADC
+#define DO_A_PIN PINADC
+#define DO_A_BIT ADC1
+
+#define PCINT1_DDR DDRADC
+#define PCINT1_PORT PORTADC
+#define PCINT1_PIN PINADC
+#define PCINT1_BIT ADC1
+
+#define PA1_DDR DDRADC
+#define PA1_PORT PORTADC
+#define PA1_PIN PINADC
+#define PA1_BIT ADC1
+
+#define DI_A_DDR DDRADC
+#define DI_A_PORT PORTADC
+#define DI_A_PIN PINADC
+#define DI_A_BIT ADC0
+
+#define SDA_A_DDR DDRADC
+#define SDA_A_PORT PORTADC
+#define SDA_A_PIN PINADC
+#define SDA_A_BIT ADC0
+
+#define PCINT0_DDR DDRADC
+#define PCINT0_PORT PORTADC
+#define PCINT0_PIN PINADC
+#define PCINT0_BIT ADC0
+
+#define PA0_DDR DDRADC
+#define PA0_PORT PORTADC
+#define PA0_PIN PINADC
+#define PA0_BIT ADC0
+
+#endif /* _AVR_ATtiny261A_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iotn28.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn28.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn28.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn28.h Mon May 10 11:31:23 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotn28.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef __ASSEMBLER__
# warning "MCU not supported by the C compiler"
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn4313.h:1.1
--- /dev/null Mon May 10 12:10:59 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn4313.h Mon May 10 11:31:23 2010
@@ -0,0 +1,769 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn4313.h - definitions for ATtiny4313 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn4313.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny4313_H_
+#define _AVR_ATtiny4313_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define DIDR _SFR_IO8(0x001)
+#define AIN0D 0
+#define AIN1D 1
+
+#define UBRRH _SFR_IO8(0x002)
+#define UBRR8 0
+#define UBRR9 1
+#define UBRR10 2
+#define UBRR11 3
+
+#define UCSRC _SFR_IO8(0x003)
+#define UCPOL 0
+#define UCSZ0 1
+#define UCSZ1 2
+#define USBS 3
+#define UPM0 4
+#define UPM1 5
+#define UMSEL 6
+
+#define PCMSK1 _SFR_IO8(0x004)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+
+#define PCMSK2 _SFR_IO8(0x005)
+#define PCINT11 0
+#define PCINT12 1
+#define PCINT13 2
+#define PCINT14 3
+#define PCINT15 4
+#define PCINT16 5
+#define PCINT17 6
+
+#define PRR _SFR_IO8(0x006)
+#define PRUSART 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define BODCR _SFR_IO8(0x007)
+#define BPDSE 0
+#define BPDS 1
+
+#define ACSR _SFR_IO8(0x008)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define UBRRL _SFR_IO8(0x009)
+#define UBRR0 0
+#define UBRR1 1
+#define UBRR2 2
+#define UBRR3 3
+#define UBRR4 4
+#define UBRR5 5
+#define UBRR6 6
+#define UBRR7 7
+
+#define UCSRB _SFR_IO8(0x00A)
+#define TXB8 0
+#define RXB8 1
+#define UCSZ2 2
+#define TXEN 3
+#define RXEN 4
+#define UDRIE 5
+#define TXCIE 6
+#define RXCIE 7
+
+#define UCSRA _SFR_IO8(0x00B)
+#define MPCM 0
+#define U2X 1
+#define UPE 2
+#define DOR 3
+#define FE 4
+#define UDRE 5
+#define TXC 6
+#define RXC 7
+
+#define UDR _SFR_IO8(0x00C)
+#define UDR0 0
+#define UDR1 1
+#define UDR2 2
+#define UDR3 3
+#define UDR4 4
+#define UDR5 5
+#define UDR6 6
+#define UDR7 7
+
+#define USICR _SFR_IO8(0x00D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x00E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x00F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define PIND _SFR_IO8(0x010)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+
+#define DDRD _SFR_IO8(0x011)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+
+#define PORTD _SFR_IO8(0x012)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+
+#define GPIOR0 _SFR_IO8(0x013)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x014)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x015)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define PINB _SFR_IO8(0x016)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x017)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x018)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x019)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+
+#define DDRA _SFR_IO8(0x01A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+
+#define PORTA _SFR_IO8(0x01B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+
+#define EECR _SFR_IO8(0x01C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x01D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO8(0x01E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+
+#define PCMSK _SFR_IO8(0x020)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define WDTCR _SFR_IO8(0x021)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define TCCR1C _SFR_IO8(0x022)
+#define FOC1B 6
+#define FOC1A 7
+
+#define GTCCR _SFR_IO8(0x023)
+#define PSR10 0
+
+#define ICR1 _SFR_IO16(0x024)
+
+#define ICR1L _SFR_IO8(0x024)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_IO8(0x025)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define CLKPR _SFR_IO8(0x026)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define OCR1B _SFR_IO16(0x028)
+
+#define OCR1BL _SFR_IO8(0x028)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_IO8(0x029)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1A _SFR_IO16(0x02A)
+
+#define OCR1AL _SFR_IO8(0x02A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_IO8(0x02B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCNT1 _SFR_IO16(0x02C)
+
+#define TCNT1L _SFR_IO8(0x02C)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_IO8(0x02D)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define TCCR1B _SFR_IO8(0x02E)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1A _SFR_IO8(0x02F)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR0A _SFR_IO8(0x030)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define OSCCAL _SFR_IO8(0x031)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+
+#define TCNT0 _SFR_IO8(0x032)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCCR0B _SFR_IO8(0x033)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define MCUSR _SFR_IO8(0x034)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x035)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define SM0 4
+#define SE 5
+#define SM1 6
+#define PUD 7
+
+#define OCR0A _SFR_IO8(0x036)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define SPMCSR _SFR_IO8(0x037)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR _SFR_IO8(0x038)
+#define OCF0A 0
+#define TOV0 1
+#define OCF0B 2
+#define ICF1 3
+#define OCF1B 5
+#define OCF1A 6
+#define TOV1 7
+
+#define TIMSK _SFR_IO8(0x039)
+#define OCIE0A 0
+#define TOIE0 1
+#define OCIE0B 2
+#define ICIE1 3
+#define OCIE1B 5
+#define OCIE1A 6
+#define TOIE1 7
+
+#define EIFR _SFR_IO8(0x03A)
+#define PCIF 5
+#define INTF0 6
+#define INTF1 7
+
+#define GIMSK _SFR_IO8(0x03B)
+#define PCIE 5
+#define INT0 6
+#define INT1 7
+
+#define OCR0B _SFR_IO8(0x03C)
+#define OCR0_0 0
+#define OCR0_1 1
+#define OCR0_2 2
+#define OCR0_3 3
+#define OCR0_4 4
+#define OCR0_5 5
+#define OCR0_6 6
+#define OCR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define INT1_vect_num 2
+#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
+#define TIMER1_CAPT_vect_num 3
+#define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect_num 4
+#define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */
+#define TIMER1_OVF_vect_num 5
+#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num 6
+#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */
+#define USART_RX_vect_num 7
+#define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */
+#define USART_UDRE_vect_num 8
+#define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */
+#define USART_TX_vect_num 9
+#define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */
+#define ANA_COMP_vect_num 10
+#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */
+#define PCINT_B_vect_num 11
+#define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */
+#define TIMER1_COMPB_vect_num 12
+#define TIMER1_COMPB_vect _VECTOR(12) /* */
+#define TIMER0_COMPA_vect_num 13
+#define TIMER0_COMPA_vect _VECTOR(13) /* */
+#define TIMER0_COMPB_vect_num 14
+#define TIMER0_COMPB_vect _VECTOR(14) /* */
+#define USI_START_vect_num 15
+#define USI_START_vect _VECTOR(15) /* USI Start Condition */
+#define USI_OVERFLOW_vect_num 16
+#define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */
+#define WDT_OVERFLOW_vect_num 18
+#define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */
+#define PCINT_D_vect_num 20
+#define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */
+#define EEPROM_Ready_vect_num 17
+#define EEPROM_Ready_vect _VECTOR(17) /* */
+#define PCINT_A_vect_num 19
+#define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART (0x60)
+#define RAMSIZE (256)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0xFF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0xFFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x92
+#define SIGNATURE_2 0x0D
+
+
+/* Device Pin Definitions */
+#define RXD_DDR DDRD
+#define RXD_PORT PORTD
+#define RXD_PIN PIND
+#define RXD_BIT 0
+
+#define TXD_DDR DDRD
+#define TXD_PORT PORTD
+#define TXD_PIN PIND
+#define TXD_BIT 1
+
+#define PA1_DDR DDRXTAL
+#define PA1_PORT PORTXTAL
+#define PA1_PIN PINXTAL
+#define PA1_BIT XTAL2
+
+#define PA0_DDR DDRXTAL
+#define PA0_PORT PORTXTAL
+#define PA0_PIN PINXTAL
+#define PA0_BIT XTAL1
+
+#define INT0_DDR DDRD
+#define INT0_PORT PORTD
+#define INT0_PIN PIND
+#define INT0_BIT 2
+
+#define XCK_DDR DDRD
+#define XCK_PORT PORTD
+#define XCK_PIN PIND
+#define XCK_BIT 2
+
+#define CKOUT_DDR DDRD
+#define CKOUT_PORT PORTD
+#define CKOUT_PIN PIND
+#define CKOUT_BIT 2
+
+#define INT1_DDR DDRD
+#define INT1_PORT PORTD
+#define INT1_PIN PIND
+#define INT1_BIT 3
+
+#define T0_DDR DDRD
+#define T0_PORT PORTD
+#define T0_PIN PIND
+#define T0_BIT 4
+
+#define T1_DDR DDRD
+#define T1_PORT PORTD
+#define T1_PIN PIND
+#define T1_BIT 5
+
+#define OC0B_DDR DDRD
+#define OC0B_PORT PORTD
+#define OC0B_PIN PIND
+#define OC0B_BIT 5
+
+#define ICP_DDR DDRD
+#define ICP_PORT PORTD
+#define ICP_PIN PIND
+#define ICP_BIT 6
+
+#define AIN0_DDR DDRB
+#define AIN0_PORT PORTB
+#define AIN0_PIN PINB
+#define AIN0_BIT 0
+
+#define AIN1_DDR DDRB
+#define AIN1_PORT PORTB
+#define AIN1_PIN PINB
+#define AIN1_BIT 1
+
+#define OC0A_DDR DDRB
+#define OC0A_PORT PORTB
+#define OC0A_PIN PINB
+#define OC0A_BIT 2
+
+#define OC1A_DDR DDRB
+#define OC1A_PORT PORTB
+#define OC1A_PIN PINB
+#define OC1A_BIT 3
+
+#define OC1B_DDR DDRB
+#define OC1B_PORT PORTB
+#define OC1B_PIN PINB
+#define OC1B_BIT 4
+
+#define MOSI_DDR DDRB
+#define MOSI_PORT PORTB
+#define MOSI_PIN PINB
+#define MOSI_BIT 5
+
+#define DI_DDR DDRB
+#define DI_PORT PORTB
+#define DI_PIN PINB
+#define DI_BIT 5
+
+#define MISO_DDR DDRB
+#define MISO_PORT PORTB
+#define MISO_PIN PINB
+#define MISO_BIT 6
+
+#define DO_DDR DDRB
+#define DO_PORT PORTB
+#define DO_PIN PINB
+#define DO_BIT 6
+
+#define SCK_DDR DDRB
+#define SCK_PORT PORTB
+#define SCK_PIN PINB
+#define SCK_BIT 7
+
+#define SCL_DDR DDRB
+#define SCL_PORT PORTB
+#define SCL_PIN PINB
+#define SCL_BIT 7
+
+#endif /* _AVR_ATtiny4313_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iotn43u.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn43u.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn43u.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn43u.h Mon May 10 11:31:23 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iotn43u.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOTN43U_H_
@@ -555,7 +555,7 @@
#define FUSE_SPIEN (unsigned char)~_BV(5)
#define FUSE_DWEN (unsigned char)~_BV(6)
#define FUSE_RSTDISBL (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0)
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn44a.h:1.1
--- /dev/null Mon May 10 12:10:59 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn44a.h Mon May 10 11:31:23 2010
@@ -0,0 +1,831 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn44a.h - definitions for ATtiny44A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn44a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny44A_H_
+#define _AVR_ATtiny44A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define PRR _SFR_IO8(0x00)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ADLAR 4
+#define ACME 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define MUX5 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSR _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define TIFR1 _SFR_IO8(0x0B)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIMSK1 _SFR_IO8(0x0C)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define PCMSK0 _SFR_IO8(0x12)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define GPIOR0 _SFR_IO8(0x13)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x14)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x15)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define PCMSK1 _SFR_IO8(0x20)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+
+#define WDTCSR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define TCCR1C _SFR_IO8(0x22)
+#define FOC1B 6
+#define FOC1A 7
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSR10 0
+#define TSM 7
+
+#define ICR1 _SFR_IO16(0x24)
+
+#define ICR1L _SFR_IO8(0x24)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_IO8(0x25)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define CLKPR _SFR_IO8(0x26)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define DWDR _SFR_IO8(0x27)
+
+#define OCR1B _SFR_IO16(0x28)
+
+#define OCR1BL _SFR_IO8(0x28)
+#define OCR1BL0 0
+#define OCR1BL1 1
+#define OCR1BL2 2
+#define OCR1BL3 3
+#define OCR1BL4 4
+#define OCR1BL5 5
+#define OCR1BL6 6
+#define OCR1BL7 7
+
+#define OCR1BH _SFR_IO8(0x29)
+#define OCR1BH0 0
+#define OCR1BH1 1
+#define OCR1BH2 2
+#define OCR1BH3 3
+#define OCR1BH4 4
+#define OCR1BH5 5
+#define OCR1BH6 6
+#define OCR1BH7 7
+
+#define OCR1A _SFR_IO16(0x2A)
+
+#define OCR1AL _SFR_IO8(0x2A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_IO8(0x2B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCNT1 _SFR_IO16(0x2C)
+
+#define TCNT1L _SFR_IO8(0x2C)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_IO8(0x2D)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define TCCR1B _SFR_IO8(0x2E)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1A _SFR_IO8(0x2F)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR0A _SFR_IO8(0x30)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0 _SFR_IO8(0x32)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+
+#define OCR0A _SFR_IO8(0x36)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR0 _SFR_IO8(0x38)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIMSK0 _SFR_IO8(0x39)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF0 4
+#define PCIF1 5
+#define INTF0 6
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+
+#define OCR0B _SFR_IO8(0x3C)
+#define OCR0_0 0
+#define OCR0_1 1
+#define OCR0_2 2
+#define OCR0_3 3
+#define OCR0_4 4
+#define OCR0_5 5
+#define OCR0_6 6
+#define OCR0_7 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define EXT_INT0_vect_num 1
+#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
+#define PCINT0_vect_num 2
+#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect_num 3
+#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */
+#define WATCHDOG_vect_num 4
+#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */
+#define TIM1_CAPT_vect_num 5
+#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */
+#define TIM1_COMPA_vect_num 6
+#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */
+#define TIM1_COMPB_vect_num 7
+#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */
+#define TIM1_OVF_vect_num 8
+#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */
+#define TIM0_COMPA_vect_num 9
+#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */
+#define TIM0_COMPB_vect_num 10
+#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */
+#define TIM0_OVF_vect_num 11
+#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */
+#define ANA_COMP_vect_num 12
+#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */
+#define ADC_vect_num 13
+#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */
+#define EE_RDY_vect_num 14
+#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */
+#define USI_STR_vect_num 15
+#define USI_STR_vect _VECTOR(15) /* USI START */
+#define USI_OVF_vect_num 16
+#define USI_OVF_vect _VECTOR(16) /* USI Overflow */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (17 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART (0x60)
+#define RAMSIZE (256)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0xFF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0xFFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x92
+#define SIGNATURE_2 0x07
+
+
+/* Device Pin Definitions */
+#define ADC4_DDR DDRA
+#define ADC4_PORT PORTA
+#define ADC4_PIN PINA
+#define ADC4_BIT 4
+
+#define USCK_DDR DDRA
+#define USCK_PORT PORTA
+#define USCK_PIN PINA
+#define USCK_BIT 4
+
+#define SCL_DDR DDRA
+#define SCL_PORT PORTA
+#define SCL_PIN PINA
+#define SCL_BIT 4
+
+#define T1_DDR DDRA
+#define T1_PORT PORTA
+#define T1_PIN PINA
+#define T1_BIT 4
+
+#define PCINT4_DDR DDRA
+#define PCINT4_PORT PORTA
+#define PCINT4_PIN PINA
+#define PCINT4_BIT 4
+
+#define ADC3_DDR DDRA
+#define ADC3_PORT PORTA
+#define ADC3_PIN PINA
+#define ADC3_BIT 3
+
+#define T0_DDR DDRA
+#define T0_PORT PORTA
+#define T0_PIN PINA
+#define T0_BIT 3
+
+#define PCINT3_DDR DDRA
+#define PCINT3_PORT PORTA
+#define PCINT3_PIN PINA
+#define PCINT3_BIT 3
+
+#define ADC2_DDR DDRA
+#define ADC2_PORT PORTA
+#define ADC2_PIN PINA
+#define ADC2_BIT 2
+
+#define AIN1_DDR DDRA
+#define AIN1_PORT PORTA
+#define AIN1_PIN PINA
+#define AIN1_BIT 2
+
+#define PCINT2_DDR DDRA
+#define PCINT2_PORT PORTA
+#define PCINT2_PIN PINA
+#define PCINT2_BIT 2
+
+#define ADC1_DDR DDRA
+#define ADC1_PORT PORTA
+#define ADC1_PIN PINA
+#define ADC1_BIT 1
+
+#define AIN0_DDR DDRA
+#define AIN0_PORT PORTA
+#define AIN0_PIN PINA
+#define AIN0_BIT 1
+
+#define PCINT1_DDR DDRA
+#define PCINT1_PORT PORTA
+#define PCINT1_PIN PINA
+#define PCINT1_BIT 1
+
+#define ADC0_DDR DDRA
+#define ADC0_PORT PORTA
+#define ADC0_PIN PINA
+#define ADC0_BIT 0
+
+#define PCINT0_DDR DDRA
+#define PCINT0_PORT PORTA
+#define PCINT0_PIN PINA
+#define PCINT0_BIT 0
+
+#define PCINT8_DDR DDRB
+#define PCINT8_PORT PORTB
+#define PCINT8_PIN PINB
+#define PCINT8_BIT 0
+
+#define PCINT9_DDR DDRB
+#define PCINT9_PORT PORTB
+#define PCINT9_PIN PINB
+#define PCINT9_BIT 1
+
+#define PCINT11_DDR DDRB
+#define PCINT11_PORT PORTB
+#define PCINT11_PIN PINB
+#define PCINT11_BIT 3
+
+#define dW_DDR DDRB
+#define dW_PORT PORTB
+#define dW_PIN PINB
+#define dW_BIT 3
+
+#define PCINT10_DDR DDRB
+#define PCINT10_PORT PORTB
+#define PCINT10_PIN PINB
+#define PCINT10_BIT 2
+
+#define INT0_DDR DDRB
+#define INT0_PORT PORTB
+#define INT0_PIN PINB
+#define INT0_BIT 2
+
+#define OC0A_DDR DDRB
+#define OC0A_PORT PORTB
+#define OC0A_PIN PINB
+#define OC0A_BIT 2
+
+#define CKOUT_DDR DDRB
+#define CKOUT_PORT PORTB
+#define CKOUT_PIN PINB
+#define CKOUT_BIT 2
+
+#define PCINT7_DDR DDRA
+#define PCINT7_PORT PORTA
+#define PCINT7_PIN PINA
+#define PCINT7_BIT 7
+
+#define ICP1_DDR DDRA
+#define ICP1_PORT PORTA
+#define ICP1_PIN PINA
+#define ICP1_BIT 7
+
+#define OC0B_DDR DDRA
+#define OC0B_PORT PORTA
+#define OC0B_PIN PINA
+#define OC0B_BIT 7
+
+#define ADC7_DDR DDRA
+#define ADC7_PORT PORTA
+#define ADC7_PIN PINA
+#define ADC7_BIT 7
+
+#define PCINT6_DDR DDRA
+#define PCINT6_PORT PORTA
+#define PCINT6_PIN PINA
+#define PCINT6_BIT 6
+
+#define OC1A_DDR DDRA
+#define OC1A_PORT PORTA
+#define OC1A_PIN PINA
+#define OC1A_BIT 6
+
+#define DI_DDR DDRA
+#define DI_PORT PORTA
+#define DI_PIN PINA
+#define DI_BIT 6
+
+#define SDA_DDR DDRA
+#define SDA_PORT PORTA
+#define SDA_PIN PINA
+#define SDA_BIT 6
+
+#define MOSI_DDR DDRA
+#define MOSI_PORT PORTA
+#define MOSI_PIN PINA
+#define MOSI_BIT 6
+
+#define ADC6_DDR DDRA
+#define ADC6_PORT PORTA
+#define ADC6_PIN PINA
+#define ADC6_BIT 6
+
+#define ADC5_DDR DDRA
+#define ADC5_PORT PORTA
+#define ADC5_PIN PINA
+#define ADC5_BIT 5
+
+#define DO_DDR DDRA
+#define DO_PORT PORTA
+#define DO_PIN PINA
+#define DO_BIT 5
+
+#define MISO_DDR DDRA
+#define MISO_PORT PORTA
+#define MISO_PIN PINA
+#define MISO_BIT 5
+
+#define OC1B_DDR DDRA
+#define OC1B_PORT PORTA
+#define OC1B_PIN PINA
+#define OC1B_BIT 5
+
+#define PCINT5_DDR DDRA
+#define PCINT5_PORT PORTA
+#define PCINT5_PIN PINA
+#define PCINT5_BIT 5
+
+#endif /* _AVR_ATtiny44A_H_ */
+
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn461a.h:1.1
--- /dev/null Mon May 10 12:11:00 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn461a.h Mon May 10 11:31:23 2010
@@ -0,0 +1,976 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn461a.h - definitions for ATtiny461A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn461a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny461A_H_
+#define _AVR_ATtiny461A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define TCCR1E _SFR_IO8(0x00)
+#define OC1OE0 0
+#define OC1OE1 1
+#define OC1OE2 2
+#define OC1OE3 3
+#define OC1OE4 4
+#define OC1OE5 5
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define AREFD 3
+#define ADC3D 4
+#define ADC4D 5
+#define ADC5D 6
+#define ADC6D 7
+
+#define DIDR1 _SFR_IO8(0x02)
+#define ADC7D 4
+#define ADC8D 5
+#define ADC9D 6
+#define ADC10D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define MUX5 3
+#define REFS2 4
+#define IPR 5
+#define GSEL 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSRA _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACME 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define ACSRB _SFR_IO8(0x09)
+#define ACM0 0
+#define ACM1 1
+#define ACM2 2
+#define HLEV 6
+#define HSEL 7
+
+#define GPIOR0 _SFR_IO8(0x0A)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x0B)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x0C)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define USIPP _SFR_IO8(0x11)
+#define USIPOS 0
+
+#define OCR0B _SFR_IO8(0x12)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define OCR0A _SFR_IO8(0x13)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define TCNT0H _SFR_IO8(0x14)
+#define TCNT0H_0 0
+#define TCNT0H_1 1
+#define TCNT0H_2 2
+#define TCNT0H_3 3
+#define TCNT0H_4 4
+#define TCNT0H_5 5
+#define TCNT0H_6 6
+#define TCNT0H_7 7
+
+#define TCCR0A _SFR_IO8(0x15)
+#define WGM00 0
+#define ACIC0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define DWDR _SFR_IO8(0x20)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define WDTCR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define PCMSK1 _SFR_IO8(0x22)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0 _SFR_IO8(0x23)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define DT1 _SFR_IO8(0x24)
+#define DT1L0 0
+#define DT1L1 1
+#define DT1L2 2
+#define DT1L3 3
+#define DT1H0 4
+#define DT1H1 5
+#define DT1H2 6
+#define DT1H3 7
+
+#define TC1H _SFR_IO8(0x25)
+#define TC18 0
+#define TC19 1
+
+#define TCCR1D _SFR_IO8(0x26)
+#define WGM10 0
+#define WGM11 1
+#define FPF1 2
+#define FPAC1 3
+#define FPES1 4
+#define FPNC1 5
+#define FPEN1 6
+#define FPIE1 7
+
+#define TCCR1C _SFR_IO8(0x27)
+#define PWM1D 0
+#define FOC1D 1
+#define COM1D0 2
+#define COM1D1 3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR _SFR_IO8(0x28)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PCKE 2
+#define LSM 7
+
+#define OCR1D _SFR_IO8(0x2A)
+#define OCR1D0 0
+#define OCR1D1 1
+#define OCR1D2 2
+#define OCR1D3 3
+#define OCR1D4 4
+#define OCR1D5 5
+#define OCR1D6 6
+#define OCR1D7 7
+
+#define OCR1C _SFR_IO8(0x2B)
+#define OCR1C0 0
+#define OCR1C1 1
+#define OCR1C2 2
+#define OCR1C3 3
+#define OCR1C4 4
+#define OCR1C5 5
+#define OCR1C6 6
+#define OCR1C7 7
+
+#define OCR1B _SFR_IO8(0x2C)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define OCR1A _SFR_IO8(0x2D)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define TCNT1 _SFR_IO8(0x2E)
+#define TC1H_0 0
+#define TC1H_1 1
+#define TC1H_2 2
+#define TC1H_3 3
+#define TC1H_4 4
+#define TC1H_5 5
+#define TC1H_6 6
+#define TC1H_7 7
+
+#define TCCR1B _SFR_IO8(0x2F)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define CS13 3
+#define DTPS10 4
+#define DTPS11 5
+#define PSR1 6
+
+#define TCCR1A _SFR_IO8(0x30)
+#define PWM1B 0
+#define PWM1A 1
+#define FOC1B 2
+#define FOC1A 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0L _SFR_IO8(0x32)
+#define TCNT0L_0 0
+#define TCNT0L_1 1
+#define TCNT0L_2 2
+#define TCNT0L_3 3
+#define TCNT0L_4 4
+#define TCNT0L_5 5
+#define TCNT0L_6 6
+#define TCNT0L_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define PSR0 3
+#define TSM 4
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define BODSE 2
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+#define BODS 7
+
+#define PRR _SFR_IO8(0x36)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR _SFR_IO8(0x38)
+#define ICF0 0
+#define TOV0 1
+#define TOV1 2
+#define OCF0B 3
+#define OCF0A 4
+#define OCF1B 5
+#define OCF1A 6
+#define OCF1D 7
+
+#define TIMSK _SFR_IO8(0x39)
+#define TICIE0 0
+#define TOIE0 1
+#define TOIE1 2
+#define OCIE0B 3
+#define OCIE0A 4
+#define OCIE1B 5
+#define OCIE1A 6
+#define OCIE1D 7
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF 5
+#define INTF0 6
+#define INTF1 7
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+#define INT1 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
+#define PCINT_vect_num 2
+#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */
+#define TIMER1_COMPA_vect_num 3
+#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPB_vect_num 4
+#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */
+#define TIMER1_OVF_vect_num 5
+#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num 6
+#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */
+#define USI_START_vect_num 7
+#define USI_START_vect _VECTOR(7) /* USI Start */
+#define USI_OVF_vect_num 8
+#define USI_OVF_vect _VECTOR(8) /* USI Overflow */
+#define EE_RDY_vect_num 9
+#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */
+#define ANA_COMP_vect_num 10
+#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */
+#define ADC_vect_num 11
+#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */
+#define WDT_vect_num 12
+#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */
+#define INT1_vect_num 13
+#define INT1_vect _VECTOR(13) /* External Interrupt 1 */
+#define TIMER0_COMPA_vect_num 14
+#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 15
+#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */
+#define TIMER0_CAPT_vect_num 16
+#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */
+#define TIMER1_COMPD_vect_num 17
+#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */
+#define FAULT_PROTECTION_vect_num 18
+#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART (0x60)
+#define RAMSIZE (256)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0xFF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0xFFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x92
+#define SIGNATURE_2 0x08
+
+
+/* Device Pin Definitions */
+#define DI_B_DDR DDRMOSI
+#define DI_B_PORT PORTMOSI
+#define DI_B_PIN PINMOSI
+#define DI_B_BIT MOSI
+
+#define SDA_B_DDR DDRMOSI
+#define SDA_B_PORT PORTMOSI
+#define SDA_B_PIN PINMOSI
+#define SDA_B_BIT MOSI
+
+#define _OC1A_DDR DDRMOSI
+#define _OC1A_PORT PORTMOSI
+#define _OC1A_PIN PINMOSI
+#define _OC1A_BIT MOSI
+
+#define PCINT8_DDR DDRMOSI
+#define PCINT8_PORT PORTMOSI
+#define PCINT8_PIN PINMOSI
+#define PCINT8_BIT MOSI
+
+#define PB0_DDR DDRMOSI
+#define PB0_PORT PORTMOSI
+#define PB0_PIN PINMOSI
+#define PB0_BIT MOSI
+
+#define DO_B_DDR DDRMISO
+#define DO_B_PORT PORTMISO
+#define DO_B_PIN PINMISO
+#define DO_B_BIT MISO
+
+#define OC1A_DDR DDRMISO
+#define OC1A_PORT PORTMISO
+#define OC1A_PIN PINMISO
+#define OC1A_BIT MISO
+
+#define PCINT9_DDR DDRMISO
+#define PCINT9_PORT PORTMISO
+#define PCINT9_PIN PINMISO
+#define PCINT9_BIT MISO
+
+#define PB1_DDR DDRMISO
+#define PB1_PORT PORTMISO
+#define PB1_PIN PINMISO
+#define PB1_BIT MISO
+
+#define USCK_B_DDR DDRSCK
+#define USCK_B_PORT PORTSCK
+#define USCK_B_PIN PINSCK
+#define USCK_B_BIT SCK
+
+#define SCL_B_DDR DDRSCK
+#define SCL_B_PORT PORTSCK
+#define SCL_B_PIN PINSCK
+#define SCL_B_BIT SCK
+
+#define OC1B_DDR DDRSCK
+#define OC1B_PORT PORTSCK
+#define OC1B_PIN PINSCK
+#define OC1B_BIT SCK
+
+#define PCINT10_DDR DDRSCK
+#define PCINT10_PORT PORTSCK
+#define PCINT10_PIN PINSCK
+#define PCINT10_BIT SCK
+
+#define PB2_DDR DDRSCK
+#define PB2_PORT PORTSCK
+#define PB2_PIN PINSCK
+#define PB2_BIT SCK
+
+#define PCINT11_DDR DDROC1B
+#define PCINT11_PORT PORTOC1B
+#define PCINT11_PIN PINOC1B
+#define PCINT11_BIT OC1B
+
+#define PB3_DDR DDROC1B
+#define PB3_PORT PORTOC1B
+#define PB3_PIN PINOC1B
+#define PB3_BIT OC1B
+
+#define PCINT12_DDR DDRADC
+#define PCINT12_PORT PORTADC
+#define PCINT12_PIN PINADC
+#define PCINT12_BIT ADC7
+
+#define _OC1D_DDR DDRADC
+#define _OC1D_PORT PORTADC
+#define _OC1D_PIN PINADC
+#define _OC1D_BIT ADC7
+
+#define CLKI_DDR DDRADC
+#define CLKI_PORT PORTADC
+#define CLKI_PIN PINADC
+#define CLKI_BIT ADC7
+
+#define PB4_DDR DDRADC
+#define PB4_PORT PORTADC
+#define PB4_PIN PINADC
+#define PB4_BIT ADC7
+
+#define PCINT13_DDR DDRADC
+#define PCINT13_PORT PORTADC
+#define PCINT13_PIN PINADC
+#define PCINT13_BIT ADC8
+
+#define OC1D_DDR DDRADC
+#define OC1D_PORT PORTADC
+#define OC1D_PIN PINADC
+#define OC1D_BIT ADC8
+
+#define CKLO_DDR DDRADC
+#define CKLO_PORT PORTADC
+#define CKLO_PIN PINADC
+#define CKLO_BIT ADC8
+
+#define PB5_DDR DDRADC
+#define PB5_PORT PORTADC
+#define PB5_PIN PINADC
+#define PB5_BIT ADC8
+
+#define INT0_DDR DDRADC
+#define INT0_PORT PORTADC
+#define INT0_PIN PINADC
+#define INT0_BIT ADC9
+
+#define T0_DDR DDRADC
+#define T0_PORT PORTADC
+#define T0_PIN PINADC
+#define T0_BIT ADC9
+
+#define PCINT14_DDR DDRADC
+#define PCINT14_PORT PORTADC
+#define PCINT14_PIN PINADC
+#define PCINT14_BIT ADC9
+
+#define PB6_DDR DDRADC
+#define PB6_PORT PORTADC
+#define PB6_PIN PINADC
+#define PB6_BIT ADC9
+
+#define PCINT15_DDR DDRADC1
+#define PCINT15_PORT PORTADC1
+#define PCINT15_PIN PINADC1
+#define PCINT15_BIT ADC10
+
+#define PB7_DDR DDRADC1
+#define PB7_PORT PORTADC1
+#define PB7_PIN PINADC1
+#define PB7_BIT ADC10
+
+#define AIN1_DDR DDRADC
+#define AIN1_PORT PORTADC
+#define AIN1_PIN PINADC
+#define AIN1_BIT ADC6
+
+#define PCINT7_DDR DDRADC
+#define PCINT7_PORT PORTADC
+#define PCINT7_PIN PINADC
+#define PCINT7_BIT ADC6
+
+#define PA7_DDR DDRADC
+#define PA7_PORT PORTADC
+#define PA7_PIN PINADC
+#define PA7_BIT ADC6
+
+#define AIN0_DDR DDRADC
+#define AIN0_PORT PORTADC
+#define AIN0_PIN PINADC
+#define AIN0_BIT ADC5
+
+#define PCINT6_DDR DDRADC
+#define PCINT6_PORT PORTADC
+#define PCINT6_PIN PINADC
+#define PCINT6_BIT ADC5
+
+#define PA6_DDR DDRADC
+#define PA6_PORT PORTADC
+#define PA6_PIN PINADC
+#define PA6_BIT ADC5
+
+#define AIN2_DDR DDRADC
+#define AIN2_PORT PORTADC
+#define AIN2_PIN PINADC
+#define AIN2_BIT ADC4
+
+#define PCINT5_DDR DDRADC
+#define PCINT5_PORT PORTADC
+#define PCINT5_PIN PINADC
+#define PCINT5_BIT ADC4
+
+#define PA5_DDR DDRADC
+#define PA5_PORT PORTADC
+#define PA5_PIN PINADC
+#define PA5_BIT ADC4
+
+#define ICP0_DDR DDRADC
+#define ICP0_PORT PORTADC
+#define ICP0_PIN PINADC
+#define ICP0_BIT ADC3
+
+#define PCINT4_DDR DDRADC
+#define PCINT4_PORT PORTADC
+#define PCINT4_PIN PINADC
+#define PCINT4_BIT ADC3
+
+#define PA4_DDR DDRADC
+#define PA4_PORT PORTADC
+#define PA4_PIN PINADC
+#define PA4_BIT ADC3
+
+#define PCINT3_DDR DDRAREF
+#define PCINT3_PORT PORTAREF
+#define PCINT3_PIN PINAREF
+#define PCINT3_BIT AREF
+
+#define PA3_DDR DDRAREF
+#define PA3_PORT PORTAREF
+#define PA3_PIN PINAREF
+#define PA3_BIT AREF
+
+#define INT1_DDR DDRADC
+#define INT1_PORT PORTADC
+#define INT1_PIN PINADC
+#define INT1_BIT ADC2
+
+#define USCK_A_DDR DDRADC
+#define USCK_A_PORT PORTADC
+#define USCK_A_PIN PINADC
+#define USCK_A_BIT ADC2
+
+#define SCL_A_DDR DDRADC
+#define SCL_A_PORT PORTADC
+#define SCL_A_PIN PINADC
+#define SCL_A_BIT ADC2
+
+#define PCINT2_DDR DDRADC
+#define PCINT2_PORT PORTADC
+#define PCINT2_PIN PINADC
+#define PCINT2_BIT ADC2
+
+#define PA2_DDR DDRADC
+#define PA2_PORT PORTADC
+#define PA2_PIN PINADC
+#define PA2_BIT ADC2
+
+#define DO_A_DDR DDRADC
+#define DO_A_PORT PORTADC
+#define DO_A_PIN PINADC
+#define DO_A_BIT ADC1
+
+#define PCINT1_DDR DDRADC
+#define PCINT1_PORT PORTADC
+#define PCINT1_PIN PINADC
+#define PCINT1_BIT ADC1
+
+#define PA1_DDR DDRADC
+#define PA1_PORT PORTADC
+#define PA1_PIN PINADC
+#define PA1_BIT ADC1
+
+#define DI_A_DDR DDRADC
+#define DI_A_PORT PORTADC
+#define DI_A_PIN PINADC
+#define DI_A_BIT ADC0
+
+#define SDA_A_DDR DDRADC
+#define SDA_A_PORT PORTADC
+#define SDA_A_PIN PINADC
+#define SDA_A_BIT ADC0
+
+#define PCINT0_DDR DDRADC
+#define PCINT0_PORT PORTADC
+#define PCINT0_PIN PINADC
+#define PCINT0_BIT ADC0
+
+#define PA0_DDR DDRADC
+#define PA0_PORT PORTADC
+#define PA0_PIN PINADC
+#define PA0_BIT ADC0
+
+#endif /* _AVR_ATtiny461A_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iotn48.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn48.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn48.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn48.h Mon May 10 11:31:23 2010
@@ -26,12 +26,12 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
-/* avr/iotn48.h - definitions for ATtiny43U */
+/* avr/iotn48.h - definitions for ATtiny48 */
/* This file should only be included from <avr/io.h>, never directly. */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iotn48.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOTN48_H_
@@ -737,7 +737,7 @@
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iotn861a.h:1.1
--- /dev/null Mon May 10 12:11:00 2010
+++ rtems/cpukit/score/cpu/avr/avr/iotn861a.h Mon May 10 11:31:23 2010
@@ -0,0 +1,976 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iotn861a.h - definitions for ATtiny861A */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iotn861a.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATtiny861A_H_
+#define _AVR_ATtiny861A_H_ 1
+
+
+/* Registers and associated bit numbers. */
+
+#define TCCR1E _SFR_IO8(0x00)
+#define OC1OE0 0
+#define OC1OE1 1
+#define OC1OE2 2
+#define OC1OE3 3
+#define OC1OE4 4
+#define OC1OE5 5
+
+#define DIDR0 _SFR_IO8(0x01)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define AREFD 3
+#define ADC3D 4
+#define ADC4D 5
+#define ADC5D 6
+#define ADC6D 7
+
+#define DIDR1 _SFR_IO8(0x02)
+#define ADC7D 4
+#define ADC8D 5
+#define ADC9D 6
+#define ADC10D 7
+
+#define ADCSRB _SFR_IO8(0x03)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define MUX5 3
+#define REFS2 4
+#define IPR 5
+#define GSEL 6
+#define BIN 7
+
+#ifndef __ASSEMBLER__
+#define ADC _SFR_IO16(0x04)
+#endif
+#define ADCW _SFR_IO16(0x04)
+
+#define ADCL _SFR_IO8(0x04)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_IO8(0x05)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_IO8(0x06)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADMUX _SFR_IO8(0x07)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define ACSRA _SFR_IO8(0x08)
+#define ACIS0 0
+#define ACIS1 1
+#define ACME 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define ACSRB _SFR_IO8(0x09)
+#define ACM0 0
+#define ACM1 1
+#define ACM2 2
+#define HLEV 6
+#define HSEL 7
+
+#define GPIOR0 _SFR_IO8(0x0A)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1 _SFR_IO8(0x0B)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x0C)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define USICR _SFR_IO8(0x0D)
+#define USITC 0
+#define USICLK 1
+#define USICS0 2
+#define USICS1 3
+#define USIWM0 4
+#define USIWM1 5
+#define USIOIE 6
+#define USISIE 7
+
+#define USISR _SFR_IO8(0x0E)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC 4
+#define USIPF 5
+#define USIOIF 6
+#define USISIF 7
+
+#define USIDR _SFR_IO8(0x0F)
+#define USIDR0 0
+#define USIDR1 1
+#define USIDR2 2
+#define USIDR3 3
+#define USIDR4 4
+#define USIDR5 5
+#define USIDR6 6
+#define USIDR7 7
+
+#define USIBR _SFR_IO8(0x10)
+#define USIBR0 0
+#define USIBR1 1
+#define USIBR2 2
+#define USIBR3 3
+#define USIBR4 4
+#define USIBR5 5
+#define USIBR6 6
+#define USIBR7 7
+
+#define USIPP _SFR_IO8(0x11)
+#define USIPOS 0
+
+#define OCR0B _SFR_IO8(0x12)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define OCR0A _SFR_IO8(0x13)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define TCNT0H _SFR_IO8(0x14)
+#define TCNT0H_0 0
+#define TCNT0H_1 1
+#define TCNT0H_2 2
+#define TCNT0H_3 3
+#define TCNT0H_4 4
+#define TCNT0H_5 5
+#define TCNT0H_6 6
+#define TCNT0H_7 7
+
+#define TCCR0A _SFR_IO8(0x15)
+#define WGM00 0
+#define ACIC0 3
+#define ICES0 4
+#define ICNC0 5
+#define ICEN0 6
+#define TCW0 7
+
+#define PINB _SFR_IO8(0x16)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x17)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x18)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINA _SFR_IO8(0x19)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x1A)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x1B)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define EECR _SFR_IO8(0x1C)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x1D)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x1E)
+
+#define EEARL _SFR_IO8(0x1E)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x1F)
+#define EEAR8 0
+
+#define DWDR _SFR_IO8(0x20)
+#define DWDR0 0
+#define DWDR1 1
+#define DWDR2 2
+#define DWDR3 3
+#define DWDR4 4
+#define DWDR5 5
+#define DWDR6 6
+#define DWDR7 7
+
+#define WDTCR _SFR_IO8(0x21)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define PCMSK1 _SFR_IO8(0x22)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK0 _SFR_IO8(0x23)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define DT1 _SFR_IO8(0x24)
+#define DT1L0 0
+#define DT1L1 1
+#define DT1L2 2
+#define DT1L3 3
+#define DT1H0 4
+#define DT1H1 5
+#define DT1H2 6
+#define DT1H3 7
+
+#define TC1H _SFR_IO8(0x25)
+#define TC18 0
+#define TC19 1
+
+#define TCCR1D _SFR_IO8(0x26)
+#define WGM10 0
+#define WGM11 1
+#define FPF1 2
+#define FPAC1 3
+#define FPES1 4
+#define FPNC1 5
+#define FPEN1 6
+#define FPIE1 7
+
+#define TCCR1C _SFR_IO8(0x27)
+#define PWM1D 0
+#define FOC1D 1
+#define COM1D0 2
+#define COM1D1 3
+#define COM1B0S 4
+#define COM1B1S 5
+#define COM1A0S 6
+#define COM1A1S 7
+
+#define CLKPR _SFR_IO8(0x28)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PLLCSR _SFR_IO8(0x29)
+#define PLOCK 0
+#define PLLE 1
+#define PCKE 2
+#define LSM 7
+
+#define OCR1D _SFR_IO8(0x2A)
+#define OCR1D0 0
+#define OCR1D1 1
+#define OCR1D2 2
+#define OCR1D3 3
+#define OCR1D4 4
+#define OCR1D5 5
+#define OCR1D6 6
+#define OCR1D7 7
+
+#define OCR1C _SFR_IO8(0x2B)
+#define OCR1C0 0
+#define OCR1C1 1
+#define OCR1C2 2
+#define OCR1C3 3
+#define OCR1C4 4
+#define OCR1C5 5
+#define OCR1C6 6
+#define OCR1C7 7
+
+#define OCR1B _SFR_IO8(0x2C)
+#define OCR1B0 0
+#define OCR1B1 1
+#define OCR1B2 2
+#define OCR1B3 3
+#define OCR1B4 4
+#define OCR1B5 5
+#define OCR1B6 6
+#define OCR1B7 7
+
+#define OCR1A _SFR_IO8(0x2D)
+#define OCR1A0 0
+#define OCR1A1 1
+#define OCR1A2 2
+#define OCR1A3 3
+#define OCR1A4 4
+#define OCR1A5 5
+#define OCR1A6 6
+#define OCR1A7 7
+
+#define TCNT1 _SFR_IO8(0x2E)
+#define TC1H_0 0
+#define TC1H_1 1
+#define TC1H_2 2
+#define TC1H_3 3
+#define TC1H_4 4
+#define TC1H_5 5
+#define TC1H_6 6
+#define TC1H_7 7
+
+#define TCCR1B _SFR_IO8(0x2F)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define CS13 3
+#define DTPS10 4
+#define DTPS11 5
+#define PSR1 6
+
+#define TCCR1A _SFR_IO8(0x30)
+#define PWM1B 0
+#define PWM1A 1
+#define FOC1B 2
+#define FOC1A 3
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define OSCCAL _SFR_IO8(0x31)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define TCNT0L _SFR_IO8(0x32)
+#define TCNT0L_0 0
+#define TCNT0L_1 1
+#define TCNT0L_2 2
+#define TCNT0L_3 3
+#define TCNT0L_4 4
+#define TCNT0L_5 5
+#define TCNT0L_6 6
+#define TCNT0L_7 7
+
+#define TCCR0B _SFR_IO8(0x33)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define PSR0 3
+#define TSM 4
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+
+#define MCUCR _SFR_IO8(0x35)
+#define ISC00 0
+#define ISC01 1
+#define BODSE 2
+#define SM0 3
+#define SM1 4
+#define SE 5
+#define PUD 6
+#define BODS 7
+
+#define PRR _SFR_IO8(0x36)
+#define PRADC 0
+#define PRUSI 1
+#define PRTIM0 2
+#define PRTIM1 3
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define RFLB 3
+#define CTPB 4
+
+#define TIFR _SFR_IO8(0x38)
+#define ICF0 0
+#define TOV0 1
+#define TOV1 2
+#define OCF0B 3
+#define OCF0A 4
+#define OCF1B 5
+#define OCF1A 6
+#define OCF1D 7
+
+#define TIMSK _SFR_IO8(0x39)
+#define TICIE0 0
+#define TOIE0 1
+#define TOIE1 2
+#define OCIE0B 3
+#define OCIE0A 4
+#define OCIE1B 5
+#define OCIE1A 6
+#define OCIE1D 7
+
+#define GIFR _SFR_IO8(0x3A)
+#define PCIF 5
+#define INTF0 6
+#define INTF1 7
+
+#define GIMSK _SFR_IO8(0x3B)
+#define PCIE0 4
+#define PCIE1 5
+#define INT0 6
+#define INT1 7
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+#define INT0_vect_num 1
+#define INT0_vect _VECTOR(1) /* External Interrupt 0 */
+#define PCINT_vect_num 2
+#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */
+#define TIMER1_COMPA_vect_num 3
+#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPB_vect_num 4
+#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */
+#define TIMER1_OVF_vect_num 5
+#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */
+#define TIMER0_OVF_vect_num 6
+#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */
+#define USI_START_vect_num 7
+#define USI_START_vect _VECTOR(7) /* USI Start */
+#define USI_OVF_vect_num 8
+#define USI_OVF_vect _VECTOR(8) /* USI Overflow */
+#define EE_RDY_vect_num 9
+#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */
+#define ANA_COMP_vect_num 10
+#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */
+#define ADC_vect_num 11
+#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */
+#define WDT_vect_num 12
+#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */
+#define INT1_vect_num 13
+#define INT1_vect _VECTOR(13) /* External Interrupt 1 */
+#define TIMER0_COMPA_vect_num 14
+#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect_num 15
+#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */
+#define TIMER0_CAPT_vect_num 16
+#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */
+#define TIMER1_COMPD_vect_num 17
+#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */
+#define FAULT_PROTECTION_vect_num 18
+#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */
+
+#define _VECTOR_SIZE 2 /* Size of individual vector. */
+#define _VECTORS_SIZE (19 * _VECTOR_SIZE)
+
+
+/* Constants */
+#define SPM_PAGESIZE (64)
+#define RAMSTART (0x60)
+#define RAMSIZE (512)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+#define XRAMSTART (NA)
+#define XRAMSIZE (0)
+#define XRAMEND (RAMEND)
+#define E2END (0x1FF)
+#define E2PAGESIZE (4)
+#define FLASHEND (0x1FFF)
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */
+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */
+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */
+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */
+#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */
+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */
+#define HFUSE_DEFAULT (FUSE_SPIEN)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x0D
+
+
+/* Device Pin Definitions */
+#define DI_B_DDR DDRMOSI
+#define DI_B_PORT PORTMOSI
+#define DI_B_PIN PINMOSI
+#define DI_B_BIT MOSI
+
+#define SDA_B_DDR DDRMOSI
+#define SDA_B_PORT PORTMOSI
+#define SDA_B_PIN PINMOSI
+#define SDA_B_BIT MOSI
+
+#define _OC1A_DDR DDRMOSI
+#define _OC1A_PORT PORTMOSI
+#define _OC1A_PIN PINMOSI
+#define _OC1A_BIT MOSI
+
+#define PCINT8_DDR DDRMOSI
+#define PCINT8_PORT PORTMOSI
+#define PCINT8_PIN PINMOSI
+#define PCINT8_BIT MOSI
+
+#define PB0_DDR DDRMOSI
+#define PB0_PORT PORTMOSI
+#define PB0_PIN PINMOSI
+#define PB0_BIT MOSI
+
+#define DO_B_DDR DDRMISO
+#define DO_B_PORT PORTMISO
+#define DO_B_PIN PINMISO
+#define DO_B_BIT MISO
+
+#define OC1A_DDR DDRMISO
+#define OC1A_PORT PORTMISO
+#define OC1A_PIN PINMISO
+#define OC1A_BIT MISO
+
+#define PCINT9_DDR DDRMISO
+#define PCINT9_PORT PORTMISO
+#define PCINT9_PIN PINMISO
+#define PCINT9_BIT MISO
+
+#define PB1_DDR DDRMISO
+#define PB1_PORT PORTMISO
+#define PB1_PIN PINMISO
+#define PB1_BIT MISO
+
+#define USCK_B_DDR DDRSCK
+#define USCK_B_PORT PORTSCK
+#define USCK_B_PIN PINSCK
+#define USCK_B_BIT SCK
+
+#define SCL_B_DDR DDRSCK
+#define SCL_B_PORT PORTSCK
+#define SCL_B_PIN PINSCK
+#define SCL_B_BIT SCK
+
+#define OC1B_DDR DDRSCK
+#define OC1B_PORT PORTSCK
+#define OC1B_PIN PINSCK
+#define OC1B_BIT SCK
+
+#define PCINT10_DDR DDRSCK
+#define PCINT10_PORT PORTSCK
+#define PCINT10_PIN PINSCK
+#define PCINT10_BIT SCK
+
+#define PB2_DDR DDRSCK
+#define PB2_PORT PORTSCK
+#define PB2_PIN PINSCK
+#define PB2_BIT SCK
+
+#define PCINT11_DDR DDROC1B
+#define PCINT11_PORT PORTOC1B
+#define PCINT11_PIN PINOC1B
+#define PCINT11_BIT OC1B
+
+#define PB3_DDR DDROC1B
+#define PB3_PORT PORTOC1B
+#define PB3_PIN PINOC1B
+#define PB3_BIT OC1B
+
+#define PCINT12_DDR DDRADC
+#define PCINT12_PORT PORTADC
+#define PCINT12_PIN PINADC
+#define PCINT12_BIT ADC7
+
+#define _OC1D_DDR DDRADC
+#define _OC1D_PORT PORTADC
+#define _OC1D_PIN PINADC
+#define _OC1D_BIT ADC7
+
+#define CLKI_DDR DDRADC
+#define CLKI_PORT PORTADC
+#define CLKI_PIN PINADC
+#define CLKI_BIT ADC7
+
+#define PB4_DDR DDRADC
+#define PB4_PORT PORTADC
+#define PB4_PIN PINADC
+#define PB4_BIT ADC7
+
+#define PCINT13_DDR DDRADC
+#define PCINT13_PORT PORTADC
+#define PCINT13_PIN PINADC
+#define PCINT13_BIT ADC8
+
+#define OC1D_DDR DDRADC
+#define OC1D_PORT PORTADC
+#define OC1D_PIN PINADC
+#define OC1D_BIT ADC8
+
+#define CKLO_DDR DDRADC
+#define CKLO_PORT PORTADC
+#define CKLO_PIN PINADC
+#define CKLO_BIT ADC8
+
+#define PB5_DDR DDRADC
+#define PB5_PORT PORTADC
+#define PB5_PIN PINADC
+#define PB5_BIT ADC8
+
+#define INT0_DDR DDRADC
+#define INT0_PORT PORTADC
+#define INT0_PIN PINADC
+#define INT0_BIT ADC9
+
+#define T0_DDR DDRADC
+#define T0_PORT PORTADC
+#define T0_PIN PINADC
+#define T0_BIT ADC9
+
+#define PCINT14_DDR DDRADC
+#define PCINT14_PORT PORTADC
+#define PCINT14_PIN PINADC
+#define PCINT14_BIT ADC9
+
+#define PB6_DDR DDRADC
+#define PB6_PORT PORTADC
+#define PB6_PIN PINADC
+#define PB6_BIT ADC9
+
+#define PCINT15_DDR DDRADC1
+#define PCINT15_PORT PORTADC1
+#define PCINT15_PIN PINADC1
+#define PCINT15_BIT ADC10
+
+#define PB7_DDR DDRADC1
+#define PB7_PORT PORTADC1
+#define PB7_PIN PINADC1
+#define PB7_BIT ADC10
+
+#define AIN1_DDR DDRADC
+#define AIN1_PORT PORTADC
+#define AIN1_PIN PINADC
+#define AIN1_BIT ADC6
+
+#define PCINT7_DDR DDRADC
+#define PCINT7_PORT PORTADC
+#define PCINT7_PIN PINADC
+#define PCINT7_BIT ADC6
+
+#define PA7_DDR DDRADC
+#define PA7_PORT PORTADC
+#define PA7_PIN PINADC
+#define PA7_BIT ADC6
+
+#define AIN0_DDR DDRADC
+#define AIN0_PORT PORTADC
+#define AIN0_PIN PINADC
+#define AIN0_BIT ADC5
+
+#define PCINT6_DDR DDRADC
+#define PCINT6_PORT PORTADC
+#define PCINT6_PIN PINADC
+#define PCINT6_BIT ADC5
+
+#define PA6_DDR DDRADC
+#define PA6_PORT PORTADC
+#define PA6_PIN PINADC
+#define PA6_BIT ADC5
+
+#define AIN2_DDR DDRADC
+#define AIN2_PORT PORTADC
+#define AIN2_PIN PINADC
+#define AIN2_BIT ADC4
+
+#define PCINT5_DDR DDRADC
+#define PCINT5_PORT PORTADC
+#define PCINT5_PIN PINADC
+#define PCINT5_BIT ADC4
+
+#define PA5_DDR DDRADC
+#define PA5_PORT PORTADC
+#define PA5_PIN PINADC
+#define PA5_BIT ADC4
+
+#define ICP0_DDR DDRADC
+#define ICP0_PORT PORTADC
+#define ICP0_PIN PINADC
+#define ICP0_BIT ADC3
+
+#define PCINT4_DDR DDRADC
+#define PCINT4_PORT PORTADC
+#define PCINT4_PIN PINADC
+#define PCINT4_BIT ADC3
+
+#define PA4_DDR DDRADC
+#define PA4_PORT PORTADC
+#define PA4_PIN PINADC
+#define PA4_BIT ADC3
+
+#define PCINT3_DDR DDRAREF
+#define PCINT3_PORT PORTAREF
+#define PCINT3_PIN PINAREF
+#define PCINT3_BIT AREF
+
+#define PA3_DDR DDRAREF
+#define PA3_PORT PORTAREF
+#define PA3_PIN PINAREF
+#define PA3_BIT AREF
+
+#define INT1_DDR DDRADC
+#define INT1_PORT PORTADC
+#define INT1_PIN PINADC
+#define INT1_BIT ADC2
+
+#define USCK_A_DDR DDRADC
+#define USCK_A_PORT PORTADC
+#define USCK_A_PIN PINADC
+#define USCK_A_BIT ADC2
+
+#define SCL_A_DDR DDRADC
+#define SCL_A_PORT PORTADC
+#define SCL_A_PIN PINADC
+#define SCL_A_BIT ADC2
+
+#define PCINT2_DDR DDRADC
+#define PCINT2_PORT PORTADC
+#define PCINT2_PIN PINADC
+#define PCINT2_BIT ADC2
+
+#define PA2_DDR DDRADC
+#define PA2_PORT PORTADC
+#define PA2_PIN PINADC
+#define PA2_BIT ADC2
+
+#define DO_A_DDR DDRADC
+#define DO_A_PORT PORTADC
+#define DO_A_PIN PINADC
+#define DO_A_BIT ADC1
+
+#define PCINT1_DDR DDRADC
+#define PCINT1_PORT PORTADC
+#define PCINT1_PIN PINADC
+#define PCINT1_BIT ADC1
+
+#define PA1_DDR DDRADC
+#define PA1_PORT PORTADC
+#define PA1_PIN PINADC
+#define PA1_BIT ADC1
+
+#define DI_A_DDR DDRADC
+#define DI_A_PORT PORTADC
+#define DI_A_PIN PINADC
+#define DI_A_BIT ADC0
+
+#define SDA_A_DDR DDRADC
+#define SDA_A_PORT PORTADC
+#define SDA_A_PIN PINADC
+#define SDA_A_BIT ADC0
+
+#define PCINT0_DDR DDRADC
+#define PCINT0_PORT PORTADC
+#define PCINT0_PIN PINADC
+#define PCINT0_BIT ADC0
+
+#define PA0_DDR DDRADC
+#define PA0_PORT PORTADC
+#define PA0_PIN PINADC
+#define PA0_BIT ADC0
+
+#endif /* _AVR_ATtiny861A_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iotn87.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn87.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn87.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn87.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iotn87.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATtiny87_H_
diff -u rtems/cpukit/score/cpu/avr/avr/iotn88.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotn88.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotn88.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotn88.h Mon May 10 11:31:23 2010
@@ -26,7 +26,7 @@
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
+ POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id$ */
@@ -43,7 +43,7 @@
# define _AVR_IOXXX_H_ "iotn88.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOTN88_H_
@@ -737,7 +737,7 @@
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
+#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_SELFPRGEN ~_BV(0) /* Self Programming Enable */
diff -u rtems/cpukit/score/cpu/avr/avr/iotnx4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotnx4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotnx4.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotnx4.h Mon May 10 11:31:23 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotnx4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -62,7 +62,7 @@
#define ADC4D 4
#define ADC3D 3
#define ADC2D 2
-#define ADC1D 1
+#define ADC1D 1
#define ADC0D 0
/* Reserved [0x02] */
@@ -137,7 +137,7 @@
#define USITC 0
#define USISR _SFR_IO8(0x0E)
-#define USISIF 7
+#define USISIF 7
#define USIOIF 6
#define USIPF 5
#define USIDC 4
diff -u rtems/cpukit/score/cpu/avr/avr/iotnx5.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotnx5.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotnx5.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotnx5.h Mon May 10 11:31:23 2010
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iotnx5.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* I/O registers */
@@ -108,7 +108,7 @@
#define USITC 0
#define USISR _SFR_IO8(0x0E)
-#define USISIF 7
+#define USISIF 7
#define USIOIF 6
#define USIPF 5
#define USIDC 4
@@ -129,7 +129,7 @@
#define ADC2D 4
#define ADC3D 3
#define ADC1D 2
-#define AIN1D 1
+#define AIN1D 1
#define AIN0D 0
#define PCMSK _SFR_IO8(0x15)
diff -u rtems/cpukit/score/cpu/avr/avr/iotnx61.h:1.2 rtems/cpukit/score/cpu/avr/avr/iotnx61.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iotnx61.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iotnx61.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iotnx61.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_IOTNx61_H_
#define _AVR_IOTNx61_H_ 1
diff -u rtems/cpukit/score/cpu/avr/avr/iousb1286.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousb1286.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousb1286.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousb1286.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2006 Anatoly Sokolov
+/* Copyright (c) 2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iousb1287.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousb1287.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousb1287.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousb1287.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2006 Anatoly Sokolov
+/* Copyright (c) 2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iousb162.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousb162.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousb162.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousb162.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2007 Anatoly Sokolov
+/* Copyright (c) 2007 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iousb646.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousb646.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousb646.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousb646.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2006 Anatoly Sokolov
+/* Copyright (c) 2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iousb647.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousb647.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousb647.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousb647.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2006 Anatoly Sokolov
+/* Copyright (c) 2006 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
diff -u rtems/cpukit/score/cpu/avr/avr/iousb82.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousb82.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousb82.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousb82.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2007 Anatoly Sokolov
+/* Copyright (c) 2007 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -82,7 +82,7 @@
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
#endif /* _AVR_AT90USB82_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/iousbxx2.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousbxx2.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousbxx2.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousbxx2.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2007 Anatoly Sokolov
+/* Copyright (c) 2007 Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,7 @@
# define _AVR_IOXXX_H_ "iousbxx2.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
/* Registers and associated bit numbers */
@@ -175,7 +175,7 @@
#define INT4 4
#define INT3 3
#define INT2 2
-#define INT1 1
+#define INT1 1
#define INT0 0
#define GPIOR0 _SFR_IO8(0x1E)
diff -u rtems/cpukit/score/cpu/avr/avr/iousbxx6_7.h:1.2 rtems/cpukit/score/cpu/avr/avr/iousbxx6_7.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iousbxx6_7.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iousbxx6_7.h Mon May 10 11:31:23 2010
@@ -1,4 +1,4 @@
-/* Copyright (c) 2006, Anatoly Sokolov
+/* Copyright (c) 2006, Anatoly Sokolov
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,7 @@
/* $Id$ */
-/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286
+/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286
and AT90USB1287 */
#ifndef _AVR_IOUSBXX6_7_H_
@@ -46,7 +46,7 @@
# define _AVR_IOXXX_H_ "iousbxx6_7.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
# define __AT90USBxx6__ 1
@@ -284,7 +284,7 @@
#define INT4 4
#define INT3 3
#define INT2 2
-#define INT1 1
+#define INT1 1
#define INT0 0
#define GPIOR0 _SFR_IO8(0x1E)
diff -u rtems/cpukit/score/cpu/avr/avr/iox128a1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox128a1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox128a1.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox128a1.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox128a1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega128A1_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6625,21 +6625,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -7076,50 +7076,50 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0 ~_BV(0) /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1 ~_BV(1) /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2 ~_BV(2) /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3 ~_BV(3) /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4 ~_BV(4) /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5 ~_BV(5) /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6 ~_BV(6) /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7 ~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BODACT0 ~_BV(2) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(3) /* BOD Operation in Active Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_JTAGEN ~_BV(0) /* JTAG Interface Enable */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
#define FUSE5_DEFAULT (0xFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iox128a3.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox128a3.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox128a3.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox128a3.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox128a3.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega128A3_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6438,21 +6438,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -6826,50 +6826,50 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0 ~_BV(0) /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1 ~_BV(1) /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2 ~_BV(2) /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3 ~_BV(3) /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4 ~_BV(4) /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5 ~_BV(5) /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6 ~_BV(6) /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7 ~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_JTAGEN ~_BV(0) /* JTAG Interface Enable */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iox128d3.h:1.1
--- /dev/null Mon May 10 12:11:01 2010
+++ rtems/cpukit/score/cpu/avr/avr/iox128d3.h Mon May 10 11:31:23 2010
@@ -0,0 +1,5646 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iox128d3.h - definitions for ATxmega128D3 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iox128d3.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATxmega128D3_H_
+#define _AVR_ATxmega128D3_H_ 1
+
+
+/* Ungrouped common registers */
+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+#define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register16_t regname; \
+ struct \
+ { \
+ register8_t regname ## L; \
+ register8_t regname ## H; \
+ }; \
+ }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register32_t regname; \
+ struct \
+ { \
+ register8_t regname ## 0; \
+ register8_t regname ## 1; \
+ register8_t regname ## 2; \
+ register8_t regname ## 3; \
+ }; \
+ }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+ register8_t OCDR0; /* OCD Register 0 */
+ register8_t OCDR1; /* OCD Register 1 */
+} OCD_t;
+
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
+} CCP_t;
+
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t PSCTRL; /* Prescaler Control Register */
+ register8_t LOCK; /* Lock register */
+ register8_t RTCCTRL; /* RTC Control Register */
+} CLK_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+ register8_t PRGEN; /* General Power Reduction */
+ register8_t PRPA; /* Power Reduction Port A */
+ register8_t PRPB; /* Power Reduction Port B */
+ register8_t PRPC; /* Power Reduction Port C */
+ register8_t PRPD; /* Power Reduction Port D */
+ register8_t PRPE; /* Power Reduction Port E */
+ register8_t PRPF; /* Power Reduction Port F */
+} PR_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
+} CLK_RTCSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+ register8_t CTRL; /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
+ register8_t PLLCTRL; /* PLL Control REgister */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+} OSC_PLLSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t CALA; /* Calibration Register A */
+ register8_t CALB; /* Calibration Register B */
+ register8_t COMP0; /* Oscillator Compare Register 0 */
+ register8_t COMP1; /* Oscillator Compare Register 1 */
+ register8_t COMP2; /* Oscillator Compare Register 2 */
+ register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t CTRL; /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t WINCTRL; /* Windowed Mode Control */
+ register8_t STATUS; /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+ register8_t DEVID0; /* Device ID byte 0 */
+ register8_t DEVID1; /* Device ID byte 1 */
+ register8_t DEVID2; /* Device ID byte 2 */
+ register8_t REVID; /* Revision ID */
+ register8_t JTAGUID; /* JTAG User ID */
+ register8_t reserved_0x05;
+ register8_t MCUCR; /* MCU Control */
+ register8_t reserved_0x07;
+ register8_t EVSYSLOCK; /* Event System Lock */
+ register8_t AWEXLOCK; /* AWEX Lock */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t INTPRI; /* Interrupt Priority */
+ register8_t CTRL; /* Control Register */
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
+ register8_t CH0CTRL; /* Channel 0 Control Register */
+ register8_t CH1CTRL; /* Channel 1 Control Register */
+ register8_t CH2CTRL; /* Channel 2 Control Register */
+ register8_t CH3CTRL; /* Channel 3 Control Register */
+ register8_t STROBE; /* Event Strobe */
+ register8_t DATA; /* Event Data */
+} EVSYS_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+ register8_t ADDR0; /* Address Register 0 */
+ register8_t ADDR1; /* Address Register 1 */
+ register8_t ADDR2; /* Address Register 2 */
+ register8_t reserved_0x03;
+ register8_t DATA0; /* Data Register 0 */
+ register8_t DATA1; /* Data Register 1 */
+ register8_t DATA2; /* Data Register 2 */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t CMD; /* Command */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t INTCTRL; /* Interrupt Control */
+ register8_t reserved_0x0E;
+ register8_t STATUS; /* Status */
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_LOCKBITS_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+ register8_t FUSEBYTE0; /* User ID */
+ register8_t FUSEBYTE1; /* Watchdog Configuration */
+ register8_t FUSEBYTE2; /* Reset Configuration */
+ register8_t reserved_0x03;
+ register8_t FUSEBYTE4; /* Start-up Configuration */
+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
+ register8_t reserved_0x01;
+ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
+ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
+ register8_t reserved_0x04;
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t WAFNUM; /* Wafer Number */
+ register8_t reserved_0x11;
+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
+ register8_t reserved_0x26;
+ register8_t reserved_0x27;
+ register8_t reserved_0x28;
+ register8_t reserved_0x29;
+ register8_t reserved_0x2A;
+ register8_t reserved_0x2B;
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
+ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
+ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ register8_t reserved_0x36;
+ register8_t reserved_0x37;
+ register8_t reserved_0x38;
+ register8_t reserved_0x39;
+ register8_t reserved_0x3A;
+ register8_t reserved_0x3B;
+ register8_t reserved_0x3C;
+ register8_t reserved_0x3D;
+ register8_t reserved_0x3E;
+} NVM_PROD_SIGNATURES_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
+} NVM_CMD_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
+} NVM_SPMLVL_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
+} NVM_EELVL_t;
+
+/* Boot lock bits - boot setcion */
+typedef enum NVM_BLBB_enum
+{
+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
+} NVM_BLBB_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
+} NVM_BLBAT_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
+} NVM_LB_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
+} BOOTRST_t;
+
+/* BOD operation */
+typedef enum BOD_enum
+{
+ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
+ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
+} BOD_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WD_enum
+{
+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
+} WD_t;
+
+/* Start-up Time */
+typedef enum SUT_enum
+{
+ SUT_0MS_gc = (0x03<<2), /* 0 ms */
+ SUT_4MS_gc = (0x01<<2), /* 4 ms */
+ SUT_64MS_gc = (0x00<<2), /* 64 ms */
+} SUT_t;
+
+/* Brown Out Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
+ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */
+ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */
+ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */
+ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */
+ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */
+ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */
+} BODLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+ register8_t AC0CTRL; /* Comparator 0 Control */
+ register8_t AC1CTRL; /* Comparator 1 Control */
+ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
+ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t WINCTRL; /* Window Mode Control */
+ register8_t STATUS; /* Status */
+} AC_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
+} AC_INTLVL_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
+} AC_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
+} AC_WINTLVL_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
+} AC_WSTATE_t;
+
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+ register8_t INTCTRL; /* Channel Interrupt Control */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+ register8_t reserved_0x6;
+ register8_t reserved_0x7;
+} ADC_CH_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t REFCTRL; /* Reference Control */
+ register8_t EVCTRL; /* Event Control */
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t CALCTRL; /* Calibration Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ _WORDREGISTER(CAL); /* Calibration Value */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ _WORDREGISTER(CH0RES); /* Channel 0 Result */
+ _WORDREGISTER(CMP); /* Compare Value */
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ ADC_CH_t CH0; /* ADC Channel 0 */
+} ADC_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
+} ADC_CH_MUXPOS_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
+ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
+ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
+ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
+ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
+} ADC_CH_MUXNEG_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+} ADC_CH_GAIN_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
+ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
+} ADC_REFSEL_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
+} ADC_SWEEP_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
+} ADC_EVACT_t;
+
+/* Interupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
+} ADC_CH_INTLVL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Clounter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ _WORDREGISTER(CNT); /* Count Register */
+ _WORDREGISTER(PER); /* Period Register */
+ _WORDREGISTER(COMP); /* Compare Register */
+} RTC_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} RTC_OVFINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+ register8_t CTRLA; /* Chip Select Control Register A */
+ register8_t CTRLB; /* Chip Select Control Register B */
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+} EBI_CS_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t SDRAMCTRLA; /* SDRAM Control Register A */
+ register8_t reserved_0x02;
+ register8_t reserved_0x03;
+ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
+ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
+ register8_t SDRAMCTRLB; /* SDRAM Control Register B */
+ register8_t SDRAMCTRLC; /* SDRAM Control Register C */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ EBI_CS_t CS0; /* Chip Select 0 */
+ EBI_CS_t CS1; /* Chip Select 1 */
+ EBI_CS_t CS2; /* Chip Select 2 */
+ EBI_CS_t CS3; /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select adress space */
+typedef enum EBI_CS_ASPACE_enum
+{
+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* */
+typedef enum EBI_CS_SRWS_enum
+{
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
+ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
+ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
+ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
+ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* */
+typedef enum EBI_SDDATAW_enum
+{
+ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
+ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/* */
+typedef enum EBI_LPCMODE_enum
+{
+ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
+ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* */
+typedef enum EBI_SRMODE_enum
+{
+ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
+ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
+ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
+ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* */
+typedef enum EBI_IFMODE_enum
+{
+ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
+ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
+ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
+ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
+} EBI_IFMODE_t;
+
+/* */
+typedef enum EBI_SDCOL_enum
+{
+ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
+ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
+ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+} EBI_SDCOL_t;
+
+/* */
+typedef enum EBI_MRDLY_enum
+{
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* */
+typedef enum EBI_ROWCYCDLY_enum
+{
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* */
+typedef enum EBI_RPDLY_enum
+{
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_RPDLY_t;
+
+/* */
+typedef enum EBI_WRDLY_enum
+{
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_WRDLY_t;
+
+/* */
+typedef enum EBI_ESRDLY_enum
+{
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/* */
+typedef enum EBI_ROWCOLDLY_enum
+{
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_MASTER_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t STATUS; /* Status Register */
+ register8_t BAUD; /* Baurd Rate Control Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+} TWI_MASTER_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_SLAVE_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+ register8_t ADDRMASK; /* Address Mask Register */
+} TWI_SLAVE_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+ register8_t CTRL; /* TWI Common Control Register */
+ TWI_MASTER_t MASTER; /* TWI master module */
+ TWI_SLAVE_t SLAVE; /* TWI slave module */
+} TWI_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+ register8_t MPCMASK; /* Multi-pin Configuration Mask */
+ register8_t reserved_0x01;
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
+} PORTCFG_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t OUT; /* I/O Port Output */
+ register8_t IN; /* I/O Port Input */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+} VPORT_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t DIRSET; /* I/O Port Data Direction Set */
+ register8_t DIRCLR; /* I/O Port Data Direction Clear */
+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
+ register8_t OUT; /* I/O Port Output */
+ register8_t OUTSET; /* I/O Port Output Set */
+ register8_t OUTCLR; /* I/O Port Output Clear */
+ register8_t OUTTGL; /* I/O Port Output Toggle */
+ register8_t IN; /* I/O port Input */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INT0MASK; /* Port Interrupt 0 Mask */
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+ register8_t PIN2CTRL; /* Pin 2 Control Register */
+ register8_t PIN3CTRL; /* Pin 3 Control Register */
+ register8_t PIN4CTRL; /* Pin 4 Control Register */
+ register8_t PIN5CTRL; /* Pin 5 Control Register */
+ register8_t PIN6CTRL; /* Pin 6 Control Register */
+ register8_t PIN7CTRL; /* Pin 7 Control Register */
+} PORT_t;
+
+/* Virtual Port 0 Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Virtual Port 1 Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Virtual Port 2 Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port 3 Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/* Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
+} PORT_INT1LVL_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ _WORDREGISTER(CCC); /* Compare or Capture C */
+ _WORDREGISTER(CCD); /* Compare or Capture D */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+} TC0_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x05;
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+ register8_t DTHS; /* Dead Time High Side */
+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
+ register8_t DTHSBUF; /* Dead Time High Side Buffer */
+ register8_t OUTOVEN; /* Output Override Enable */
+} AWEX_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+ register8_t CTRLA; /* Control Register */
+} HIRES_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+ register8_t DATA; /* Data Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
+} USART_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
+} USART_TXCINTLVL_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
+} USART_DREINTLVL_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
+} USART_PMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t DATA; /* Data Register */
+} SPI_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} SPI_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
+ register8_t CTRL; /* Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRDA_EVSEL_enum
+{
+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
+} IRDA_EVSEL_t;
+
+
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
+#define CLK (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
+#define PR (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST (*(RST_t *) 0x0078) /* Reset Controller */
+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
+#define GPIO_GPIORA _SFR_MEM8(0x000A)
+#define GPIO_GPIORB _SFR_MEM8(0x000B)
+#define GPIO_GPIORC _SFR_MEM8(0x000C)
+#define GPIO_GPIORD _SFR_MEM8(0x000D)
+#define GPIO_GPIORE _SFR_MEM8(0x000E)
+#define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+/* VPORT0 - Virtual Port 0 */
+#define VPORT0_DIR _SFR_MEM8(0x0010)
+#define VPORT0_OUT _SFR_MEM8(0x0011)
+#define VPORT0_IN _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+/* VPORT1 - Virtual Port 1 */
+#define VPORT1_DIR _SFR_MEM8(0x0014)
+#define VPORT1_OUT _SFR_MEM8(0x0015)
+#define VPORT1_IN _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+/* VPORT2 - Virtual Port 2 */
+#define VPORT2_DIR _SFR_MEM8(0x0018)
+#define VPORT2_OUT _SFR_MEM8(0x0019)
+#define VPORT2_IN _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+/* VPORT3 - Virtual Port 3 */
+#define VPORT3_DIR _SFR_MEM8(0x001C)
+#define VPORT3_OUT _SFR_MEM8(0x001D)
+#define VPORT3_IN _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0 _SFR_MEM8(0x002E)
+#define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+/* CPU - CPU Registers */
+#define CPU_CCP _SFR_MEM8(0x0034)
+#define CPU_RAMPD _SFR_MEM8(0x0038)
+#define CPU_RAMPX _SFR_MEM8(0x0039)
+#define CPU_RAMPY _SFR_MEM8(0x003A)
+#define CPU_RAMPZ _SFR_MEM8(0x003B)
+#define CPU_EIND _SFR_MEM8(0x003C)
+#define CPU_SPL _SFR_MEM8(0x003D)
+#define CPU_SPH _SFR_MEM8(0x003E)
+#define CPU_SREG _SFR_MEM8(0x003F)
+
+/* CLK - Clock System */
+#define CLK_CTRL _SFR_MEM8(0x0040)
+#define CLK_PSCTRL _SFR_MEM8(0x0041)
+#define CLK_LOCK _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL _SFR_MEM8(0x0043)
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+/* OSC - Oscillator Control */
+#define OSC_CTRL _SFR_MEM8(0x0050)
+#define OSC_STATUS _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+
+/* PR - Power Reduction */
+#define PR_PRGEN _SFR_MEM8(0x0070)
+#define PR_PRPA _SFR_MEM8(0x0071)
+#define PR_PRPB _SFR_MEM8(0x0072)
+#define PR_PRPC _SFR_MEM8(0x0073)
+#define PR_PRPD _SFR_MEM8(0x0074)
+#define PR_PRPE _SFR_MEM8(0x0075)
+#define PR_PRPF _SFR_MEM8(0x0076)
+
+/* RST - Reset Controller */
+#define RST_STATUS _SFR_MEM8(0x0078)
+#define RST_CTRL _SFR_MEM8(0x0079)
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL _SFR_MEM8(0x0080)
+#define WDT_WINCTRL _SFR_MEM8(0x0081)
+#define WDT_STATUS _SFR_MEM8(0x0082)
+
+/* MCU - MCU Control */
+#define MCU_DEVID0 _SFR_MEM8(0x0090)
+#define MCU_DEVID1 _SFR_MEM8(0x0091)
+#define MCU_DEVID2 _SFR_MEM8(0x0092)
+#define MCU_REVID _SFR_MEM8(0x0093)
+#define MCU_JTAGUID _SFR_MEM8(0x0094)
+#define MCU_MCUCR _SFR_MEM8(0x0096)
+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+/* PMIC - Programmable Interrupt Controller */
+#define PMIC_STATUS _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI _SFR_MEM8(0x00A1)
+#define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+/* PORTCFG - Port Configuration */
+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
+#define EVSYS_STROBE _SFR_MEM8(0x0190)
+#define EVSYS_DATA _SFR_MEM8(0x0191)
+
+/* NVM - Non Volatile Memory Controller */
+#define NVM_ADDR0 _SFR_MEM8(0x01C0)
+#define NVM_ADDR1 _SFR_MEM8(0x01C1)
+#define NVM_ADDR2 _SFR_MEM8(0x01C2)
+#define NVM_DATA0 _SFR_MEM8(0x01C4)
+#define NVM_DATA1 _SFR_MEM8(0x01C5)
+#define NVM_DATA2 _SFR_MEM8(0x01C6)
+#define NVM_CMD _SFR_MEM8(0x01CA)
+#define NVM_CTRLA _SFR_MEM8(0x01CB)
+#define NVM_CTRLB _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL _SFR_MEM8(0x01CD)
+#define NVM_STATUS _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+/* ADCA - Analog to Digital Converter A */
+#define ADCA_CTRLA _SFR_MEM8(0x0200)
+#define ADCA_CTRLB _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER _SFR_MEM8(0x0204)
+#define ADCA_CALCTRL _SFR_MEM8(0x0205)
+#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
+#define ADCA_CAL _SFR_MEM16(0x020C)
+#define ADCA_CH0RES _SFR_MEM16(0x0210)
+#define ADCA_CMP _SFR_MEM16(0x0218)
+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES _SFR_MEM16(0x0224)
+
+/* ACA - Analog Comparator A */
+#define ACA_AC0CTRL _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
+#define ACA_CTRLA _SFR_MEM8(0x0384)
+#define ACA_CTRLB _SFR_MEM8(0x0385)
+#define ACA_WINCTRL _SFR_MEM8(0x0386)
+#define ACA_STATUS _SFR_MEM8(0x0387)
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL _SFR_MEM8(0x0400)
+#define RTC_STATUS _SFR_MEM8(0x0401)
+#define RTC_INTCTRL _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS _SFR_MEM8(0x0403)
+#define RTC_TEMP _SFR_MEM8(0x0404)
+#define RTC_CNT _SFR_MEM16(0x0408)
+#define RTC_PER _SFR_MEM16(0x040A)
+#define RTC_COMP _SFR_MEM16(0x040C)
+
+/* TWIC - Two-Wire Interface C */
+#define TWIC_CTRL _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483)
+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484)
+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485)
+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486)
+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487)
+#define TWIC_MASTER_DATA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+/* PORTA - Port A */
+#define PORTA_DIR _SFR_MEM8(0x0600)
+#define PORTA_DIRSET _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL _SFR_MEM8(0x0603)
+#define PORTA_OUT _SFR_MEM8(0x0604)
+#define PORTA_OUTSET _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL _SFR_MEM8(0x0607)
+#define PORTA_IN _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+/* PORTB - Port B */
+#define PORTB_DIR _SFR_MEM8(0x0620)
+#define PORTB_DIRSET _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL _SFR_MEM8(0x0623)
+#define PORTB_OUT _SFR_MEM8(0x0624)
+#define PORTB_OUTSET _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL _SFR_MEM8(0x0627)
+#define PORTB_IN _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+/* PORTC - Port C */
+#define PORTC_DIR _SFR_MEM8(0x0640)
+#define PORTC_DIRSET _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL _SFR_MEM8(0x0643)
+#define PORTC_OUT _SFR_MEM8(0x0644)
+#define PORTC_OUTSET _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL _SFR_MEM8(0x0647)
+#define PORTC_IN _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+/* PORTD - Port D */
+#define PORTD_DIR _SFR_MEM8(0x0660)
+#define PORTD_DIRSET _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL _SFR_MEM8(0x0663)
+#define PORTD_OUT _SFR_MEM8(0x0664)
+#define PORTD_OUTSET _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL _SFR_MEM8(0x0667)
+#define PORTD_IN _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+/* PORTE - Port E */
+#define PORTE_DIR _SFR_MEM8(0x0680)
+#define PORTE_DIRSET _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL _SFR_MEM8(0x0683)
+#define PORTE_OUT _SFR_MEM8(0x0684)
+#define PORTE_OUTSET _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL _SFR_MEM8(0x0687)
+#define PORTE_IN _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+/* PORTF - Port F */
+#define PORTF_DIR _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
+#define PORTF_OUT _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
+#define PORTF_IN _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+/* PORTR - Port R */
+#define PORTR_DIR _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
+#define PORTR_OUT _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
+#define PORTR_IN _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+/* TCC0 - Timer/Counter C0 */
+#define TCC0_CTRLA _SFR_MEM8(0x0800)
+#define TCC0_CTRLB _SFR_MEM8(0x0801)
+#define TCC0_CTRLC _SFR_MEM8(0x0802)
+#define TCC0_CTRLD _SFR_MEM8(0x0803)
+#define TCC0_CTRLE _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
+#define TCC0_TEMP _SFR_MEM8(0x080F)
+#define TCC0_CNT _SFR_MEM16(0x0820)
+#define TCC0_PER _SFR_MEM16(0x0826)
+#define TCC0_CCA _SFR_MEM16(0x0828)
+#define TCC0_CCB _SFR_MEM16(0x082A)
+#define TCC0_CCC _SFR_MEM16(0x082C)
+#define TCC0_CCD _SFR_MEM16(0x082E)
+#define TCC0_PERBUF _SFR_MEM16(0x0836)
+#define TCC0_CCABUF _SFR_MEM16(0x0838)
+#define TCC0_CCBBUF _SFR_MEM16(0x083A)
+#define TCC0_CCCBUF _SFR_MEM16(0x083C)
+#define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+/* TCC1 - Timer/Counter C1 */
+#define TCC1_CTRLA _SFR_MEM8(0x0840)
+#define TCC1_CTRLB _SFR_MEM8(0x0841)
+#define TCC1_CTRLC _SFR_MEM8(0x0842)
+#define TCC1_CTRLD _SFR_MEM8(0x0843)
+#define TCC1_CTRLE _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
+#define TCC1_TEMP _SFR_MEM8(0x084F)
+#define TCC1_CNT _SFR_MEM16(0x0860)
+#define TCC1_PER _SFR_MEM16(0x0866)
+#define TCC1_CCA _SFR_MEM16(0x0868)
+#define TCC1_CCB _SFR_MEM16(0x086A)
+#define TCC1_PERBUF _SFR_MEM16(0x0876)
+#define TCC1_CCABUF _SFR_MEM16(0x0878)
+#define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+/* AWEXC - Advanced Waveform Extension C */
+#define AWEXC_CTRL _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+#define AWEXC_STATUS _SFR_MEM8(0x0884)
+#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+#define AWEXC_DTLS _SFR_MEM8(0x0888)
+#define AWEXC_DTHS _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+/* HIRESC - High-Resolution Extension C */
+#define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0_DATA _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+/* SPIC - Serial Peripheral Interface C */
+#define SPIC_CTRL _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+#define SPIC_STATUS _SFR_MEM8(0x08C2)
+#define SPIC_DATA _SFR_MEM8(0x08C3)
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8)
+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9)
+#define IRCOM_CTRL _SFR_MEM8(0x08FA)
+
+/* TCD0 - Timer/Counter D0 */
+#define TCD0_CTRLA _SFR_MEM8(0x0900)
+#define TCD0_CTRLB _SFR_MEM8(0x0901)
+#define TCD0_CTRLC _SFR_MEM8(0x0902)
+#define TCD0_CTRLD _SFR_MEM8(0x0903)
+#define TCD0_CTRLE _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
+#define TCD0_TEMP _SFR_MEM8(0x090F)
+#define TCD0_CNT _SFR_MEM16(0x0920)
+#define TCD0_PER _SFR_MEM16(0x0926)
+#define TCD0_CCA _SFR_MEM16(0x0928)
+#define TCD0_CCB _SFR_MEM16(0x092A)
+#define TCD0_CCC _SFR_MEM16(0x092C)
+#define TCD0_CCD _SFR_MEM16(0x092E)
+#define TCD0_PERBUF _SFR_MEM16(0x0936)
+#define TCD0_CCABUF _SFR_MEM16(0x0938)
+#define TCD0_CCBBUF _SFR_MEM16(0x093A)
+#define TCD0_CCCBUF _SFR_MEM16(0x093C)
+#define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0_DATA _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+/* SPID - Serial Peripheral Interface D */
+#define SPID_CTRL _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL _SFR_MEM8(0x09C1)
+#define SPID_STATUS _SFR_MEM8(0x09C2)
+#define SPID_DATA _SFR_MEM8(0x09C3)
+
+/* TCE0 - Timer/Counter E0 */
+#define TCE0_CTRLA _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP _SFR_MEM8(0x0A0F)
+#define TCE0_CNT _SFR_MEM16(0x0A20)
+#define TCE0_PER _SFR_MEM16(0x0A26)
+#define TCE0_CCA _SFR_MEM16(0x0A28)
+#define TCE0_CCB _SFR_MEM16(0x0A2A)
+#define TCE0_CCC _SFR_MEM16(0x0A2C)
+#define TCE0_CCD _SFR_MEM16(0x0A2E)
+#define TCE0_PERBUF _SFR_MEM16(0x0A36)
+#define TCE0_CCABUF _SFR_MEM16(0x0A38)
+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+/* AWEXE - Advanced Waveform Extension E */
+#define AWEXE_CTRL _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS _SFR_MEM8(0x0A84)
+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0_DATA _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+/* SPIE - Serial Peripheral Interface E */
+#define SPIE_CTRL _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS _SFR_MEM8(0x0AC2)
+#define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+/* TCF0 - Timer/Counter F0 */
+#define TCF0_CTRLA _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP _SFR_MEM8(0x0B0F)
+#define TCF0_CNT _SFR_MEM16(0x0B20)
+#define TCF0_PER _SFR_MEM16(0x0B26)
+#define TCF0_CCA _SFR_MEM16(0x0B28)
+#define TCF0_CCB _SFR_MEM16(0x0B2A)
+#define TCF0_CCC _SFR_MEM16(0x0B2C)
+#define TCF0_CCD _SFR_MEM16(0x0B2E)
+#define TCF0_PERBUF _SFR_MEM16(0x0B36)
+#define TCF0_CCABUF _SFR_MEM16(0x0B38)
+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR1 bit masks and bit positions */
+#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+
+/* CPU - CPU */
+/* CPU.CCP bit masks and bit positions */
+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+#define CPU_CCP_gp 0 /* CCP signature group position. */
+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+
+/* CPU.SREG bit masks and bit positions */
+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+
+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
+#define CPU_T_bp 6 /* Transfer Bit bit position. */
+
+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
+#define CPU_H_bp 5 /* Half Carry Flag bit position. */
+
+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
+
+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
+
+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
+#define CPU_N_bp 2 /* Negative Flag bit position. */
+
+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
+#define CPU_Z_bp 1 /* Zero Flag bit position. */
+
+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+#define CPU_C_bp 0 /* Carry Flag bit position. */
+
+
+/* CLK - Clock System */
+/* CLK.CTRL bit masks and bit positions */
+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+
+/* CLK.PSCTRL bit masks and bit positions */
+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
+
+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+
+/* CLK.LOCK bit masks and bit positions */
+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+
+/* CLK.RTCCTRL bit masks and bit positions */
+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
+
+#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
+
+
+/* PR.PRGEN bit masks and bit positions */
+#define PR_AES_bm 0x10 /* AES bit mask. */
+#define PR_AES_bp 4 /* AES bit position. */
+
+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
+#define PR_EBI_bp 3 /* External Bus Interface bit position. */
+
+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
+#define PR_RTC_bp 2 /* Real-time Counter bit position. */
+
+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
+#define PR_EVSYS_bp 1 /* Event System bit position. */
+
+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
+#define PR_DMA_bp 0 /* DMA-Controller bit position. */
+
+
+/* PR.PRPA bit masks and bit positions */
+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
+#define PR_DAC_bp 2 /* Port A DAC bit position. */
+
+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
+#define PR_ADC_bp 1 /* Port A ADC bit position. */
+
+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+
+/* PR.PRPB bit masks and bit positions */
+/* PR_DAC_bm Predefined. */
+/* PR_DAC_bp Predefined. */
+
+/* PR_ADC_bm Predefined. */
+/* PR_ADC_bp Predefined. */
+
+/* PR_AC_bm Predefined. */
+/* PR_AC_bp Predefined. */
+
+
+/* PR.PRPC bit masks and bit positions */
+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
+
+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
+#define PR_USART1_bp 5 /* Port C USART1 bit position. */
+
+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
+#define PR_USART0_bp 4 /* Port C USART0 bit position. */
+
+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
+#define PR_SPI_bp 3 /* Port C SPI bit position. */
+
+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+
+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
+
+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+
+/* PR.PRPD bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPE bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPF bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL bit masks and bit positions */
+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
+
+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+
+/* OSC - Oscillator */
+/* OSC.CTRL bit masks and bit positions */
+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
+
+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
+
+#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
+
+#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
+
+#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
+
+
+/* OSC.STATUS bit masks and bit positions */
+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+
+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
+
+#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
+
+#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
+
+#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
+
+
+/* OSC.XOSCCTRL bit masks and bit positions */
+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
+
+#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
+
+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+
+/* OSC.XOSCFAIL bit masks and bit positions */
+#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
+
+#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
+
+
+/* OSC.PLLCTRL bit masks and bit positions */
+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+
+/* OSC.DFLLCTRL bit masks and bit positions */
+#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
+#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
+
+#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL bit masks and bit positions */
+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+
+/* DFLL.CALA bit masks and bit positions */
+#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
+#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
+#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
+#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
+#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
+#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
+#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
+#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
+#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
+
+
+/* DFLL.CALB bit masks and bit positions */
+#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
+#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
+#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
+#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
+#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
+#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
+#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
+#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
+
+
+/* RST - Reset */
+/* RST.STATUS bit masks and bit positions */
+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
+
+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
+
+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
+
+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
+
+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
+
+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
+
+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+
+/* RST.CTRL bit masks and bit positions */
+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+#define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL bit masks and bit positions */
+#define WDT_PER_gm 0x3C /* Period group mask. */
+#define WDT_PER_gp 2 /* Period group position. */
+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
+#define WDT_PER0_bp 2 /* Period bit 0 position. */
+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
+#define WDT_PER1_bp 3 /* Period bit 1 position. */
+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
+#define WDT_PER2_bp 4 /* Period bit 2 position. */
+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
+#define WDT_PER3_bp 5 /* Period bit 3 position. */
+
+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
+#define WDT_ENABLE_bp 1 /* Enable bit position. */
+
+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+#define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+
+/* WDT.WINCTRL bit masks and bit positions */
+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
+
+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
+
+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+
+/* WDT.STATUS bit masks and bit positions */
+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR bit masks and bit positions */
+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+
+/* MCU.EVSYSLOCK bit masks and bit positions */
+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
+
+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+
+/* MCU.AWEXLOCK bit masks and bit positions */
+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS bit masks and bit positions */
+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
+
+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
+
+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
+
+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+
+/* PMIC.CTRL bit masks and bit positions */
+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+
+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
+
+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
+
+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
+
+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX bit masks and bit positions */
+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+
+/* EVSYS.CH1MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH2MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH3MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH0CTRL bit masks and bit positions */
+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
+
+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
+
+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+
+/* EVSYS.CH1CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH2CTRL bit masks and bit positions */
+/* EVSYS_QDIRM_gm Predefined. */
+/* EVSYS_QDIRM_gp Predefined. */
+/* EVSYS_QDIRM0_bm Predefined. */
+/* EVSYS_QDIRM0_bp Predefined. */
+/* EVSYS_QDIRM1_bm Predefined. */
+/* EVSYS_QDIRM1_bp Predefined. */
+
+/* EVSYS_QDIEN_bm Predefined. */
+/* EVSYS_QDIEN_bp Predefined. */
+
+/* EVSYS_QDEN_bm Predefined. */
+/* EVSYS_QDEN_bp Predefined. */
+
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH3CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD bit masks and bit positions */
+#define NVM_CMD_gm 0xFF /* Command group mask. */
+#define NVM_CMD_gp 0 /* Command group position. */
+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define NVM_CMD0_bp 0 /* Command bit 0 position. */
+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define NVM_CMD1_bp 1 /* Command bit 1 position. */
+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
+#define NVM_CMD2_bp 2 /* Command bit 2 position. */
+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
+#define NVM_CMD3_bp 3 /* Command bit 3 position. */
+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
+#define NVM_CMD4_bp 4 /* Command bit 4 position. */
+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
+#define NVM_CMD5_bp 5 /* Command bit 5 position. */
+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+#define NVM_CMD6_bp 6 /* Command bit 6 position. */
+#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
+#define NVM_CMD7_bp 7 /* Command bit 7 position. */
+
+
+/* NVM.CTRLA bit masks and bit positions */
+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+
+/* NVM.CTRLB bit masks and bit positions */
+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+
+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
+
+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
+
+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+
+/* NVM.INTCTRL bit masks and bit positions */
+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
+
+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+
+/* NVM.STATUS bit masks and bit positions */
+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+
+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
+
+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
+
+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+
+/* NVM.LOCKBITS bit masks and bit positions */
+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
+#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
+#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
+#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
+#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
+#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
+#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
+#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
+#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
+#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
+#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
+#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
+#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
+#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
+#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
+#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
+#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
+#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
+#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
+
+
+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
+
+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
+
+
+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
+#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
+#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
+
+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
+
+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
+
+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
+
+
+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
+
+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
+
+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
+
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL bit masks and bit positions */
+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
+
+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
+
+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
+
+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
+
+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+#define AC_ENABLE_bp 0 /* Enable bit position. */
+
+
+/* AC.AC1CTRL bit masks and bit positions */
+/* AC_INTMODE_gm Predefined. */
+/* AC_INTMODE_gp Predefined. */
+/* AC_INTMODE0_bm Predefined. */
+/* AC_INTMODE0_bp Predefined. */
+/* AC_INTMODE1_bm Predefined. */
+/* AC_INTMODE1_bp Predefined. */
+
+/* AC_INTLVL_gm Predefined. */
+/* AC_INTLVL_gp Predefined. */
+/* AC_INTLVL0_bm Predefined. */
+/* AC_INTLVL0_bp Predefined. */
+/* AC_INTLVL1_bm Predefined. */
+/* AC_INTLVL1_bp Predefined. */
+
+/* AC_HSMODE_bm Predefined. */
+/* AC_HSMODE_bp Predefined. */
+
+/* AC_HYSMODE_gm Predefined. */
+/* AC_HYSMODE_gp Predefined. */
+/* AC_HYSMODE0_bm Predefined. */
+/* AC_HYSMODE0_bp Predefined. */
+/* AC_HYSMODE1_bm Predefined. */
+/* AC_HYSMODE1_bp Predefined. */
+
+/* AC_ENABLE_bm Predefined. */
+/* AC_ENABLE_bp Predefined. */
+
+
+/* AC.AC0MUXCTRL bit masks and bit positions */
+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
+
+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+
+/* AC.AC1MUXCTRL bit masks and bit positions */
+/* AC_MUXPOS_gm Predefined. */
+/* AC_MUXPOS_gp Predefined. */
+/* AC_MUXPOS0_bm Predefined. */
+/* AC_MUXPOS0_bp Predefined. */
+/* AC_MUXPOS1_bm Predefined. */
+/* AC_MUXPOS1_bp Predefined. */
+/* AC_MUXPOS2_bm Predefined. */
+/* AC_MUXPOS2_bp Predefined. */
+
+/* AC_MUXNEG_gm Predefined. */
+/* AC_MUXNEG_gp Predefined. */
+/* AC_MUXNEG0_bm Predefined. */
+/* AC_MUXNEG0_bp Predefined. */
+/* AC_MUXNEG1_bm Predefined. */
+/* AC_MUXNEG1_bp Predefined. */
+/* AC_MUXNEG2_bm Predefined. */
+/* AC_MUXNEG2_bp Predefined. */
+
+
+/* AC.CTRLA bit masks and bit positions */
+#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
+
+
+/* AC.CTRLB bit masks and bit positions */
+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+
+/* AC.WINCTRL bit masks and bit positions */
+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+
+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
+
+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+
+/* AC.STATUS bit masks and bit positions */
+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+#define AC_WSTATE_gp 6 /* Window Mode State group position. */
+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
+
+#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
+
+#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
+
+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
+
+#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
+
+#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
+
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL bit masks and bit positions */
+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
+
+#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
+#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
+#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
+#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
+#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
+
+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+
+/* ADC_CH.MUXCTRL bit masks and bit positions */
+#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
+#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
+#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
+#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
+#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
+#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
+
+#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
+#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
+#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
+#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
+#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
+#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
+#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
+#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
+#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
+#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
+
+#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
+#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
+#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
+#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
+
+
+/* ADC_CH.INTCTRL bit masks and bit positions */
+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
+
+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+
+/* ADC_CH.INTFLAGS bit masks and bit positions */
+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
+
+/* ADC.CTRLA bit masks and bit positions */
+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
+
+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+
+/* ADC.CTRLB bit masks and bit positions */
+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+
+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
+
+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+
+/* ADC.REFCTRL bit masks and bit positions */
+#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
+
+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
+
+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+
+/* ADC.EVCTRL bit masks and bit positions */
+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
+
+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
+
+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
+#define ADC_EVACT_gp 0 /* Event Action Select group position. */
+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
+
+
+/* ADC.PRESCALER bit masks and bit positions */
+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+
+/* ADC.CALCTRL bit masks and bit positions */
+#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
+#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
+
+
+/* ADC.INTFLAGS bit masks and bit positions */
+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+
+/* RTC - Real-Time Clounter */
+/* RTC.CTRL bit masks and bit positions */
+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+
+/* RTC.STATUS bit masks and bit positions */
+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+
+/* RTC.INTCTRL bit masks and bit positions */
+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
+
+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+
+/* RTC.INTFLAGS bit masks and bit positions */
+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+
+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* EBI - External Bus Interface */
+/* EBI_CS.CTRLA bit masks and bit positions */
+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
+#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
+#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+
+/* EBI_CS.CTRLB bit masks and bit positions */
+#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
+#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
+#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
+#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
+#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
+#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
+
+#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
+#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
+
+#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
+#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
+
+#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
+#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
+#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
+#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
+#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+
+/* EBI.CTRL bit masks and bit positions */
+#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
+#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
+#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
+#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
+
+#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
+#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
+#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
+#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
+#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
+#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
+
+#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
+#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
+#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
+#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
+#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
+#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
+
+#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
+#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
+#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
+#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
+#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+
+/* EBI.SDRAMCTRLA bit masks and bit positions */
+#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+
+#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
+#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
+
+#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
+#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
+#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
+#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
+#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+
+/* EBI.SDRAMCTRLB bit masks and bit positions */
+#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
+#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
+#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
+#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
+
+#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
+#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
+#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
+#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
+#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
+#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
+#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
+#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
+
+#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
+#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
+#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
+#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
+#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
+#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
+#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+
+/* EBI.SDRAMCTRLC bit masks and bit positions */
+#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
+#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
+#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
+#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
+
+#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+
+#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
+#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
+#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
+#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
+#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
+#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
+#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA bit masks and bit positions */
+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
+
+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
+
+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+
+/* TWI_MASTER.CTRLB bit masks and bit positions */
+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
+
+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
+
+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_MASTER.CTRLC bit masks and bit positions */
+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
+#define TWI_MASTER_CMD_gp 0 /* Command group position. */
+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_MASTER.STATUS bit masks and bit positions */
+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+
+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
+
+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
+
+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+
+/* TWI_SLAVE.CTRLA bit masks and bit positions */
+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
+
+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
+
+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
+
+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_SLAVE.CTRLB bit masks and bit positions */
+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_SLAVE.STATUS bit masks and bit positions */
+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+
+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
+
+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
+
+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
+
+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+
+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
+
+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+
+/* TWI.CTRL bit masks and bit positions */
+#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+
+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+
+/* PORT - Port Configuration */
+/* PORTCFG.VPCTRLA bit masks and bit positions */
+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
+
+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+
+/* PORTCFG.VPCTRLB bit masks and bit positions */
+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
+
+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+
+/* PORTCFG.CLKEVOUT bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
+
+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
+
+
+/* VPORT.INTFLAGS bit masks and bit positions */
+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.INTCTRL bit masks and bit positions */
+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
+
+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+
+/* PORT.INTFLAGS bit masks and bit positions */
+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.PIN0CTRL bit masks and bit positions */
+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
+
+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
+
+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
+
+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+
+/* PORT.PIN1CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN2CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN3CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN4CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN5CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN6CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN7CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA bit masks and bit positions */
+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC0.CTRLB bit masks and bit positions */
+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+
+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
+
+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC0.CTRLC bit masks and bit positions */
+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+
+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
+
+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC0.CTRLD bit masks and bit positions */
+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC0_EVACT_gp 5 /* Event Action group position. */
+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC0.CTRLE bit masks and bit positions */
+#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC0.INTCTRLA bit masks and bit positions */
+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC0.INTCTRLB bit masks and bit positions */
+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
+
+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
+
+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC0.CTRLFCLR bit masks and bit positions */
+#define TC0_CMD_gm 0x0C /* Command group mask. */
+#define TC0_CMD_gp 2 /* Command group position. */
+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC0_CMD0_bp 2 /* Command bit 0 position. */
+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC0_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC0_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC0_DIR_bm 0x01 /* Direction bit mask. */
+#define TC0_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC0.CTRLFSET bit masks and bit positions */
+/* TC0_CMD_gm Predefined. */
+/* TC0_CMD_gp Predefined. */
+/* TC0_CMD0_bm Predefined. */
+/* TC0_CMD0_bp Predefined. */
+/* TC0_CMD1_bm Predefined. */
+/* TC0_CMD1_bp Predefined. */
+
+/* TC0_LUPD_bm Predefined. */
+/* TC0_LUPD_bp Predefined. */
+
+/* TC0_DIR_bm Predefined. */
+/* TC0_DIR_bp Predefined. */
+
+
+/* TC0.CTRLGCLR bit masks and bit positions */
+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
+
+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
+
+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC0.CTRLGSET bit masks and bit positions */
+/* TC0_CCDBV_bm Predefined. */
+/* TC0_CCDBV_bp Predefined. */
+
+/* TC0_CCCBV_bm Predefined. */
+/* TC0_CCCBV_bp Predefined. */
+
+/* TC0_CCBBV_bm Predefined. */
+/* TC0_CCBBV_bp Predefined. */
+
+/* TC0_CCABV_bm Predefined. */
+/* TC0_CCABV_bp Predefined. */
+
+/* TC0_PERBV_bm Predefined. */
+/* TC0_PERBV_bp Predefined. */
+
+
+/* TC0.INTFLAGS bit masks and bit positions */
+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
+
+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
+
+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* TC1.CTRLA bit masks and bit positions */
+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC1.CTRLB bit masks and bit positions */
+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC1.CTRLC bit masks and bit positions */
+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC1.CTRLD bit masks and bit positions */
+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC1_EVACT_gp 5 /* Event Action group position. */
+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC1.CTRLE bit masks and bit positions */
+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC1.INTCTRLA bit masks and bit positions */
+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC1.INTCTRLB bit masks and bit positions */
+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC1.CTRLFCLR bit masks and bit positions */
+#define TC1_CMD_gm 0x0C /* Command group mask. */
+#define TC1_CMD_gp 2 /* Command group position. */
+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC1_CMD0_bp 2 /* Command bit 0 position. */
+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC1_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC1_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC1_DIR_bm 0x01 /* Direction bit mask. */
+#define TC1_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC1.CTRLFSET bit masks and bit positions */
+/* TC1_CMD_gm Predefined. */
+/* TC1_CMD_gp Predefined. */
+/* TC1_CMD0_bm Predefined. */
+/* TC1_CMD0_bp Predefined. */
+/* TC1_CMD1_bm Predefined. */
+/* TC1_CMD1_bp Predefined. */
+
+/* TC1_LUPD_bm Predefined. */
+/* TC1_LUPD_bp Predefined. */
+
+/* TC1_DIR_bm Predefined. */
+/* TC1_DIR_bp Predefined. */
+
+
+/* TC1.CTRLGCLR bit masks and bit positions */
+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC1.CTRLGSET bit masks and bit positions */
+/* TC1_CCBBV_bm Predefined. */
+/* TC1_CCBBV_bp Predefined. */
+
+/* TC1_CCABV_bm Predefined. */
+/* TC1_CCABV_bp Predefined. */
+
+/* TC1_PERBV_bm Predefined. */
+/* TC1_PERBV_bp Predefined. */
+
+
+/* TC1.INTFLAGS bit masks and bit positions */
+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* AWEX.CTRL bit masks and bit positions */
+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
+
+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
+
+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
+
+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
+
+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
+
+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+
+/* AWEX.FDCTRL bit masks and bit positions */
+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+
+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
+
+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+
+/* AWEX.STATUS bit masks and bit positions */
+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+
+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
+
+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
+
+/* HIRES.CTRLA bit masks and bit positions */
+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS bit masks and bit positions */
+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
+
+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
+
+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
+
+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
+#define USART_FERR_bp 4 /* Frame Error bit position. */
+
+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
+
+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
+#define USART_PERR_bp 2 /* Parity Error bit position. */
+
+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+
+/* USART.CTRLA bit masks and bit positions */
+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
+
+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
+
+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+
+/* USART.CTRLB bit masks and bit positions */
+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+
+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
+
+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
+
+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
+
+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+
+/* USART.CTRLC bit masks and bit positions */
+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+#define USART_CMODE_gp 6 /* Communication Mode group position. */
+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
+
+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
+#define USART_PMODE_gp 4 /* Parity Mode group position. */
+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
+
+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
+
+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
+#define USART_CHSIZE_gp 0 /* Character Size group position. */
+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+
+/* USART.BAUDCTRLA bit masks and bit positions */
+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+
+/* USART.BAUDCTRLB bit masks and bit positions */
+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+/* USART_BSEL_gm Predefined. */
+/* USART_BSEL_gp Predefined. */
+/* USART_BSEL0_bm Predefined. */
+/* USART_BSEL0_bp Predefined. */
+/* USART_BSEL1_bm Predefined. */
+/* USART_BSEL1_bp Predefined. */
+/* USART_BSEL2_bm Predefined. */
+/* USART_BSEL2_bp Predefined. */
+/* USART_BSEL3_bm Predefined. */
+/* USART_BSEL3_bp Predefined. */
+
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL bit masks and bit positions */
+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
+
+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
+
+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
+
+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
+
+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
+#define SPI_MODE_gp 2 /* SPI Mode group position. */
+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
+
+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+
+/* SPI.INTCTRL bit masks and bit positions */
+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+
+/* SPI.STATUS bit masks and bit positions */
+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+
+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL bit masks and bit positions */
+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_XOSCF_vect_num 1
+#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num 2
+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
+#define PORTC_INT1_vect_num 3
+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num 4
+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
+#define PORTR_INT1_vect_num 5
+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num 10
+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
+#define RTC_COMP_vect_num 11
+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num 12
+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num 13
+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num 14
+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
+#define TCC0_ERR_vect_num 15
+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
+#define TCC0_CCA_vect_num 16
+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
+#define TCC0_CCB_vect_num 17
+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
+#define TCC0_CCC_vect_num 18
+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
+#define TCC0_CCD_vect_num 19
+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num 20
+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+#define TCC1_ERR_vect_num 21
+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
+#define TCC1_CCA_vect_num 22
+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num 23
+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num 24
+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num 25
+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num 26
+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num 27
+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num 32
+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
+#define NVM_SPM_vect_num 33
+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num 34
+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
+#define PORTB_INT1_vect_num 35
+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num 43
+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
+#define PORTE_INT1_vect_num 44
+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num 47
+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
+#define TCE0_ERR_vect_num 48
+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
+#define TCE0_CCA_vect_num 49
+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
+#define TCE0_CCB_vect_num 50
+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
+#define TCE0_CCC_vect_num 51
+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
+#define TCE0_CCD_vect_num 52
+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num 58
+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num 59
+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num 60
+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num 64
+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
+#define PORTD_INT1_vect_num 65
+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num 66
+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
+#define PORTA_INT1_vect_num 67
+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num 68
+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
+#define ACA_AC1_vect_num 69
+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
+#define ACA_ACW_vect_num 70
+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num 71
+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num 77
+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
+#define TCD0_ERR_vect_num 78
+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
+#define TCD0_CCA_vect_num 79
+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
+#define TCD0_CCB_vect_num 80
+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
+#define TCD0_CCC_vect_num 81
+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
+#define TCD0_CCD_vect_num 82
+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num 87
+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num 88
+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num 89
+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num 90
+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num 104
+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
+#define PORTF_INT1_vect_num 105
+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num 108
+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
+#define TCF0_ERR_vect_num 109
+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
+#define TCF0_CCA_vect_num 110
+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
+#define TCF0_CCB_vect_num 111
+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
+#define TCF0_CCC_vect_num 112
+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
+#define TCF0_CCD_vect_num 113
+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#define PROGMEM_START (0x0000)
+#define PROGMEM_SIZE (139264)
+#define PROGMEM_PAGE_SIZE (512)
+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#define APP_SECTION_START (0x0000)
+#define APP_SECTION_SIZE (131072)
+#define APP_SECTION_PAGE_SIZE (512)
+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#define APPTABLE_SECTION_START (0x1E000)
+#define APPTABLE_SECTION_SIZE (8192)
+#define APPTABLE_SECTION_PAGE_SIZE (512)
+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#define BOOT_SECTION_START (0x20000)
+#define BOOT_SECTION_SIZE (8192)
+#define BOOT_SECTION_PAGE_SIZE (512)
+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#define DATAMEM_START (0x0000)
+#define DATAMEM_SIZE (16384)
+#define DATAMEM_PAGE_SIZE (0)
+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#define IO_START (0x0000)
+#define IO_SIZE (4096)
+#define IO_PAGE_SIZE (0)
+#define IO_END (IO_START + IO_SIZE - 1)
+
+#define MAPPED_EEPROM_START (0x1000)
+#define MAPPED_EEPROM_SIZE (2048)
+#define MAPPED_EEPROM_PAGE_SIZE (0)
+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#define INTERNAL_SRAM_START (0x2000)
+#define INTERNAL_SRAM_SIZE (8192)
+#define INTERNAL_SRAM_PAGE_SIZE (0)
+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#define EEPROM_START (0x0000)
+#define EEPROM_SIZE (2048)
+#define EEPROM_PAGE_SIZE (32)
+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+#define FUSE_START (0x0000)
+#define FUSE_SIZE (6)
+#define FUSE_PAGE_SIZE (0)
+#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+
+#define LOCKBIT_START (0x0000)
+#define LOCKBIT_SIZE (1)
+#define LOCKBIT_PAGE_SIZE (0)
+#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
+
+#define SIGNATURES_START (0x0000)
+#define SIGNATURES_SIZE (3)
+#define SIGNATURES_PAGE_SIZE (0)
+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#define USER_SIGNATURES_START (0x0000)
+#define USER_SIGNATURES_SIZE (512)
+#define USER_SIGNATURES_PAGE_SIZE (0)
+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#define PROD_SIGNATURES_START (0x0000)
+#define PROD_SIGNATURES_SIZE (52)
+#define PROD_SIGNATURES_PAGE_SIZE (0)
+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHEND PROGMEM_END
+#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
+#define RAMSTART INTERNAL_SRAM_START
+#define RAMSIZE INTERNAL_SRAM_SIZE
+#define RAMEND INTERNAL_SRAM_END
+#define XRAMSTART EXTERNAL_SRAM_START
+#define XRAMSIZE EXTERNAL_SRAM_SIZE
+#define XRAMEND INTERNAL_SRAM_END
+#define E2END EEPROM_END
+#define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
+#define FUSE0_DEFAULT (0xFF)
+
+/* Fuse Byte 1 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT (0xFF)
+
+/* Fuse Byte 2 */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
+#define FUSE2_DEFAULT (0xFF)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE4_DEFAULT (0xFF)
+
+/* Fuse Byte 5 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT (0xFF)
+
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x48
+
+
+#endif /* _AVR_ATxmega128D3_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iox16a4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox16a4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox16a4.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox16a4.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox16a4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega16A4_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6252,21 +6252,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -6582,49 +6582,49 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_USERID0 ~_BV(0) /* User ID Bit 0 */
-#define FUSE_USERID1 ~_BV(1) /* User ID Bit 1 */
-#define FUSE_USERID2 ~_BV(2) /* User ID Bit 2 */
-#define FUSE_USERID3 ~_BV(3) /* User ID Bit 3 */
-#define FUSE_USERID4 ~_BV(4) /* User ID Bit 4 */
-#define FUSE_USERID5 ~_BV(5) /* User ID Bit 5 */
-#define FUSE_USERID6 ~_BV(6) /* User ID Bit 6 */
-#define FUSE_USERID7 ~_BV(7) /* User ID Bit 7 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iox16d4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox16d4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox16d4.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox16d4.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox16d4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega16D4_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -689,7 +689,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -5219,21 +5219,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -5479,49 +5479,49 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_USERID0 ~_BV(0) /* User ID Bit 0 */
-#define FUSE_USERID1 ~_BV(1) /* User ID Bit 1 */
-#define FUSE_USERID2 ~_BV(2) /* User ID Bit 2 */
-#define FUSE_USERID3 ~_BV(3) /* User ID Bit 3 */
-#define FUSE_USERID4 ~_BV(4) /* User ID Bit 4 */
-#define FUSE_USERID5 ~_BV(5) /* User ID Bit 5 */
-#define FUSE_USERID6 ~_BV(6) /* User ID Bit 6 */
-#define FUSE_USERID7 ~_BV(7) /* User ID Bit 7 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iox192a3.h:1.1
--- /dev/null Mon May 10 12:11:02 2010
+++ rtems/cpukit/score/cpu/avr/avr/iox192a3.h Mon May 10 11:31:23 2010
@@ -0,0 +1,6890 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iox192a3.h - definitions for ATxmega192A3 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iox192a3.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATxmega192A3_H_
+#define _AVR_ATxmega192A3_H_ 1
+
+
+/* Ungrouped common registers */
+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+#define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register16_t regname; \
+ struct \
+ { \
+ register8_t regname ## L; \
+ register8_t regname ## H; \
+ }; \
+ }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register32_t regname; \
+ struct \
+ { \
+ register8_t regname ## 0; \
+ register8_t regname ## 1; \
+ register8_t regname ## 2; \
+ register8_t regname ## 3; \
+ }; \
+ }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+ register8_t OCDR0; /* OCD Register 0 */
+ register8_t OCDR1; /* OCD Register 1 */
+} OCD_t;
+
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
+} CCP_t;
+
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t PSCTRL; /* Prescaler Control Register */
+ register8_t LOCK; /* Lock register */
+ register8_t RTCCTRL; /* RTC Control Register */
+} CLK_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+ register8_t PRGEN; /* General Power Reduction */
+ register8_t PRPA; /* Power Reduction Port A */
+ register8_t PRPB; /* Power Reduction Port B */
+ register8_t PRPC; /* Power Reduction Port C */
+ register8_t PRPD; /* Power Reduction Port D */
+ register8_t PRPE; /* Power Reduction Port E */
+ register8_t PRPF; /* Power Reduction Port F */
+} PR_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
+} CLK_RTCSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+ register8_t CTRL; /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
+ register8_t PLLCTRL; /* PLL Control REgister */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+} OSC_PLLSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t CALA; /* Calibration Register A */
+ register8_t CALB; /* Calibration Register B */
+ register8_t COMP0; /* Oscillator Compare Register 0 */
+ register8_t COMP1; /* Oscillator Compare Register 1 */
+ register8_t COMP2; /* Oscillator Compare Register 2 */
+ register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t CTRL; /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t WINCTRL; /* Windowed Mode Control */
+ register8_t STATUS; /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+ register8_t DEVID0; /* Device ID byte 0 */
+ register8_t DEVID1; /* Device ID byte 1 */
+ register8_t DEVID2; /* Device ID byte 2 */
+ register8_t REVID; /* Revision ID */
+ register8_t JTAGUID; /* JTAG User ID */
+ register8_t reserved_0x05;
+ register8_t MCUCR; /* MCU Control */
+ register8_t reserved_0x07;
+ register8_t EVSYSLOCK; /* Event System Lock */
+ register8_t AWEXLOCK; /* AWEX Lock */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t INTPRI; /* Interrupt Priority */
+ register8_t CTRL; /* Control Register */
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+DMA - DMA Controller
+--------------------------------------------------------------------------
+*/
+
+/* DMA Channel */
+typedef struct DMA_CH_struct
+{
+ register8_t CTRLA; /* Channel Control */
+ register8_t CTRLB; /* Channel Control */
+ register8_t ADDRCTRL; /* Address Control */
+ register8_t TRIGSRC; /* Channel Trigger Source */
+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
+ register8_t REPCNT; /* Channel Repeat Count */
+ register8_t reserved_0x07;
+ register8_t SRCADDR0; /* Channel Source Address 0 */
+ register8_t SRCADDR1; /* Channel Source Address 1 */
+ register8_t SRCADDR2; /* Channel Source Address 2 */
+ register8_t reserved_0x0B;
+ register8_t DESTADDR0; /* Channel Destination Address 0 */
+ register8_t DESTADDR1; /* Channel Destination Address 1 */
+ register8_t DESTADDR2; /* Channel Destination Address 2 */
+ register8_t reserved_0x0F;
+} DMA_CH_t;
+
+/*
+--------------------------------------------------------------------------
+DMA - DMA Controller
+--------------------------------------------------------------------------
+*/
+
+/* DMA Controller */
+typedef struct DMA_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t reserved_0x01;
+ register8_t reserved_0x02;
+ register8_t INTFLAGS; /* Transfer Interrupt Status */
+ register8_t STATUS; /* Status */
+ register8_t reserved_0x05;
+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ DMA_CH_t CH0; /* DMA Channel 0 */
+ DMA_CH_t CH1; /* DMA Channel 1 */
+ DMA_CH_t CH2; /* DMA Channel 2 */
+ DMA_CH_t CH3; /* DMA Channel 3 */
+} DMA_t;
+
+/* Burst mode */
+typedef enum DMA_CH_BURSTLEN_enum
+{
+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
+} DMA_CH_BURSTLEN_t;
+
+/* Source address reload mode */
+typedef enum DMA_CH_SRCRELOAD_enum
+{
+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */
+} DMA_CH_SRCRELOAD_t;
+
+/* Source addressing mode */
+typedef enum DMA_CH_SRCDIR_enum
+{
+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
+} DMA_CH_SRCDIR_t;
+
+/* Destination adress reload mode */
+typedef enum DMA_CH_DESTRELOAD_enum
+{
+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */
+} DMA_CH_DESTRELOAD_t;
+
+/* Destination adressing mode */
+typedef enum DMA_CH_DESTDIR_enum
+{
+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
+} DMA_CH_DESTDIR_t;
+
+/* Transfer trigger source */
+typedef enum DMA_CH_TRIGSRC_enum
+{
+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */
+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */
+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */
+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */
+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */
+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */
+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */
+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */
+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */
+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */
+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */
+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */
+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */
+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */
+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */
+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */
+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */
+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */
+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */
+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */
+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */
+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */
+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */
+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */
+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */
+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */
+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */
+} DMA_CH_TRIGSRC_t;
+
+/* Double buffering mode */
+typedef enum DMA_DBUFMODE_enum
+{
+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */
+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */
+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
+} DMA_DBUFMODE_t;
+
+/* Priority mode */
+typedef enum DMA_PRIMODE_enum
+{
+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */
+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */
+} DMA_PRIMODE_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_ERRINTLVL_enum
+{
+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
+} DMA_CH_ERRINTLVL_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_TRNINTLVL_enum
+{
+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
+} DMA_CH_TRNINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
+ register8_t CH0CTRL; /* Channel 0 Control Register */
+ register8_t CH1CTRL; /* Channel 1 Control Register */
+ register8_t CH2CTRL; /* Channel 2 Control Register */
+ register8_t CH3CTRL; /* Channel 3 Control Register */
+ register8_t CH4CTRL; /* Channel 4 Control Register */
+ register8_t CH5CTRL; /* Channel 5 Control Register */
+ register8_t CH6CTRL; /* Channel 6 Control Register */
+ register8_t CH7CTRL; /* Channel 7 Control Register */
+ register8_t STROBE; /* Event Strobe */
+ register8_t DATA; /* Event Data */
+} EVSYS_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+ register8_t ADDR0; /* Address Register 0 */
+ register8_t ADDR1; /* Address Register 1 */
+ register8_t ADDR2; /* Address Register 2 */
+ register8_t reserved_0x03;
+ register8_t DATA0; /* Data Register 0 */
+ register8_t DATA1; /* Data Register 1 */
+ register8_t DATA2; /* Data Register 2 */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t CMD; /* Command */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t INTCTRL; /* Interrupt Control */
+ register8_t reserved_0x0E;
+ register8_t STATUS; /* Status */
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_LOCKBITS_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+ register8_t FUSEBYTE0; /* JTAG User ID */
+ register8_t FUSEBYTE1; /* Watchdog Configuration */
+ register8_t FUSEBYTE2; /* Reset Configuration */
+ register8_t reserved_0x03;
+ register8_t FUSEBYTE4; /* Start-up Configuration */
+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
+ register8_t reserved_0x01;
+ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
+ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
+ register8_t reserved_0x04;
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t WAFNUM; /* Wafer Number */
+ register8_t reserved_0x11;
+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
+ register8_t reserved_0x26;
+ register8_t reserved_0x27;
+ register8_t reserved_0x28;
+ register8_t reserved_0x29;
+ register8_t reserved_0x2A;
+ register8_t reserved_0x2B;
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
+ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
+ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ register8_t reserved_0x36;
+ register8_t reserved_0x37;
+ register8_t reserved_0x38;
+ register8_t reserved_0x39;
+ register8_t reserved_0x3A;
+ register8_t reserved_0x3B;
+ register8_t reserved_0x3C;
+ register8_t reserved_0x3D;
+ register8_t reserved_0x3E;
+} NVM_PROD_SIGNATURES_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
+} NVM_CMD_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
+} NVM_SPMLVL_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
+} NVM_EELVL_t;
+
+/* Boot lock bits - boot setcion */
+typedef enum NVM_BLBB_enum
+{
+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
+} NVM_BLBB_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
+} NVM_BLBAT_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
+} NVM_LB_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
+} BOOTRST_t;
+
+/* BOD operation */
+typedef enum BOD_enum
+{
+ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
+ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
+} BOD_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WD_enum
+{
+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
+} WD_t;
+
+/* Start-up Time */
+typedef enum SUT_enum
+{
+ SUT_0MS_gc = (0x03<<2), /* 0 ms */
+ SUT_4MS_gc = (0x01<<2), /* 4 ms */
+ SUT_64MS_gc = (0x00<<2), /* 64 ms */
+} SUT_t;
+
+/* Brown Out Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
+ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */
+ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */
+ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */
+ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */
+ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */
+ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */
+} BODLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+ register8_t AC0CTRL; /* Comparator 0 Control */
+ register8_t AC1CTRL; /* Comparator 1 Control */
+ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
+ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t WINCTRL; /* Window Mode Control */
+ register8_t STATUS; /* Status */
+} AC_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
+} AC_INTLVL_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
+} AC_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
+} AC_WINTLVL_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
+} AC_WSTATE_t;
+
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+ register8_t INTCTRL; /* Channel Interrupt Control */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+ register8_t reserved_0x6;
+ register8_t reserved_0x7;
+} ADC_CH_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t REFCTRL; /* Reference Control */
+ register8_t EVCTRL; /* Event Control */
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t CALCTRL; /* Calibration Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ _WORDREGISTER(CAL); /* Calibration Value */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ _WORDREGISTER(CH0RES); /* Channel 0 Result */
+ _WORDREGISTER(CH1RES); /* Channel 1 Result */
+ _WORDREGISTER(CH2RES); /* Channel 2 Result */
+ _WORDREGISTER(CH3RES); /* Channel 3 Result */
+ _WORDREGISTER(CMP); /* Compare Value */
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ ADC_CH_t CH0; /* ADC Channel 0 */
+ ADC_CH_t CH1; /* ADC Channel 1 */
+ ADC_CH_t CH2; /* ADC Channel 2 */
+ ADC_CH_t CH3; /* ADC Channel 3 */
+} ADC_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
+} ADC_CH_MUXPOS_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
+ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
+ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
+ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
+ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
+} ADC_CH_MUXNEG_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+} ADC_CH_GAIN_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
+ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */
+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
+} ADC_REFSEL_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
+} ADC_SWEEP_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */
+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
+ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */
+} ADC_EVACT_t;
+
+/* Interupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
+} ADC_CH_INTLVL_t;
+
+/* DMA request selection */
+typedef enum ADC_DMASEL_enum
+{
+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
+} ADC_DMASEL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+
+/*
+--------------------------------------------------------------------------
+DAC - Digital/Analog Converter
+--------------------------------------------------------------------------
+*/
+
+/* Digital-to-Analog Converter */
+typedef struct DAC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t EVCTRL; /* Event Input Control */
+ register8_t TIMCTRL; /* Timing Control */
+ register8_t STATUS; /* Status */
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t GAINCAL; /* Gain Calibration */
+ register8_t OFFSETCAL; /* Offset Calibration */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
+} DAC_t;
+
+/* Output channel selection */
+typedef enum DAC_CHSEL_enum
+{
+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */
+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */
+} DAC_CHSEL_t;
+
+/* Reference voltage selection */
+typedef enum DAC_REFSEL_enum
+{
+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
+} DAC_REFSEL_t;
+
+/* Event channel selection */
+typedef enum DAC_EVSEL_enum
+{
+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
+} DAC_EVSEL_t;
+
+/* Conversion interval */
+typedef enum DAC_CONINTVAL_enum
+{
+ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
+ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
+ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
+ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
+ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
+ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
+ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
+ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
+} DAC_CONINTVAL_t;
+
+/* Refresh rate */
+typedef enum DAC_REFRESH_enum
+{
+ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
+ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
+ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
+ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
+ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
+ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
+ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
+ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
+ DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
+ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
+ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
+ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
+ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
+ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
+} DAC_REFRESH_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Clounter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ _WORDREGISTER(CNT); /* Count Register */
+ _WORDREGISTER(PER); /* Period Register */
+ _WORDREGISTER(COMP); /* Compare Register */
+} RTC_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} RTC_OVFINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+ register8_t CTRLA; /* Chip Select Control Register A */
+ register8_t CTRLB; /* Chip Select Control Register B */
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+} EBI_CS_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t SDRAMCTRLA; /* SDRAM Control Register A */
+ register8_t reserved_0x02;
+ register8_t reserved_0x03;
+ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
+ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
+ register8_t SDRAMCTRLB; /* SDRAM Control Register B */
+ register8_t SDRAMCTRLC; /* SDRAM Control Register C */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ EBI_CS_t CS0; /* Chip Select 0 */
+ EBI_CS_t CS1; /* Chip Select 1 */
+ EBI_CS_t CS2; /* Chip Select 2 */
+ EBI_CS_t CS3; /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select adress space */
+typedef enum EBI_CS_ASPACE_enum
+{
+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* */
+typedef enum EBI_CS_SRWS_enum
+{
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
+ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
+ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
+ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
+ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* */
+typedef enum EBI_SDDATAW_enum
+{
+ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
+ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/* */
+typedef enum EBI_LPCMODE_enum
+{
+ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
+ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* */
+typedef enum EBI_SRMODE_enum
+{
+ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
+ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
+ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
+ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* */
+typedef enum EBI_IFMODE_enum
+{
+ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
+ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
+ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
+ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
+} EBI_IFMODE_t;
+
+/* */
+typedef enum EBI_SDCOL_enum
+{
+ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
+ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
+ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+} EBI_SDCOL_t;
+
+/* */
+typedef enum EBI_MRDLY_enum
+{
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* */
+typedef enum EBI_ROWCYCDLY_enum
+{
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* */
+typedef enum EBI_RPDLY_enum
+{
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_RPDLY_t;
+
+/* */
+typedef enum EBI_WRDLY_enum
+{
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_WRDLY_t;
+
+/* */
+typedef enum EBI_ESRDLY_enum
+{
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/* */
+typedef enum EBI_ROWCOLDLY_enum
+{
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_MASTER_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t STATUS; /* Status Register */
+ register8_t BAUD; /* Baurd Rate Control Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+} TWI_MASTER_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_SLAVE_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+ register8_t ADDRMASK; /* Address Mask Register */
+} TWI_SLAVE_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+ register8_t CTRL; /* TWI Common Control Register */
+ TWI_MASTER_t MASTER; /* TWI master module */
+ TWI_SLAVE_t SLAVE; /* TWI slave module */
+} TWI_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+ register8_t MPCMASK; /* Multi-pin Configuration Mask */
+ register8_t reserved_0x01;
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
+} PORTCFG_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t OUT; /* I/O Port Output */
+ register8_t IN; /* I/O Port Input */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+} VPORT_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t DIRSET; /* I/O Port Data Direction Set */
+ register8_t DIRCLR; /* I/O Port Data Direction Clear */
+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
+ register8_t OUT; /* I/O Port Output */
+ register8_t OUTSET; /* I/O Port Output Set */
+ register8_t OUTCLR; /* I/O Port Output Clear */
+ register8_t OUTTGL; /* I/O Port Output Toggle */
+ register8_t IN; /* I/O port Input */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INT0MASK; /* Port Interrupt 0 Mask */
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+ register8_t PIN2CTRL; /* Pin 2 Control Register */
+ register8_t PIN3CTRL; /* Pin 3 Control Register */
+ register8_t PIN4CTRL; /* Pin 4 Control Register */
+ register8_t PIN5CTRL; /* Pin 5 Control Register */
+ register8_t PIN6CTRL; /* Pin 6 Control Register */
+ register8_t PIN7CTRL; /* Pin 7 Control Register */
+} PORT_t;
+
+/* Virtual Port 0 Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Virtual Port 1 Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Virtual Port 2 Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port 3 Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/* Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
+} PORT_INT1LVL_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ _WORDREGISTER(CCC); /* Compare or Capture C */
+ _WORDREGISTER(CCD); /* Compare or Capture D */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+} TC0_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t FDEVMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x05;
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+ register8_t DTHS; /* Dead Time High Side */
+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
+ register8_t DTHSBUF; /* Dead Time High Side Buffer */
+ register8_t OUTOVEN; /* Output Override Enable */
+} AWEX_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+ register8_t CTRL; /* Control Register */
+} HIRES_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
+ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */
+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+ register8_t DATA; /* Data Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
+} USART_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
+} USART_TXCINTLVL_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
+} USART_DREINTLVL_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
+} USART_PMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t DATA; /* Data Register */
+} SPI_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} SPI_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRDA_EVSEL_enum
+{
+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
+} IRDA_EVSEL_t;
+
+
+/*
+--------------------------------------------------------------------------
+AES - AES Module
+--------------------------------------------------------------------------
+*/
+
+/* AES Module */
+typedef struct AES_struct
+{
+ register8_t CTRL; /* AES Control Register */
+ register8_t STATUS; /* AES Status Register */
+ register8_t STATE; /* AES State Register */
+ register8_t KEY; /* AES Key Register */
+ register8_t INTCTRL; /* AES Interrupt Control Register */
+} AES_t;
+
+/* Interrupt level */
+typedef enum AES_INTLVL_enum
+{
+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} AES_INTLVL_t;
+
+
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
+#define CLK (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
+#define PR (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST (*(RST_t *) 0x0078) /* Reset Controller */
+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
+#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
+#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */
+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */
+#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */
+#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */
+
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIO0 _SFR_MEM8(0x0000)
+#define GPIO_GPIO1 _SFR_MEM8(0x0001)
+#define GPIO_GPIO2 _SFR_MEM8(0x0002)
+#define GPIO_GPIO3 _SFR_MEM8(0x0003)
+#define GPIO_GPIO4 _SFR_MEM8(0x0004)
+#define GPIO_GPIO5 _SFR_MEM8(0x0005)
+#define GPIO_GPIO6 _SFR_MEM8(0x0006)
+#define GPIO_GPIO7 _SFR_MEM8(0x0007)
+#define GPIO_GPIO8 _SFR_MEM8(0x0008)
+#define GPIO_GPIO9 _SFR_MEM8(0x0009)
+#define GPIO_GPIOA _SFR_MEM8(0x000A)
+#define GPIO_GPIOB _SFR_MEM8(0x000B)
+#define GPIO_GPIOC _SFR_MEM8(0x000C)
+#define GPIO_GPIOD _SFR_MEM8(0x000D)
+#define GPIO_GPIOE _SFR_MEM8(0x000E)
+#define GPIO_GPIOF _SFR_MEM8(0x000F)
+
+/* VPORT0 - Virtual Port 0 */
+#define VPORT0_DIR _SFR_MEM8(0x0010)
+#define VPORT0_OUT _SFR_MEM8(0x0011)
+#define VPORT0_IN _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+/* VPORT1 - Virtual Port 1 */
+#define VPORT1_DIR _SFR_MEM8(0x0014)
+#define VPORT1_OUT _SFR_MEM8(0x0015)
+#define VPORT1_IN _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+/* VPORT2 - Virtual Port 2 */
+#define VPORT2_DIR _SFR_MEM8(0x0018)
+#define VPORT2_OUT _SFR_MEM8(0x0019)
+#define VPORT2_IN _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+/* VPORT3 - Virtual Port 3 */
+#define VPORT3_DIR _SFR_MEM8(0x001C)
+#define VPORT3_OUT _SFR_MEM8(0x001D)
+#define VPORT3_IN _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0 _SFR_MEM8(0x002E)
+#define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+/* CPU - CPU Registers */
+#define CPU_CCP _SFR_MEM8(0x0034)
+#define CPU_RAMPD _SFR_MEM8(0x0038)
+#define CPU_RAMPX _SFR_MEM8(0x0039)
+#define CPU_RAMPY _SFR_MEM8(0x003A)
+#define CPU_RAMPZ _SFR_MEM8(0x003B)
+#define CPU_EIND _SFR_MEM8(0x003C)
+#define CPU_SPL _SFR_MEM8(0x003D)
+#define CPU_SPH _SFR_MEM8(0x003E)
+#define CPU_SREG _SFR_MEM8(0x003F)
+
+/* CLK - Clock System */
+#define CLK_CTRL _SFR_MEM8(0x0040)
+#define CLK_PSCTRL _SFR_MEM8(0x0041)
+#define CLK_LOCK _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL _SFR_MEM8(0x0043)
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+/* OSC - Oscillator Control */
+#define OSC_CTRL _SFR_MEM8(0x0050)
+#define OSC_STATUS _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+
+/* PR - Power Reduction */
+#define PR_PRGEN _SFR_MEM8(0x0070)
+#define PR_PRPA _SFR_MEM8(0x0071)
+#define PR_PRPB _SFR_MEM8(0x0072)
+#define PR_PRPC _SFR_MEM8(0x0073)
+#define PR_PRPD _SFR_MEM8(0x0074)
+#define PR_PRPE _SFR_MEM8(0x0075)
+#define PR_PRPF _SFR_MEM8(0x0076)
+
+/* RST - Reset Controller */
+#define RST_STATUS _SFR_MEM8(0x0078)
+#define RST_CTRL _SFR_MEM8(0x0079)
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL _SFR_MEM8(0x0080)
+#define WDT_WINCTRL _SFR_MEM8(0x0081)
+#define WDT_STATUS _SFR_MEM8(0x0082)
+
+/* MCU - MCU Control */
+#define MCU_DEVID0 _SFR_MEM8(0x0090)
+#define MCU_DEVID1 _SFR_MEM8(0x0091)
+#define MCU_DEVID2 _SFR_MEM8(0x0092)
+#define MCU_REVID _SFR_MEM8(0x0093)
+#define MCU_JTAGUID _SFR_MEM8(0x0094)
+#define MCU_MCUCR _SFR_MEM8(0x0096)
+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+/* PMIC - Programmable Interrupt Controller */
+#define PMIC_STATUS _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI _SFR_MEM8(0x00A1)
+#define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+/* PORTCFG - Port Configuration */
+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+
+/* AES - AES Crypto Module */
+#define AES_CTRL _SFR_MEM8(0x00C0)
+#define AES_STATUS _SFR_MEM8(0x00C1)
+#define AES_STATE _SFR_MEM8(0x00C2)
+#define AES_KEY _SFR_MEM8(0x00C3)
+#define AES_INTCTRL _SFR_MEM8(0x00C4)
+
+/* DMA - DMA Controller */
+#define DMA_CTRL _SFR_MEM8(0x0100)
+#define DMA_INTFLAGS _SFR_MEM8(0x0103)
+#define DMA_STATUS _SFR_MEM8(0x0104)
+#define DMA_TEMP _SFR_MEM16(0x0106)
+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
+#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
+#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
+#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
+#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
+#define EVSYS_STROBE _SFR_MEM8(0x0190)
+#define EVSYS_DATA _SFR_MEM8(0x0191)
+
+/* NVM - Non Volatile Memory Controller */
+#define NVM_ADDR0 _SFR_MEM8(0x01C0)
+#define NVM_ADDR1 _SFR_MEM8(0x01C1)
+#define NVM_ADDR2 _SFR_MEM8(0x01C2)
+#define NVM_DATA0 _SFR_MEM8(0x01C4)
+#define NVM_DATA1 _SFR_MEM8(0x01C5)
+#define NVM_DATA2 _SFR_MEM8(0x01C6)
+#define NVM_CMD _SFR_MEM8(0x01CA)
+#define NVM_CTRLA _SFR_MEM8(0x01CB)
+#define NVM_CTRLB _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL _SFR_MEM8(0x01CD)
+#define NVM_STATUS _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+/* ADCA - Analog to Digital Converter A */
+#define ADCA_CTRLA _SFR_MEM8(0x0200)
+#define ADCA_CTRLB _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER _SFR_MEM8(0x0204)
+#define ADCA_CALCTRL _SFR_MEM8(0x0205)
+#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
+#define ADCA_CAL _SFR_MEM16(0x020C)
+#define ADCA_CH0RES _SFR_MEM16(0x0210)
+#define ADCA_CH1RES _SFR_MEM16(0x0212)
+#define ADCA_CH2RES _SFR_MEM16(0x0214)
+#define ADCA_CH3RES _SFR_MEM16(0x0216)
+#define ADCA_CMP _SFR_MEM16(0x0218)
+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES _SFR_MEM16(0x0224)
+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
+#define ADCA_CH1_RES _SFR_MEM16(0x022C)
+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
+#define ADCA_CH2_RES _SFR_MEM16(0x0234)
+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
+#define ADCA_CH3_RES _SFR_MEM16(0x023C)
+
+/* ADCB - Analog to Digital Converter B */
+#define ADCB_CTRLA _SFR_MEM8(0x0240)
+#define ADCB_CTRLB _SFR_MEM8(0x0241)
+#define ADCB_REFCTRL _SFR_MEM8(0x0242)
+#define ADCB_EVCTRL _SFR_MEM8(0x0243)
+#define ADCB_PRESCALER _SFR_MEM8(0x0244)
+#define ADCB_CALCTRL _SFR_MEM8(0x0245)
+#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
+#define ADCB_CAL _SFR_MEM16(0x024C)
+#define ADCB_CH0RES _SFR_MEM16(0x0250)
+#define ADCB_CH1RES _SFR_MEM16(0x0252)
+#define ADCB_CH2RES _SFR_MEM16(0x0254)
+#define ADCB_CH3RES _SFR_MEM16(0x0256)
+#define ADCB_CMP _SFR_MEM16(0x0258)
+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
+#define ADCB_CH0_RES _SFR_MEM16(0x0264)
+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
+#define ADCB_CH1_RES _SFR_MEM16(0x026C)
+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
+#define ADCB_CH2_RES _SFR_MEM16(0x0274)
+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
+#define ADCB_CH3_RES _SFR_MEM16(0x027C)
+
+/* DACB - Digital to Analog Converter B */
+#define DACB_CTRLA _SFR_MEM8(0x0320)
+#define DACB_CTRLB _SFR_MEM8(0x0321)
+#define DACB_CTRLC _SFR_MEM8(0x0322)
+#define DACB_EVCTRL _SFR_MEM8(0x0323)
+#define DACB_TIMCTRL _SFR_MEM8(0x0324)
+#define DACB_STATUS _SFR_MEM8(0x0325)
+#define DACB_GAINCAL _SFR_MEM8(0x0328)
+#define DACB_OFFSETCAL _SFR_MEM8(0x0329)
+#define DACB_CH0DATA _SFR_MEM16(0x0338)
+#define DACB_CH1DATA _SFR_MEM16(0x033A)
+
+/* ACA - Analog Comparator A */
+#define ACA_AC0CTRL _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
+#define ACA_CTRLA _SFR_MEM8(0x0384)
+#define ACA_CTRLB _SFR_MEM8(0x0385)
+#define ACA_WINCTRL _SFR_MEM8(0x0386)
+#define ACA_STATUS _SFR_MEM8(0x0387)
+
+/* ACB - Analog Comparator B */
+#define ACB_AC0CTRL _SFR_MEM8(0x0390)
+#define ACB_AC1CTRL _SFR_MEM8(0x0391)
+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
+#define ACB_CTRLA _SFR_MEM8(0x0394)
+#define ACB_CTRLB _SFR_MEM8(0x0395)
+#define ACB_WINCTRL _SFR_MEM8(0x0396)
+#define ACB_STATUS _SFR_MEM8(0x0397)
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL _SFR_MEM8(0x0400)
+#define RTC_STATUS _SFR_MEM8(0x0401)
+#define RTC_INTCTRL _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS _SFR_MEM8(0x0403)
+#define RTC_TEMP _SFR_MEM8(0x0404)
+#define RTC_CNT _SFR_MEM16(0x0408)
+#define RTC_PER _SFR_MEM16(0x040A)
+#define RTC_COMP _SFR_MEM16(0x040C)
+
+/* TWIC - Two-Wire Interface C */
+#define TWIC_CTRL _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+/* TWIE - Two-Wire Interface E */
+#define TWIE_CTRL _SFR_MEM8(0x04A0)
+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
+
+/* PORTA - Port A */
+#define PORTA_DIR _SFR_MEM8(0x0600)
+#define PORTA_DIRSET _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL _SFR_MEM8(0x0603)
+#define PORTA_OUT _SFR_MEM8(0x0604)
+#define PORTA_OUTSET _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL _SFR_MEM8(0x0607)
+#define PORTA_IN _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+/* PORTB - Port B */
+#define PORTB_DIR _SFR_MEM8(0x0620)
+#define PORTB_DIRSET _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL _SFR_MEM8(0x0623)
+#define PORTB_OUT _SFR_MEM8(0x0624)
+#define PORTB_OUTSET _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL _SFR_MEM8(0x0627)
+#define PORTB_IN _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+/* PORTC - Port C */
+#define PORTC_DIR _SFR_MEM8(0x0640)
+#define PORTC_DIRSET _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL _SFR_MEM8(0x0643)
+#define PORTC_OUT _SFR_MEM8(0x0644)
+#define PORTC_OUTSET _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL _SFR_MEM8(0x0647)
+#define PORTC_IN _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+/* PORTD - Port D */
+#define PORTD_DIR _SFR_MEM8(0x0660)
+#define PORTD_DIRSET _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL _SFR_MEM8(0x0663)
+#define PORTD_OUT _SFR_MEM8(0x0664)
+#define PORTD_OUTSET _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL _SFR_MEM8(0x0667)
+#define PORTD_IN _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+/* PORTE - Port E */
+#define PORTE_DIR _SFR_MEM8(0x0680)
+#define PORTE_DIRSET _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL _SFR_MEM8(0x0683)
+#define PORTE_OUT _SFR_MEM8(0x0684)
+#define PORTE_OUTSET _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL _SFR_MEM8(0x0687)
+#define PORTE_IN _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+/* PORTF - Port F */
+#define PORTF_DIR _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
+#define PORTF_OUT _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
+#define PORTF_IN _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+/* PORTR - Port R */
+#define PORTR_DIR _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
+#define PORTR_OUT _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
+#define PORTR_IN _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+/* TCC0 - Timer/Counter C0 */
+#define TCC0_CTRLA _SFR_MEM8(0x0800)
+#define TCC0_CTRLB _SFR_MEM8(0x0801)
+#define TCC0_CTRLC _SFR_MEM8(0x0802)
+#define TCC0_CTRLD _SFR_MEM8(0x0803)
+#define TCC0_CTRLE _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
+#define TCC0_TEMP _SFR_MEM8(0x080F)
+#define TCC0_CNT _SFR_MEM16(0x0820)
+#define TCC0_PER _SFR_MEM16(0x0826)
+#define TCC0_CCA _SFR_MEM16(0x0828)
+#define TCC0_CCB _SFR_MEM16(0x082A)
+#define TCC0_CCC _SFR_MEM16(0x082C)
+#define TCC0_CCD _SFR_MEM16(0x082E)
+#define TCC0_PERBUF _SFR_MEM16(0x0836)
+#define TCC0_CCABUF _SFR_MEM16(0x0838)
+#define TCC0_CCBBUF _SFR_MEM16(0x083A)
+#define TCC0_CCCBUF _SFR_MEM16(0x083C)
+#define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+/* TCC1 - Timer/Counter C1 */
+#define TCC1_CTRLA _SFR_MEM8(0x0840)
+#define TCC1_CTRLB _SFR_MEM8(0x0841)
+#define TCC1_CTRLC _SFR_MEM8(0x0842)
+#define TCC1_CTRLD _SFR_MEM8(0x0843)
+#define TCC1_CTRLE _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
+#define TCC1_TEMP _SFR_MEM8(0x084F)
+#define TCC1_CNT _SFR_MEM16(0x0860)
+#define TCC1_PER _SFR_MEM16(0x0866)
+#define TCC1_CCA _SFR_MEM16(0x0868)
+#define TCC1_CCB _SFR_MEM16(0x086A)
+#define TCC1_PERBUF _SFR_MEM16(0x0876)
+#define TCC1_CCABUF _SFR_MEM16(0x0878)
+#define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+/* AWEXC - Advanced Waveform Extension C */
+#define AWEXC_CTRL _SFR_MEM8(0x0880)
+#define AWEXC_FDEVMASK _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+#define AWEXC_STATUS _SFR_MEM8(0x0884)
+#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+#define AWEXC_DTLS _SFR_MEM8(0x0888)
+#define AWEXC_DTHS _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+/* HIRESC - High-Resolution Extension C */
+#define HIRESC_CTRL _SFR_MEM8(0x0890)
+
+/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0_DATA _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
+#define USARTC1_DATA _SFR_MEM8(0x08B0)
+#define USARTC1_STATUS _SFR_MEM8(0x08B1)
+#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
+#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
+#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
+
+/* SPIC - Serial Peripheral Interface C */
+#define SPIC_CTRL _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+#define SPIC_STATUS _SFR_MEM8(0x08C2)
+#define SPIC_DATA _SFR_MEM8(0x08C3)
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_CTRL _SFR_MEM8(0x08F8)
+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
+
+/* TCD0 - Timer/Counter D0 */
+#define TCD0_CTRLA _SFR_MEM8(0x0900)
+#define TCD0_CTRLB _SFR_MEM8(0x0901)
+#define TCD0_CTRLC _SFR_MEM8(0x0902)
+#define TCD0_CTRLD _SFR_MEM8(0x0903)
+#define TCD0_CTRLE _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
+#define TCD0_TEMP _SFR_MEM8(0x090F)
+#define TCD0_CNT _SFR_MEM16(0x0920)
+#define TCD0_PER _SFR_MEM16(0x0926)
+#define TCD0_CCA _SFR_MEM16(0x0928)
+#define TCD0_CCB _SFR_MEM16(0x092A)
+#define TCD0_CCC _SFR_MEM16(0x092C)
+#define TCD0_CCD _SFR_MEM16(0x092E)
+#define TCD0_PERBUF _SFR_MEM16(0x0936)
+#define TCD0_CCABUF _SFR_MEM16(0x0938)
+#define TCD0_CCBBUF _SFR_MEM16(0x093A)
+#define TCD0_CCCBUF _SFR_MEM16(0x093C)
+#define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+/* TCD1 - Timer/Counter D1 */
+#define TCD1_CTRLA _SFR_MEM8(0x0940)
+#define TCD1_CTRLB _SFR_MEM8(0x0941)
+#define TCD1_CTRLC _SFR_MEM8(0x0942)
+#define TCD1_CTRLD _SFR_MEM8(0x0943)
+#define TCD1_CTRLE _SFR_MEM8(0x0944)
+#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
+#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
+#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
+#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
+#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
+#define TCD1_TEMP _SFR_MEM8(0x094F)
+#define TCD1_CNT _SFR_MEM16(0x0960)
+#define TCD1_PER _SFR_MEM16(0x0966)
+#define TCD1_CCA _SFR_MEM16(0x0968)
+#define TCD1_CCB _SFR_MEM16(0x096A)
+#define TCD1_PERBUF _SFR_MEM16(0x0976)
+#define TCD1_CCABUF _SFR_MEM16(0x0978)
+#define TCD1_CCBBUF _SFR_MEM16(0x097A)
+
+/* HIRESD - High-Resolution Extension D */
+#define HIRESD_CTRL _SFR_MEM8(0x0990)
+
+/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0_DATA _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
+#define USARTD1_DATA _SFR_MEM8(0x09B0)
+#define USARTD1_STATUS _SFR_MEM8(0x09B1)
+#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
+#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
+#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
+
+/* SPID - Serial Peripheral Interface D */
+#define SPID_CTRL _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL _SFR_MEM8(0x09C1)
+#define SPID_STATUS _SFR_MEM8(0x09C2)
+#define SPID_DATA _SFR_MEM8(0x09C3)
+
+/* TCE0 - Timer/Counter E0 */
+#define TCE0_CTRLA _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP _SFR_MEM8(0x0A0F)
+#define TCE0_CNT _SFR_MEM16(0x0A20)
+#define TCE0_PER _SFR_MEM16(0x0A26)
+#define TCE0_CCA _SFR_MEM16(0x0A28)
+#define TCE0_CCB _SFR_MEM16(0x0A2A)
+#define TCE0_CCC _SFR_MEM16(0x0A2C)
+#define TCE0_CCD _SFR_MEM16(0x0A2E)
+#define TCE0_PERBUF _SFR_MEM16(0x0A36)
+#define TCE0_CCABUF _SFR_MEM16(0x0A38)
+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+/* TCE1 - Timer/Counter E1 */
+#define TCE1_CTRLA _SFR_MEM8(0x0A40)
+#define TCE1_CTRLB _SFR_MEM8(0x0A41)
+#define TCE1_CTRLC _SFR_MEM8(0x0A42)
+#define TCE1_CTRLD _SFR_MEM8(0x0A43)
+#define TCE1_CTRLE _SFR_MEM8(0x0A44)
+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
+#define TCE1_TEMP _SFR_MEM8(0x0A4F)
+#define TCE1_CNT _SFR_MEM16(0x0A60)
+#define TCE1_PER _SFR_MEM16(0x0A66)
+#define TCE1_CCA _SFR_MEM16(0x0A68)
+#define TCE1_CCB _SFR_MEM16(0x0A6A)
+#define TCE1_PERBUF _SFR_MEM16(0x0A76)
+#define TCE1_CCABUF _SFR_MEM16(0x0A78)
+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
+
+/* AWEXE - Advanced Waveform Extension E */
+#define AWEXE_CTRL _SFR_MEM8(0x0A80)
+#define AWEXE_FDEVMASK _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS _SFR_MEM8(0x0A84)
+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+/* HIRESE - High-Resolution Extension E */
+#define HIRESE_CTRL _SFR_MEM8(0x0A90)
+
+/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0_DATA _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
+#define USARTE1_DATA _SFR_MEM8(0x0AB0)
+#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
+#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
+#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
+#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
+#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
+#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
+
+/* SPIE - Serial Peripheral Interface E */
+#define SPIE_CTRL _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS _SFR_MEM8(0x0AC2)
+#define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+/* TCF0 - Timer/Counter F0 */
+#define TCF0_CTRLA _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP _SFR_MEM8(0x0B0F)
+#define TCF0_CNT _SFR_MEM16(0x0B20)
+#define TCF0_PER _SFR_MEM16(0x0B26)
+#define TCF0_CCA _SFR_MEM16(0x0B28)
+#define TCF0_CCB _SFR_MEM16(0x0B2A)
+#define TCF0_CCC _SFR_MEM16(0x0B2C)
+#define TCF0_CCD _SFR_MEM16(0x0B2E)
+#define TCF0_PERBUF _SFR_MEM16(0x0B36)
+#define TCF0_CCABUF _SFR_MEM16(0x0B38)
+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+/* HIRESF - High-Resolution Extension F */
+#define HIRESF_CTRL _SFR_MEM8(0x0B90)
+
+/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
+#define USARTF0_DATA _SFR_MEM8(0x0BA0)
+#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
+
+/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
+#define USARTF1_DATA _SFR_MEM8(0x0BB0)
+#define USARTF1_STATUS _SFR_MEM8(0x0BB1)
+#define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
+#define USARTF1_CTRLB _SFR_MEM8(0x0BB4)
+#define USARTF1_CTRLC _SFR_MEM8(0x0BB5)
+#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
+#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)
+
+/* SPIF - Serial Peripheral Interface F */
+#define SPIF_CTRL _SFR_MEM8(0x0BC0)
+#define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
+#define SPIF_STATUS _SFR_MEM8(0x0BC2)
+#define SPIF_DATA _SFR_MEM8(0x0BC3)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR1 bit masks and bit positions */
+#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+
+/* CPU - CPU */
+/* CPU.CCP bit masks and bit positions */
+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+#define CPU_CCP_gp 0 /* CCP signature group position. */
+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+
+/* CPU.SREG bit masks and bit positions */
+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+
+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
+#define CPU_T_bp 6 /* Transfer Bit bit position. */
+
+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
+#define CPU_H_bp 5 /* Half Carry Flag bit position. */
+
+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
+
+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
+
+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
+#define CPU_N_bp 2 /* Negative Flag bit position. */
+
+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
+#define CPU_Z_bp 1 /* Zero Flag bit position. */
+
+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+#define CPU_C_bp 0 /* Carry Flag bit position. */
+
+
+/* CLK - Clock System */
+/* CLK.CTRL bit masks and bit positions */
+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+
+/* CLK.PSCTRL bit masks and bit positions */
+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
+
+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+
+/* CLK.LOCK bit masks and bit positions */
+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+
+/* CLK.RTCCTRL bit masks and bit positions */
+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
+
+#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
+
+
+/* PR.PRGEN bit masks and bit positions */
+#define PR_AES_bm 0x10 /* AES bit mask. */
+#define PR_AES_bp 4 /* AES bit position. */
+
+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
+#define PR_EBI_bp 3 /* External Bus Interface bit position. */
+
+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
+#define PR_RTC_bp 2 /* Real-time Counter bit position. */
+
+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
+#define PR_EVSYS_bp 1 /* Event System bit position. */
+
+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
+#define PR_DMA_bp 0 /* DMA-Controller bit position. */
+
+
+/* PR.PRPA bit masks and bit positions */
+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
+#define PR_DAC_bp 2 /* Port A DAC bit position. */
+
+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
+#define PR_ADC_bp 1 /* Port A ADC bit position. */
+
+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+
+/* PR.PRPB bit masks and bit positions */
+/* PR_DAC_bm Predefined. */
+/* PR_DAC_bp Predefined. */
+
+/* PR_ADC_bm Predefined. */
+/* PR_ADC_bp Predefined. */
+
+/* PR_AC_bm Predefined. */
+/* PR_AC_bp Predefined. */
+
+
+/* PR.PRPC bit masks and bit positions */
+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
+
+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
+#define PR_USART1_bp 5 /* Port C USART1 bit position. */
+
+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
+#define PR_USART0_bp 4 /* Port C USART0 bit position. */
+
+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
+#define PR_SPI_bp 3 /* Port C SPI bit position. */
+
+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+
+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
+
+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+
+/* PR.PRPD bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPE bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPF bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL bit masks and bit positions */
+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
+
+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+
+/* OSC - Oscillator */
+/* OSC.CTRL bit masks and bit positions */
+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
+
+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
+
+#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
+
+#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
+
+#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
+
+
+/* OSC.STATUS bit masks and bit positions */
+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+
+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
+
+#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
+
+#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
+
+#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
+
+
+/* OSC.XOSCCTRL bit masks and bit positions */
+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
+
+#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
+
+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+
+/* OSC.XOSCFAIL bit masks and bit positions */
+#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
+
+#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
+
+
+/* OSC.PLLCTRL bit masks and bit positions */
+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+
+/* OSC.DFLLCTRL bit masks and bit positions */
+#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
+#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
+
+#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL bit masks and bit positions */
+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+
+/* DFLL.CALA bit masks and bit positions */
+#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
+#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
+#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
+#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
+#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
+#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
+#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
+#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
+#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
+
+
+/* DFLL.CALB bit masks and bit positions */
+#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
+#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
+#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
+#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
+#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
+#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
+#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
+#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
+
+
+/* RST - Reset */
+/* RST.STATUS bit masks and bit positions */
+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
+
+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
+
+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
+
+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
+
+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
+
+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
+
+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+
+/* RST.CTRL bit masks and bit positions */
+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+#define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL bit masks and bit positions */
+#define WDT_PER_gm 0x3C /* Period group mask. */
+#define WDT_PER_gp 2 /* Period group position. */
+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
+#define WDT_PER0_bp 2 /* Period bit 0 position. */
+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
+#define WDT_PER1_bp 3 /* Period bit 1 position. */
+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
+#define WDT_PER2_bp 4 /* Period bit 2 position. */
+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
+#define WDT_PER3_bp 5 /* Period bit 3 position. */
+
+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
+#define WDT_ENABLE_bp 1 /* Enable bit position. */
+
+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+#define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+
+/* WDT.WINCTRL bit masks and bit positions */
+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
+
+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
+
+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+
+/* WDT.STATUS bit masks and bit positions */
+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR bit masks and bit positions */
+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+
+/* MCU.EVSYSLOCK bit masks and bit positions */
+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
+
+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+
+/* MCU.AWEXLOCK bit masks and bit positions */
+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS bit masks and bit positions */
+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
+
+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
+
+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
+
+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+
+/* PMIC.CTRL bit masks and bit positions */
+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+
+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
+
+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
+
+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
+
+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+
+/* DMA - DMA Controller */
+/* DMA_CH.CTRLA bit masks and bit positions */
+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */
+
+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */
+
+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */
+
+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */
+
+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */
+
+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */
+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */
+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */
+
+
+/* DMA_CH.CTRLB bit masks and bit positions */
+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */
+
+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */
+
+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */
+
+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */
+
+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */
+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */
+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */
+
+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */
+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */
+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */
+
+
+/* DMA_CH.ADDRCTRL bit masks and bit positions */
+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */
+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */
+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */
+
+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */
+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */
+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */
+
+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */
+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */
+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */
+
+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */
+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */
+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */
+
+
+/* DMA_CH.TRIGSRC bit masks and bit positions */
+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */
+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */
+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */
+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */
+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */
+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */
+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */
+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */
+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */
+
+
+/* DMA.CTRL bit masks and bit positions */
+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
+#define DMA_ENABLE_bp 7 /* Enable bit position. */
+
+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
+#define DMA_RESET_bp 6 /* Software Reset bit position. */
+
+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */
+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */
+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */
+
+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */
+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */
+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */
+
+
+/* DMA.INTFLAGS bit masks and bit positions */
+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
+
+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
+
+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
+
+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
+
+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */
+
+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */
+
+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */
+
+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */
+
+
+/* DMA.STATUS bit masks and bit positions */
+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */
+
+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */
+
+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */
+
+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */
+
+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */
+
+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */
+
+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */
+
+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */
+
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX bit masks and bit positions */
+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+
+/* EVSYS.CH1MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH2MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH3MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH4MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH5MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH6MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH7MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH0CTRL bit masks and bit positions */
+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
+
+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
+
+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+
+/* EVSYS.CH1CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH2CTRL bit masks and bit positions */
+/* EVSYS_QDIRM_gm Predefined. */
+/* EVSYS_QDIRM_gp Predefined. */
+/* EVSYS_QDIRM0_bm Predefined. */
+/* EVSYS_QDIRM0_bp Predefined. */
+/* EVSYS_QDIRM1_bm Predefined. */
+/* EVSYS_QDIRM1_bp Predefined. */
+
+/* EVSYS_QDIEN_bm Predefined. */
+/* EVSYS_QDIEN_bp Predefined. */
+
+/* EVSYS_QDEN_bm Predefined. */
+/* EVSYS_QDEN_bp Predefined. */
+
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH3CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH4CTRL bit masks and bit positions */
+/* EVSYS_QDIRM_gm Predefined. */
+/* EVSYS_QDIRM_gp Predefined. */
+/* EVSYS_QDIRM0_bm Predefined. */
+/* EVSYS_QDIRM0_bp Predefined. */
+/* EVSYS_QDIRM1_bm Predefined. */
+/* EVSYS_QDIRM1_bp Predefined. */
+
+/* EVSYS_QDIEN_bm Predefined. */
+/* EVSYS_QDIEN_bp Predefined. */
+
+/* EVSYS_QDEN_bm Predefined. */
+/* EVSYS_QDEN_bp Predefined. */
+
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH5CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH6CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH7CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD bit masks and bit positions */
+#define NVM_CMD_gm 0xFF /* Command group mask. */
+#define NVM_CMD_gp 0 /* Command group position. */
+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define NVM_CMD0_bp 0 /* Command bit 0 position. */
+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define NVM_CMD1_bp 1 /* Command bit 1 position. */
+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
+#define NVM_CMD2_bp 2 /* Command bit 2 position. */
+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
+#define NVM_CMD3_bp 3 /* Command bit 3 position. */
+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
+#define NVM_CMD4_bp 4 /* Command bit 4 position. */
+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
+#define NVM_CMD5_bp 5 /* Command bit 5 position. */
+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+#define NVM_CMD6_bp 6 /* Command bit 6 position. */
+#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
+#define NVM_CMD7_bp 7 /* Command bit 7 position. */
+
+
+/* NVM.CTRLA bit masks and bit positions */
+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+
+/* NVM.CTRLB bit masks and bit positions */
+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+
+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
+
+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
+
+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+
+/* NVM.INTCTRL bit masks and bit positions */
+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
+
+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+
+/* NVM.STATUS bit masks and bit positions */
+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+
+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
+
+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
+
+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+
+/* NVM.LOCKBITS bit masks and bit positions */
+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */
+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */
+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */
+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */
+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */
+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */
+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */
+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */
+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */
+
+
+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
+
+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
+
+
+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
+#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
+#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
+
+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
+
+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
+
+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
+
+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */
+
+
+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
+
+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
+
+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
+
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL bit masks and bit positions */
+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
+
+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
+
+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
+
+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
+
+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+#define AC_ENABLE_bp 0 /* Enable bit position. */
+
+
+/* AC.AC1CTRL bit masks and bit positions */
+/* AC_INTMODE_gm Predefined. */
+/* AC_INTMODE_gp Predefined. */
+/* AC_INTMODE0_bm Predefined. */
+/* AC_INTMODE0_bp Predefined. */
+/* AC_INTMODE1_bm Predefined. */
+/* AC_INTMODE1_bp Predefined. */
+
+/* AC_INTLVL_gm Predefined. */
+/* AC_INTLVL_gp Predefined. */
+/* AC_INTLVL0_bm Predefined. */
+/* AC_INTLVL0_bp Predefined. */
+/* AC_INTLVL1_bm Predefined. */
+/* AC_INTLVL1_bp Predefined. */
+
+/* AC_HSMODE_bm Predefined. */
+/* AC_HSMODE_bp Predefined. */
+
+/* AC_HYSMODE_gm Predefined. */
+/* AC_HYSMODE_gp Predefined. */
+/* AC_HYSMODE0_bm Predefined. */
+/* AC_HYSMODE0_bp Predefined. */
+/* AC_HYSMODE1_bm Predefined. */
+/* AC_HYSMODE1_bp Predefined. */
+
+/* AC_ENABLE_bm Predefined. */
+/* AC_ENABLE_bp Predefined. */
+
+
+/* AC.AC0MUXCTRL bit masks and bit positions */
+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
+
+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+
+/* AC.AC1MUXCTRL bit masks and bit positions */
+/* AC_MUXPOS_gm Predefined. */
+/* AC_MUXPOS_gp Predefined. */
+/* AC_MUXPOS0_bm Predefined. */
+/* AC_MUXPOS0_bp Predefined. */
+/* AC_MUXPOS1_bm Predefined. */
+/* AC_MUXPOS1_bp Predefined. */
+/* AC_MUXPOS2_bm Predefined. */
+/* AC_MUXPOS2_bp Predefined. */
+
+/* AC_MUXNEG_gm Predefined. */
+/* AC_MUXNEG_gp Predefined. */
+/* AC_MUXNEG0_bm Predefined. */
+/* AC_MUXNEG0_bp Predefined. */
+/* AC_MUXNEG1_bm Predefined. */
+/* AC_MUXNEG1_bp Predefined. */
+/* AC_MUXNEG2_bm Predefined. */
+/* AC_MUXNEG2_bp Predefined. */
+
+
+/* AC.CTRLA bit masks and bit positions */
+#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
+
+
+/* AC.CTRLB bit masks and bit positions */
+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+
+/* AC.WINCTRL bit masks and bit positions */
+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+
+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
+
+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+
+/* AC.STATUS bit masks and bit positions */
+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+#define AC_WSTATE_gp 6 /* Window Mode State group position. */
+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
+
+#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
+
+#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
+
+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
+
+#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
+
+#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
+
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL bit masks and bit positions */
+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
+
+#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
+#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
+#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
+#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
+#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
+
+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+
+/* ADC_CH.MUXCTRL bit masks and bit positions */
+#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
+#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
+#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
+#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
+#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
+#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
+
+#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
+#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
+#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
+#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
+#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
+#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
+#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
+#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
+#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
+#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
+
+#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
+#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
+#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
+#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
+
+
+/* ADC_CH.INTCTRL bit masks and bit positions */
+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
+
+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+
+/* ADC_CH.INTFLAGS bit masks and bit positions */
+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
+
+/* ADC.CTRLA bit masks and bit positions */
+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */
+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */
+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */
+
+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */
+
+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */
+
+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */
+
+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
+
+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */
+
+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+
+/* ADC.CTRLB bit masks and bit positions */
+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+
+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
+
+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+
+/* ADC.REFCTRL bit masks and bit positions */
+#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
+
+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
+
+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+
+/* ADC.EVCTRL bit masks and bit positions */
+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
+
+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
+
+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
+#define ADC_EVACT_gp 0 /* Event Action Select group position. */
+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
+
+
+/* ADC.PRESCALER bit masks and bit positions */
+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+
+/* ADC.CALCTRL bit masks and bit positions */
+#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
+#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
+
+
+/* ADC.INTFLAGS bit masks and bit positions */
+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */
+
+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */
+
+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */
+
+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+
+/* DAC - Digital/Analog Converter */
+/* DAC.CTRLA bit masks and bit positions */
+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */
+
+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */
+
+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */
+
+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */
+
+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
+#define DAC_ENABLE_bp 0 /* Enable bit position. */
+
+
+/* DAC.CTRLB bit masks and bit positions */
+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
+#define DAC_CHSEL_gp 5 /* Channel Select group position. */
+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */
+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */
+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */
+
+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */
+
+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */
+
+
+/* DAC.CTRLC bit masks and bit positions */
+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
+#define DAC_REFSEL_gp 3 /* Reference Select group position. */
+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */
+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */
+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */
+
+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */
+
+
+/* DAC.EVCTRL bit masks and bit positions */
+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */
+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */
+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */
+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */
+
+
+/* DAC.TIMCTRL bit masks and bit positions */
+#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
+#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
+#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */
+#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
+#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */
+#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
+#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */
+#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */
+
+#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
+#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
+#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */
+#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
+#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */
+#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
+#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */
+#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
+#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */
+#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */
+
+
+/* DAC.STATUS bit masks and bit positions */
+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */
+
+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */
+
+
+/* RTC - Real-Time Clounter */
+/* RTC.CTRL bit masks and bit positions */
+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+
+/* RTC.STATUS bit masks and bit positions */
+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+
+/* RTC.INTCTRL bit masks and bit positions */
+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
+
+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+
+/* RTC.INTFLAGS bit masks and bit positions */
+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+
+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* EBI - External Bus Interface */
+/* EBI_CS.CTRLA bit masks and bit positions */
+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
+#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
+#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+
+/* EBI_CS.CTRLB bit masks and bit positions */
+#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
+#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
+#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
+#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
+#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
+#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
+
+#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
+#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
+
+#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
+#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
+
+#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
+#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
+#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
+#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
+#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+
+/* EBI.CTRL bit masks and bit positions */
+#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
+#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
+#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
+#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
+
+#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
+#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
+#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
+#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
+#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
+#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
+
+#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
+#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
+#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
+#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
+#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
+#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
+
+#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
+#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
+#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
+#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
+#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+
+/* EBI.SDRAMCTRLA bit masks and bit positions */
+#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+
+#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
+#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
+
+#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
+#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
+#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
+#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
+#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+
+/* EBI.SDRAMCTRLB bit masks and bit positions */
+#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
+#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
+#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
+#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
+
+#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
+#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
+#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
+#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
+#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
+#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
+#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
+#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
+
+#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
+#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
+#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
+#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
+#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
+#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
+#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+
+/* EBI.SDRAMCTRLC bit masks and bit positions */
+#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
+#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
+#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
+#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
+
+#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+
+#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
+#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
+#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
+#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
+#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
+#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
+#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA bit masks and bit positions */
+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
+
+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
+
+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+
+/* TWI_MASTER.CTRLB bit masks and bit positions */
+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
+
+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
+
+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_MASTER.CTRLC bit masks and bit positions */
+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
+#define TWI_MASTER_CMD_gp 0 /* Command group position. */
+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_MASTER.STATUS bit masks and bit positions */
+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+
+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
+
+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
+
+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+
+/* TWI_SLAVE.CTRLA bit masks and bit positions */
+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
+
+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
+
+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
+
+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_SLAVE.CTRLB bit masks and bit positions */
+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_SLAVE.STATUS bit masks and bit positions */
+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+
+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
+
+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
+
+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
+
+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+
+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
+
+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+
+/* TWI.CTRL bit masks and bit positions */
+#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+
+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+
+/* PORT - Port Configuration */
+/* PORTCFG.VPCTRLA bit masks and bit positions */
+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
+
+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+
+/* PORTCFG.VPCTRLB bit masks and bit positions */
+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
+
+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+
+/* PORTCFG.CLKEVOUT bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
+
+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
+
+
+/* VPORT.INTFLAGS bit masks and bit positions */
+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.INTCTRL bit masks and bit positions */
+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
+
+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+
+/* PORT.INTFLAGS bit masks and bit positions */
+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.PIN0CTRL bit masks and bit positions */
+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
+
+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
+
+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
+
+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+
+/* PORT.PIN1CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN2CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN3CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN4CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN5CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN6CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN7CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA bit masks and bit positions */
+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC0.CTRLB bit masks and bit positions */
+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+
+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
+
+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC0.CTRLC bit masks and bit positions */
+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+
+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
+
+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC0.CTRLD bit masks and bit positions */
+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC0_EVACT_gp 5 /* Event Action group position. */
+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC0.CTRLE bit masks and bit positions */
+#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
+#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
+
+#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC0.INTCTRLA bit masks and bit positions */
+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC0.INTCTRLB bit masks and bit positions */
+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
+
+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
+
+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC0.CTRLFCLR bit masks and bit positions */
+#define TC0_CMD_gm 0x0C /* Command group mask. */
+#define TC0_CMD_gp 2 /* Command group position. */
+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC0_CMD0_bp 2 /* Command bit 0 position. */
+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC0_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC0_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC0_DIR_bm 0x01 /* Direction bit mask. */
+#define TC0_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC0.CTRLFSET bit masks and bit positions */
+/* TC0_CMD_gm Predefined. */
+/* TC0_CMD_gp Predefined. */
+/* TC0_CMD0_bm Predefined. */
+/* TC0_CMD0_bp Predefined. */
+/* TC0_CMD1_bm Predefined. */
+/* TC0_CMD1_bp Predefined. */
+
+/* TC0_LUPD_bm Predefined. */
+/* TC0_LUPD_bp Predefined. */
+
+/* TC0_DIR_bm Predefined. */
+/* TC0_DIR_bp Predefined. */
+
+
+/* TC0.CTRLGCLR bit masks and bit positions */
+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
+
+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
+
+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC0.CTRLGSET bit masks and bit positions */
+/* TC0_CCDBV_bm Predefined. */
+/* TC0_CCDBV_bp Predefined. */
+
+/* TC0_CCCBV_bm Predefined. */
+/* TC0_CCCBV_bp Predefined. */
+
+/* TC0_CCBBV_bm Predefined. */
+/* TC0_CCBBV_bp Predefined. */
+
+/* TC0_CCABV_bm Predefined. */
+/* TC0_CCABV_bp Predefined. */
+
+/* TC0_PERBV_bm Predefined. */
+/* TC0_PERBV_bp Predefined. */
+
+
+/* TC0.INTFLAGS bit masks and bit positions */
+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
+
+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
+
+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* TC1.CTRLA bit masks and bit positions */
+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC1.CTRLB bit masks and bit positions */
+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC1.CTRLC bit masks and bit positions */
+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC1.CTRLD bit masks and bit positions */
+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC1_EVACT_gp 5 /* Event Action group position. */
+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC1.CTRLE bit masks and bit positions */
+#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
+#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
+
+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC1.INTCTRLA bit masks and bit positions */
+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC1.INTCTRLB bit masks and bit positions */
+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC1.CTRLFCLR bit masks and bit positions */
+#define TC1_CMD_gm 0x0C /* Command group mask. */
+#define TC1_CMD_gp 2 /* Command group position. */
+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC1_CMD0_bp 2 /* Command bit 0 position. */
+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC1_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC1_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC1_DIR_bm 0x01 /* Direction bit mask. */
+#define TC1_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC1.CTRLFSET bit masks and bit positions */
+/* TC1_CMD_gm Predefined. */
+/* TC1_CMD_gp Predefined. */
+/* TC1_CMD0_bm Predefined. */
+/* TC1_CMD0_bp Predefined. */
+/* TC1_CMD1_bm Predefined. */
+/* TC1_CMD1_bp Predefined. */
+
+/* TC1_LUPD_bm Predefined. */
+/* TC1_LUPD_bp Predefined. */
+
+/* TC1_DIR_bm Predefined. */
+/* TC1_DIR_bp Predefined. */
+
+
+/* TC1.CTRLGCLR bit masks and bit positions */
+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC1.CTRLGSET bit masks and bit positions */
+/* TC1_CCBBV_bm Predefined. */
+/* TC1_CCBBV_bp Predefined. */
+
+/* TC1_CCABV_bm Predefined. */
+/* TC1_CCABV_bp Predefined. */
+
+/* TC1_PERBV_bm Predefined. */
+/* TC1_PERBV_bp Predefined. */
+
+
+/* TC1.INTFLAGS bit masks and bit positions */
+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* AWEX.CTRL bit masks and bit positions */
+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
+
+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
+
+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
+
+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
+
+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
+
+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+
+/* AWEX.FDCTRL bit masks and bit positions */
+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+
+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
+
+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+
+/* AWEX.STATUS bit masks and bit positions */
+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+
+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
+
+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
+
+/* HIRES.CTRL bit masks and bit positions */
+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS bit masks and bit positions */
+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
+
+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
+
+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
+
+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
+#define USART_FERR_bp 4 /* Frame Error bit position. */
+
+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
+
+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
+#define USART_PERR_bp 2 /* Parity Error bit position. */
+
+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+
+/* USART.CTRLA bit masks and bit positions */
+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
+
+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
+
+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+
+/* USART.CTRLB bit masks and bit positions */
+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+
+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
+
+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
+
+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
+
+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+
+/* USART.CTRLC bit masks and bit positions */
+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+#define USART_CMODE_gp 6 /* Communication Mode group position. */
+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
+
+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
+#define USART_PMODE_gp 4 /* Parity Mode group position. */
+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
+
+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
+
+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
+#define USART_CHSIZE_gp 0 /* Character Size group position. */
+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+
+/* USART.BAUDCTRLA bit masks and bit positions */
+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+
+/* USART.BAUDCTRLB bit masks and bit positions */
+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+/* USART_BSEL_gm Predefined. */
+/* USART_BSEL_gp Predefined. */
+/* USART_BSEL0_bm Predefined. */
+/* USART_BSEL0_bp Predefined. */
+/* USART_BSEL1_bm Predefined. */
+/* USART_BSEL1_bp Predefined. */
+/* USART_BSEL2_bm Predefined. */
+/* USART_BSEL2_bp Predefined. */
+/* USART_BSEL3_bm Predefined. */
+/* USART_BSEL3_bp Predefined. */
+
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL bit masks and bit positions */
+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
+
+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
+
+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
+
+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
+
+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
+#define SPI_MODE_gp 2 /* SPI Mode group position. */
+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
+
+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+
+/* SPI.INTCTRL bit masks and bit positions */
+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+
+/* SPI.STATUS bit masks and bit positions */
+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+
+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL bit masks and bit positions */
+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+
+/* AES - AES Module */
+/* AES.CTRL bit masks and bit positions */
+#define AES_START_bm 0x80 /* Start/Run bit mask. */
+#define AES_START_bp 7 /* Start/Run bit position. */
+
+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */
+
+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
+#define AES_RESET_bp 5 /* AES Software Reset bit position. */
+
+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */
+
+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */
+
+
+/* AES.STATUS bit masks and bit positions */
+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
+#define AES_ERROR_bp 7 /* AES Error bit position. */
+
+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */
+
+
+/* AES.INTCTRL bit masks and bit positions */
+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
+#define AES_INTLVL_gp 0 /* Interrupt level group position. */
+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_XOSCF_vect_num 1
+#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num 2
+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
+#define PORTC_INT1_vect_num 3
+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num 4
+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
+#define PORTR_INT1_vect_num 5
+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
+
+/* DMA interrupt vectors */
+#define DMA_CH0_vect_num 6
+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
+#define DMA_CH1_vect_num 7
+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
+#define DMA_CH2_vect_num 8
+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
+#define DMA_CH3_vect_num 9
+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num 10
+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
+#define RTC_COMP_vect_num 11
+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num 12
+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num 13
+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num 14
+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
+#define TCC0_ERR_vect_num 15
+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
+#define TCC0_CCA_vect_num 16
+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
+#define TCC0_CCB_vect_num 17
+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
+#define TCC0_CCC_vect_num 18
+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
+#define TCC0_CCD_vect_num 19
+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num 20
+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+#define TCC1_ERR_vect_num 21
+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
+#define TCC1_CCA_vect_num 22
+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num 23
+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num 24
+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num 25
+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num 26
+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num 27
+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
+
+/* USARTC1 interrupt vectors */
+#define USARTC1_RXC_vect_num 28
+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
+#define USARTC1_DRE_vect_num 29
+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
+#define USARTC1_TXC_vect_num 30
+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */
+
+/* AES interrupt vectors */
+#define AES_INT_vect_num 31
+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num 32
+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
+#define NVM_SPM_vect_num 33
+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num 34
+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
+#define PORTB_INT1_vect_num 35
+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
+
+/* ACB interrupt vectors */
+#define ACB_AC0_vect_num 36
+#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
+#define ACB_AC1_vect_num 37
+#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
+#define ACB_ACW_vect_num 38
+#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */
+
+/* ADCB interrupt vectors */
+#define ADCB_CH0_vect_num 39
+#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
+#define ADCB_CH1_vect_num 40
+#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
+#define ADCB_CH2_vect_num 41
+#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
+#define ADCB_CH3_vect_num 42
+#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num 43
+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
+#define PORTE_INT1_vect_num 44
+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
+
+/* TWIE interrupt vectors */
+#define TWIE_TWIS_vect_num 45
+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
+#define TWIE_TWIM_vect_num 46
+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num 47
+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
+#define TCE0_ERR_vect_num 48
+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
+#define TCE0_CCA_vect_num 49
+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
+#define TCE0_CCB_vect_num 50
+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
+#define TCE0_CCC_vect_num 51
+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
+#define TCE0_CCD_vect_num 52
+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
+/* TCE1 interrupt vectors */
+#define TCE1_OVF_vect_num 53
+#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
+#define TCE1_ERR_vect_num 54
+#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
+#define TCE1_CCA_vect_num 55
+#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
+#define TCE1_CCB_vect_num 56
+#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */
+
+/* SPIE interrupt vectors */
+#define SPIE_INT_vect_num 57
+#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num 58
+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num 59
+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num 60
+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
+
+/* USARTE1 interrupt vectors */
+#define USARTE1_RXC_vect_num 61
+#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
+#define USARTE1_DRE_vect_num 62
+#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
+#define USARTE1_TXC_vect_num 63
+#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num 64
+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
+#define PORTD_INT1_vect_num 65
+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num 66
+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
+#define PORTA_INT1_vect_num 67
+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num 68
+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
+#define ACA_AC1_vect_num 69
+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
+#define ACA_ACW_vect_num 70
+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num 71
+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
+#define ADCA_CH1_vect_num 72
+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
+#define ADCA_CH2_vect_num 73
+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
+#define ADCA_CH3_vect_num 74
+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num 77
+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
+#define TCD0_ERR_vect_num 78
+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
+#define TCD0_CCA_vect_num 79
+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
+#define TCD0_CCB_vect_num 80
+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
+#define TCD0_CCC_vect_num 81
+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
+#define TCD0_CCD_vect_num 82
+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
+/* TCD1 interrupt vectors */
+#define TCD1_OVF_vect_num 83
+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
+#define TCD1_ERR_vect_num 84
+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
+#define TCD1_CCA_vect_num 85
+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
+#define TCD1_CCB_vect_num 86
+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num 87
+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num 88
+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num 89
+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num 90
+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
+
+/* USARTD1 interrupt vectors */
+#define USARTD1_RXC_vect_num 91
+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
+#define USARTD1_DRE_vect_num 92
+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
+#define USARTD1_TXC_vect_num 93
+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num 104
+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
+#define PORTF_INT1_vect_num 105
+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num 108
+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
+#define TCF0_ERR_vect_num 109
+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
+#define TCF0_CCA_vect_num 110
+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
+#define TCF0_CCB_vect_num 111
+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
+#define TCF0_CCC_vect_num 112
+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
+#define TCF0_CCD_vect_num 113
+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
+/* USARTF0 interrupt vectors */
+#define USARTF0_RXC_vect_num 119
+#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
+#define USARTF0_DRE_vect_num 120
+#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
+#define USARTF0_TXC_vect_num 121
+#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */
+
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (122 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#define PROGMEM_START (0x0000)
+#define PROGMEM_SIZE (204800)
+#define PROGMEM_PAGE_SIZE (512)
+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#define APP_SECTION_START (0x0000)
+#define APP_SECTION_SIZE (196608)
+#define APP_SECTION_PAGE_SIZE (512)
+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#define APPTABLE_SECTION_START (0x2E000)
+#define APPTABLE_SECTION_SIZE (8192)
+#define APPTABLE_SECTION_PAGE_SIZE (512)
+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#define BOOT_SECTION_START (0x30000)
+#define BOOT_SECTION_SIZE (8192)
+#define BOOT_SECTION_PAGE_SIZE (512)
+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#define DATAMEM_START (0x0000)
+#define DATAMEM_SIZE (16777216)
+#define DATAMEM_PAGE_SIZE (0)
+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#define IO_START (0x0000)
+#define IO_SIZE (4096)
+#define IO_PAGE_SIZE (0)
+#define IO_END (IO_START + IO_SIZE - 1)
+
+#define MAPPED_EEPROM_START (0x1000)
+#define MAPPED_EEPROM_SIZE (4096)
+#define MAPPED_EEPROM_PAGE_SIZE (0)
+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#define INTERNAL_SRAM_START (0x2000)
+#define INTERNAL_SRAM_SIZE (16384)
+#define INTERNAL_SRAM_PAGE_SIZE (0)
+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#define EEPROM_START (0x0000)
+#define EEPROM_SIZE (4096)
+#define EEPROM_PAGE_SIZE (32)
+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+#define FUSE_START (0x0000)
+#define FUSE_SIZE (6)
+#define FUSE_PAGE_SIZE (0)
+#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+
+#define LOCKBIT_START (0x0000)
+#define LOCKBIT_SIZE (1)
+#define LOCKBIT_PAGE_SIZE (0)
+#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
+
+#define SIGNATURES_START (0x0000)
+#define SIGNATURES_SIZE (3)
+#define SIGNATURES_PAGE_SIZE (0)
+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#define USER_SIGNATURES_START (0x0000)
+#define USER_SIGNATURES_SIZE (512)
+#define USER_SIGNATURES_PAGE_SIZE (0)
+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#define PROD_SIGNATURES_START (0x0000)
+#define PROD_SIGNATURES_SIZE (52)
+#define PROD_SIGNATURES_PAGE_SIZE (0)
+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHEND PROGMEM_END
+#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
+#define RAMSTART INTERNAL_SRAM_START
+#define RAMSIZE INTERNAL_SRAM_SIZE
+#define RAMEND INTERNAL_SRAM_END
+#define XRAMSTART EXTERNAL_SRAM_START
+#define XRAMSIZE EXTERNAL_SRAM_SIZE
+#define XRAMEND INTERNAL_SRAM_END
+#define E2END EEPROM_END
+#define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE0_DEFAULT (0xFF)
+
+/* Fuse Byte 1 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT (0xFF)
+
+/* Fuse Byte 2 */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
+#define FUSE2_DEFAULT (0xFF)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE4_DEFAULT (0xFF)
+
+/* Fuse Byte 5 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT (0xFF)
+
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x44
+
+
+#endif /* _AVR_ATxmega192A3_H_ */
+
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iox192d3.h:1.1
--- /dev/null Mon May 10 12:11:02 2010
+++ rtems/cpukit/score/cpu/avr/avr/iox192d3.h Mon May 10 11:31:23 2010
@@ -0,0 +1,5646 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iox192d3.h - definitions for ATxmega192D3 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iox192d3.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATxmega192D3_H_
+#define _AVR_ATxmega192D3_H_ 1
+
+
+/* Ungrouped common registers */
+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+#define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register16_t regname; \
+ struct \
+ { \
+ register8_t regname ## L; \
+ register8_t regname ## H; \
+ }; \
+ }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register32_t regname; \
+ struct \
+ { \
+ register8_t regname ## 0; \
+ register8_t regname ## 1; \
+ register8_t regname ## 2; \
+ register8_t regname ## 3; \
+ }; \
+ }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+ register8_t OCDR0; /* OCD Register 0 */
+ register8_t OCDR1; /* OCD Register 1 */
+} OCD_t;
+
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
+} CCP_t;
+
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t PSCTRL; /* Prescaler Control Register */
+ register8_t LOCK; /* Lock register */
+ register8_t RTCCTRL; /* RTC Control Register */
+} CLK_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+ register8_t PRGEN; /* General Power Reduction */
+ register8_t PRPA; /* Power Reduction Port A */
+ register8_t PRPB; /* Power Reduction Port B */
+ register8_t PRPC; /* Power Reduction Port C */
+ register8_t PRPD; /* Power Reduction Port D */
+ register8_t PRPE; /* Power Reduction Port E */
+ register8_t PRPF; /* Power Reduction Port F */
+} PR_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
+} CLK_RTCSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+ register8_t CTRL; /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
+ register8_t PLLCTRL; /* PLL Control REgister */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+} OSC_PLLSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t CALA; /* Calibration Register A */
+ register8_t CALB; /* Calibration Register B */
+ register8_t COMP0; /* Oscillator Compare Register 0 */
+ register8_t COMP1; /* Oscillator Compare Register 1 */
+ register8_t COMP2; /* Oscillator Compare Register 2 */
+ register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t CTRL; /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t WINCTRL; /* Windowed Mode Control */
+ register8_t STATUS; /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+ register8_t DEVID0; /* Device ID byte 0 */
+ register8_t DEVID1; /* Device ID byte 1 */
+ register8_t DEVID2; /* Device ID byte 2 */
+ register8_t REVID; /* Revision ID */
+ register8_t JTAGUID; /* JTAG User ID */
+ register8_t reserved_0x05;
+ register8_t MCUCR; /* MCU Control */
+ register8_t reserved_0x07;
+ register8_t EVSYSLOCK; /* Event System Lock */
+ register8_t AWEXLOCK; /* AWEX Lock */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t INTPRI; /* Interrupt Priority */
+ register8_t CTRL; /* Control Register */
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
+ register8_t CH0CTRL; /* Channel 0 Control Register */
+ register8_t CH1CTRL; /* Channel 1 Control Register */
+ register8_t CH2CTRL; /* Channel 2 Control Register */
+ register8_t CH3CTRL; /* Channel 3 Control Register */
+ register8_t STROBE; /* Event Strobe */
+ register8_t DATA; /* Event Data */
+} EVSYS_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+ register8_t ADDR0; /* Address Register 0 */
+ register8_t ADDR1; /* Address Register 1 */
+ register8_t ADDR2; /* Address Register 2 */
+ register8_t reserved_0x03;
+ register8_t DATA0; /* Data Register 0 */
+ register8_t DATA1; /* Data Register 1 */
+ register8_t DATA2; /* Data Register 2 */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t CMD; /* Command */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t INTCTRL; /* Interrupt Control */
+ register8_t reserved_0x0E;
+ register8_t STATUS; /* Status */
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_LOCKBITS_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+ register8_t FUSEBYTE0; /* User ID */
+ register8_t FUSEBYTE1; /* Watchdog Configuration */
+ register8_t FUSEBYTE2; /* Reset Configuration */
+ register8_t reserved_0x03;
+ register8_t FUSEBYTE4; /* Start-up Configuration */
+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
+ register8_t reserved_0x01;
+ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
+ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
+ register8_t reserved_0x04;
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t WAFNUM; /* Wafer Number */
+ register8_t reserved_0x11;
+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
+ register8_t reserved_0x26;
+ register8_t reserved_0x27;
+ register8_t reserved_0x28;
+ register8_t reserved_0x29;
+ register8_t reserved_0x2A;
+ register8_t reserved_0x2B;
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
+ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
+ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ register8_t reserved_0x36;
+ register8_t reserved_0x37;
+ register8_t reserved_0x38;
+ register8_t reserved_0x39;
+ register8_t reserved_0x3A;
+ register8_t reserved_0x3B;
+ register8_t reserved_0x3C;
+ register8_t reserved_0x3D;
+ register8_t reserved_0x3E;
+} NVM_PROD_SIGNATURES_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
+} NVM_CMD_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
+} NVM_SPMLVL_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
+} NVM_EELVL_t;
+
+/* Boot lock bits - boot setcion */
+typedef enum NVM_BLBB_enum
+{
+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
+} NVM_BLBB_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
+} NVM_BLBAT_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
+} NVM_LB_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
+} BOOTRST_t;
+
+/* BOD operation */
+typedef enum BOD_enum
+{
+ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
+ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
+} BOD_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WD_enum
+{
+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
+} WD_t;
+
+/* Start-up Time */
+typedef enum SUT_enum
+{
+ SUT_0MS_gc = (0x03<<2), /* 0 ms */
+ SUT_4MS_gc = (0x01<<2), /* 4 ms */
+ SUT_64MS_gc = (0x00<<2), /* 64 ms */
+} SUT_t;
+
+/* Brown Out Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
+ BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */
+ BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */
+ BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */
+ BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */
+ BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */
+ BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */
+} BODLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+ register8_t AC0CTRL; /* Comparator 0 Control */
+ register8_t AC1CTRL; /* Comparator 1 Control */
+ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
+ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t WINCTRL; /* Window Mode Control */
+ register8_t STATUS; /* Status */
+} AC_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
+} AC_INTLVL_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
+} AC_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
+} AC_WINTLVL_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
+} AC_WSTATE_t;
+
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+ register8_t INTCTRL; /* Channel Interrupt Control */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+ register8_t reserved_0x6;
+ register8_t reserved_0x7;
+} ADC_CH_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t REFCTRL; /* Reference Control */
+ register8_t EVCTRL; /* Event Control */
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t CALCTRL; /* Calibration Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ _WORDREGISTER(CAL); /* Calibration Value */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ _WORDREGISTER(CH0RES); /* Channel 0 Result */
+ _WORDREGISTER(CMP); /* Compare Value */
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ ADC_CH_t CH0; /* ADC Channel 0 */
+} ADC_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
+} ADC_CH_MUXPOS_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
+ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
+ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
+ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
+ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
+} ADC_CH_MUXNEG_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+} ADC_CH_GAIN_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
+ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
+} ADC_REFSEL_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
+} ADC_SWEEP_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
+} ADC_EVACT_t;
+
+/* Interupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
+} ADC_CH_INTLVL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Clounter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ _WORDREGISTER(CNT); /* Count Register */
+ _WORDREGISTER(PER); /* Period Register */
+ _WORDREGISTER(COMP); /* Compare Register */
+} RTC_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} RTC_OVFINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+ register8_t CTRLA; /* Chip Select Control Register A */
+ register8_t CTRLB; /* Chip Select Control Register B */
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+} EBI_CS_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t SDRAMCTRLA; /* SDRAM Control Register A */
+ register8_t reserved_0x02;
+ register8_t reserved_0x03;
+ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
+ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
+ register8_t SDRAMCTRLB; /* SDRAM Control Register B */
+ register8_t SDRAMCTRLC; /* SDRAM Control Register C */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ EBI_CS_t CS0; /* Chip Select 0 */
+ EBI_CS_t CS1; /* Chip Select 1 */
+ EBI_CS_t CS2; /* Chip Select 2 */
+ EBI_CS_t CS3; /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select adress space */
+typedef enum EBI_CS_ASPACE_enum
+{
+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* */
+typedef enum EBI_CS_SRWS_enum
+{
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
+ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
+ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
+ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
+ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* */
+typedef enum EBI_SDDATAW_enum
+{
+ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
+ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/* */
+typedef enum EBI_LPCMODE_enum
+{
+ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
+ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* */
+typedef enum EBI_SRMODE_enum
+{
+ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
+ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
+ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
+ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* */
+typedef enum EBI_IFMODE_enum
+{
+ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
+ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
+ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
+ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
+} EBI_IFMODE_t;
+
+/* */
+typedef enum EBI_SDCOL_enum
+{
+ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
+ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
+ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+} EBI_SDCOL_t;
+
+/* */
+typedef enum EBI_MRDLY_enum
+{
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* */
+typedef enum EBI_ROWCYCDLY_enum
+{
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* */
+typedef enum EBI_RPDLY_enum
+{
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_RPDLY_t;
+
+/* */
+typedef enum EBI_WRDLY_enum
+{
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_WRDLY_t;
+
+/* */
+typedef enum EBI_ESRDLY_enum
+{
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/* */
+typedef enum EBI_ROWCOLDLY_enum
+{
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_MASTER_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t STATUS; /* Status Register */
+ register8_t BAUD; /* Baurd Rate Control Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+} TWI_MASTER_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_SLAVE_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+ register8_t ADDRMASK; /* Address Mask Register */
+} TWI_SLAVE_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+ register8_t CTRL; /* TWI Common Control Register */
+ TWI_MASTER_t MASTER; /* TWI master module */
+ TWI_SLAVE_t SLAVE; /* TWI slave module */
+} TWI_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+ register8_t MPCMASK; /* Multi-pin Configuration Mask */
+ register8_t reserved_0x01;
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
+} PORTCFG_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t OUT; /* I/O Port Output */
+ register8_t IN; /* I/O Port Input */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+} VPORT_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t DIRSET; /* I/O Port Data Direction Set */
+ register8_t DIRCLR; /* I/O Port Data Direction Clear */
+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
+ register8_t OUT; /* I/O Port Output */
+ register8_t OUTSET; /* I/O Port Output Set */
+ register8_t OUTCLR; /* I/O Port Output Clear */
+ register8_t OUTTGL; /* I/O Port Output Toggle */
+ register8_t IN; /* I/O port Input */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INT0MASK; /* Port Interrupt 0 Mask */
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+ register8_t PIN2CTRL; /* Pin 2 Control Register */
+ register8_t PIN3CTRL; /* Pin 3 Control Register */
+ register8_t PIN4CTRL; /* Pin 4 Control Register */
+ register8_t PIN5CTRL; /* Pin 5 Control Register */
+ register8_t PIN6CTRL; /* Pin 6 Control Register */
+ register8_t PIN7CTRL; /* Pin 7 Control Register */
+} PORT_t;
+
+/* Virtual Port 0 Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Virtual Port 1 Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Virtual Port 2 Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port 3 Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/* Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
+} PORT_INT1LVL_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ _WORDREGISTER(CCC); /* Compare or Capture C */
+ _WORDREGISTER(CCD); /* Compare or Capture D */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+} TC0_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x05;
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+ register8_t DTHS; /* Dead Time High Side */
+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
+ register8_t DTHSBUF; /* Dead Time High Side Buffer */
+ register8_t OUTOVEN; /* Output Override Enable */
+} AWEX_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+ register8_t CTRLA; /* Control Register */
+} HIRES_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+ register8_t DATA; /* Data Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
+} USART_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
+} USART_TXCINTLVL_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
+} USART_DREINTLVL_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
+} USART_PMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t DATA; /* Data Register */
+} SPI_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} SPI_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRDA_EVSEL_enum
+{
+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
+} IRDA_EVSEL_t;
+
+
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
+#define CLK (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
+#define PR (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST (*(RST_t *) 0x0078) /* Reset Controller */
+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
+#define GPIO_GPIORA _SFR_MEM8(0x000A)
+#define GPIO_GPIORB _SFR_MEM8(0x000B)
+#define GPIO_GPIORC _SFR_MEM8(0x000C)
+#define GPIO_GPIORD _SFR_MEM8(0x000D)
+#define GPIO_GPIORE _SFR_MEM8(0x000E)
+#define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+/* VPORT0 - Virtual Port 0 */
+#define VPORT0_DIR _SFR_MEM8(0x0010)
+#define VPORT0_OUT _SFR_MEM8(0x0011)
+#define VPORT0_IN _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+/* VPORT1 - Virtual Port 1 */
+#define VPORT1_DIR _SFR_MEM8(0x0014)
+#define VPORT1_OUT _SFR_MEM8(0x0015)
+#define VPORT1_IN _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+/* VPORT2 - Virtual Port 2 */
+#define VPORT2_DIR _SFR_MEM8(0x0018)
+#define VPORT2_OUT _SFR_MEM8(0x0019)
+#define VPORT2_IN _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+/* VPORT3 - Virtual Port 3 */
+#define VPORT3_DIR _SFR_MEM8(0x001C)
+#define VPORT3_OUT _SFR_MEM8(0x001D)
+#define VPORT3_IN _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0 _SFR_MEM8(0x002E)
+#define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+/* CPU - CPU Registers */
+#define CPU_CCP _SFR_MEM8(0x0034)
+#define CPU_RAMPD _SFR_MEM8(0x0038)
+#define CPU_RAMPX _SFR_MEM8(0x0039)
+#define CPU_RAMPY _SFR_MEM8(0x003A)
+#define CPU_RAMPZ _SFR_MEM8(0x003B)
+#define CPU_EIND _SFR_MEM8(0x003C)
+#define CPU_SPL _SFR_MEM8(0x003D)
+#define CPU_SPH _SFR_MEM8(0x003E)
+#define CPU_SREG _SFR_MEM8(0x003F)
+
+/* CLK - Clock System */
+#define CLK_CTRL _SFR_MEM8(0x0040)
+#define CLK_PSCTRL _SFR_MEM8(0x0041)
+#define CLK_LOCK _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL _SFR_MEM8(0x0043)
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+/* OSC - Oscillator Control */
+#define OSC_CTRL _SFR_MEM8(0x0050)
+#define OSC_STATUS _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+
+/* PR - Power Reduction */
+#define PR_PRGEN _SFR_MEM8(0x0070)
+#define PR_PRPA _SFR_MEM8(0x0071)
+#define PR_PRPB _SFR_MEM8(0x0072)
+#define PR_PRPC _SFR_MEM8(0x0073)
+#define PR_PRPD _SFR_MEM8(0x0074)
+#define PR_PRPE _SFR_MEM8(0x0075)
+#define PR_PRPF _SFR_MEM8(0x0076)
+
+/* RST - Reset Controller */
+#define RST_STATUS _SFR_MEM8(0x0078)
+#define RST_CTRL _SFR_MEM8(0x0079)
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL _SFR_MEM8(0x0080)
+#define WDT_WINCTRL _SFR_MEM8(0x0081)
+#define WDT_STATUS _SFR_MEM8(0x0082)
+
+/* MCU - MCU Control */
+#define MCU_DEVID0 _SFR_MEM8(0x0090)
+#define MCU_DEVID1 _SFR_MEM8(0x0091)
+#define MCU_DEVID2 _SFR_MEM8(0x0092)
+#define MCU_REVID _SFR_MEM8(0x0093)
+#define MCU_JTAGUID _SFR_MEM8(0x0094)
+#define MCU_MCUCR _SFR_MEM8(0x0096)
+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+/* PMIC - Programmable Interrupt Controller */
+#define PMIC_STATUS _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI _SFR_MEM8(0x00A1)
+#define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+/* PORTCFG - Port Configuration */
+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
+#define EVSYS_STROBE _SFR_MEM8(0x0190)
+#define EVSYS_DATA _SFR_MEM8(0x0191)
+
+/* NVM - Non Volatile Memory Controller */
+#define NVM_ADDR0 _SFR_MEM8(0x01C0)
+#define NVM_ADDR1 _SFR_MEM8(0x01C1)
+#define NVM_ADDR2 _SFR_MEM8(0x01C2)
+#define NVM_DATA0 _SFR_MEM8(0x01C4)
+#define NVM_DATA1 _SFR_MEM8(0x01C5)
+#define NVM_DATA2 _SFR_MEM8(0x01C6)
+#define NVM_CMD _SFR_MEM8(0x01CA)
+#define NVM_CTRLA _SFR_MEM8(0x01CB)
+#define NVM_CTRLB _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL _SFR_MEM8(0x01CD)
+#define NVM_STATUS _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+/* ADCA - Analog to Digital Converter A */
+#define ADCA_CTRLA _SFR_MEM8(0x0200)
+#define ADCA_CTRLB _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER _SFR_MEM8(0x0204)
+#define ADCA_CALCTRL _SFR_MEM8(0x0205)
+#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
+#define ADCA_CAL _SFR_MEM16(0x020C)
+#define ADCA_CH0RES _SFR_MEM16(0x0210)
+#define ADCA_CMP _SFR_MEM16(0x0218)
+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES _SFR_MEM16(0x0224)
+
+/* ACA - Analog Comparator A */
+#define ACA_AC0CTRL _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
+#define ACA_CTRLA _SFR_MEM8(0x0384)
+#define ACA_CTRLB _SFR_MEM8(0x0385)
+#define ACA_WINCTRL _SFR_MEM8(0x0386)
+#define ACA_STATUS _SFR_MEM8(0x0387)
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL _SFR_MEM8(0x0400)
+#define RTC_STATUS _SFR_MEM8(0x0401)
+#define RTC_INTCTRL _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS _SFR_MEM8(0x0403)
+#define RTC_TEMP _SFR_MEM8(0x0404)
+#define RTC_CNT _SFR_MEM16(0x0408)
+#define RTC_PER _SFR_MEM16(0x040A)
+#define RTC_COMP _SFR_MEM16(0x040C)
+
+/* TWIC - Two-Wire Interface C */
+#define TWIC_CTRL _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483)
+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484)
+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485)
+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486)
+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487)
+#define TWIC_MASTER_DATA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+/* PORTA - Port A */
+#define PORTA_DIR _SFR_MEM8(0x0600)
+#define PORTA_DIRSET _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL _SFR_MEM8(0x0603)
+#define PORTA_OUT _SFR_MEM8(0x0604)
+#define PORTA_OUTSET _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL _SFR_MEM8(0x0607)
+#define PORTA_IN _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+/* PORTB - Port B */
+#define PORTB_DIR _SFR_MEM8(0x0620)
+#define PORTB_DIRSET _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL _SFR_MEM8(0x0623)
+#define PORTB_OUT _SFR_MEM8(0x0624)
+#define PORTB_OUTSET _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL _SFR_MEM8(0x0627)
+#define PORTB_IN _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+/* PORTC - Port C */
+#define PORTC_DIR _SFR_MEM8(0x0640)
+#define PORTC_DIRSET _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL _SFR_MEM8(0x0643)
+#define PORTC_OUT _SFR_MEM8(0x0644)
+#define PORTC_OUTSET _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL _SFR_MEM8(0x0647)
+#define PORTC_IN _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+/* PORTD - Port D */
+#define PORTD_DIR _SFR_MEM8(0x0660)
+#define PORTD_DIRSET _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL _SFR_MEM8(0x0663)
+#define PORTD_OUT _SFR_MEM8(0x0664)
+#define PORTD_OUTSET _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL _SFR_MEM8(0x0667)
+#define PORTD_IN _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+/* PORTE - Port E */
+#define PORTE_DIR _SFR_MEM8(0x0680)
+#define PORTE_DIRSET _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL _SFR_MEM8(0x0683)
+#define PORTE_OUT _SFR_MEM8(0x0684)
+#define PORTE_OUTSET _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL _SFR_MEM8(0x0687)
+#define PORTE_IN _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+/* PORTF - Port F */
+#define PORTF_DIR _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
+#define PORTF_OUT _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
+#define PORTF_IN _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+/* PORTR - Port R */
+#define PORTR_DIR _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
+#define PORTR_OUT _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
+#define PORTR_IN _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+/* TCC0 - Timer/Counter C0 */
+#define TCC0_CTRLA _SFR_MEM8(0x0800)
+#define TCC0_CTRLB _SFR_MEM8(0x0801)
+#define TCC0_CTRLC _SFR_MEM8(0x0802)
+#define TCC0_CTRLD _SFR_MEM8(0x0803)
+#define TCC0_CTRLE _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
+#define TCC0_TEMP _SFR_MEM8(0x080F)
+#define TCC0_CNT _SFR_MEM16(0x0820)
+#define TCC0_PER _SFR_MEM16(0x0826)
+#define TCC0_CCA _SFR_MEM16(0x0828)
+#define TCC0_CCB _SFR_MEM16(0x082A)
+#define TCC0_CCC _SFR_MEM16(0x082C)
+#define TCC0_CCD _SFR_MEM16(0x082E)
+#define TCC0_PERBUF _SFR_MEM16(0x0836)
+#define TCC0_CCABUF _SFR_MEM16(0x0838)
+#define TCC0_CCBBUF _SFR_MEM16(0x083A)
+#define TCC0_CCCBUF _SFR_MEM16(0x083C)
+#define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+/* TCC1 - Timer/Counter C1 */
+#define TCC1_CTRLA _SFR_MEM8(0x0840)
+#define TCC1_CTRLB _SFR_MEM8(0x0841)
+#define TCC1_CTRLC _SFR_MEM8(0x0842)
+#define TCC1_CTRLD _SFR_MEM8(0x0843)
+#define TCC1_CTRLE _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
+#define TCC1_TEMP _SFR_MEM8(0x084F)
+#define TCC1_CNT _SFR_MEM16(0x0860)
+#define TCC1_PER _SFR_MEM16(0x0866)
+#define TCC1_CCA _SFR_MEM16(0x0868)
+#define TCC1_CCB _SFR_MEM16(0x086A)
+#define TCC1_PERBUF _SFR_MEM16(0x0876)
+#define TCC1_CCABUF _SFR_MEM16(0x0878)
+#define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+/* AWEXC - Advanced Waveform Extension C */
+#define AWEXC_CTRL _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+#define AWEXC_STATUS _SFR_MEM8(0x0884)
+#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+#define AWEXC_DTLS _SFR_MEM8(0x0888)
+#define AWEXC_DTHS _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+/* HIRESC - High-Resolution Extension C */
+#define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0_DATA _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+/* SPIC - Serial Peripheral Interface C */
+#define SPIC_CTRL _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+#define SPIC_STATUS _SFR_MEM8(0x08C2)
+#define SPIC_DATA _SFR_MEM8(0x08C3)
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_CTRL _SFR_MEM8(0x08F8)
+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
+
+/* TCD0 - Timer/Counter D0 */
+#define TCD0_CTRLA _SFR_MEM8(0x0900)
+#define TCD0_CTRLB _SFR_MEM8(0x0901)
+#define TCD0_CTRLC _SFR_MEM8(0x0902)
+#define TCD0_CTRLD _SFR_MEM8(0x0903)
+#define TCD0_CTRLE _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
+#define TCD0_TEMP _SFR_MEM8(0x090F)
+#define TCD0_CNT _SFR_MEM16(0x0920)
+#define TCD0_PER _SFR_MEM16(0x0926)
+#define TCD0_CCA _SFR_MEM16(0x0928)
+#define TCD0_CCB _SFR_MEM16(0x092A)
+#define TCD0_CCC _SFR_MEM16(0x092C)
+#define TCD0_CCD _SFR_MEM16(0x092E)
+#define TCD0_PERBUF _SFR_MEM16(0x0936)
+#define TCD0_CCABUF _SFR_MEM16(0x0938)
+#define TCD0_CCBBUF _SFR_MEM16(0x093A)
+#define TCD0_CCCBUF _SFR_MEM16(0x093C)
+#define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0_DATA _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+/* SPID - Serial Peripheral Interface D */
+#define SPID_CTRL _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL _SFR_MEM8(0x09C1)
+#define SPID_STATUS _SFR_MEM8(0x09C2)
+#define SPID_DATA _SFR_MEM8(0x09C3)
+
+/* TCE0 - Timer/Counter E0 */
+#define TCE0_CTRLA _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP _SFR_MEM8(0x0A0F)
+#define TCE0_CNT _SFR_MEM16(0x0A20)
+#define TCE0_PER _SFR_MEM16(0x0A26)
+#define TCE0_CCA _SFR_MEM16(0x0A28)
+#define TCE0_CCB _SFR_MEM16(0x0A2A)
+#define TCE0_CCC _SFR_MEM16(0x0A2C)
+#define TCE0_CCD _SFR_MEM16(0x0A2E)
+#define TCE0_PERBUF _SFR_MEM16(0x0A36)
+#define TCE0_CCABUF _SFR_MEM16(0x0A38)
+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+/* AWEXE - Advanced Waveform Extension E */
+#define AWEXE_CTRL _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS _SFR_MEM8(0x0A84)
+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0_DATA _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+/* SPIE - Serial Peripheral Interface E */
+#define SPIE_CTRL _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS _SFR_MEM8(0x0AC2)
+#define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+/* TCF0 - Timer/Counter F0 */
+#define TCF0_CTRLA _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP _SFR_MEM8(0x0B0F)
+#define TCF0_CNT _SFR_MEM16(0x0B20)
+#define TCF0_PER _SFR_MEM16(0x0B26)
+#define TCF0_CCA _SFR_MEM16(0x0B28)
+#define TCF0_CCB _SFR_MEM16(0x0B2A)
+#define TCF0_CCC _SFR_MEM16(0x0B2C)
+#define TCF0_CCD _SFR_MEM16(0x0B2E)
+#define TCF0_PERBUF _SFR_MEM16(0x0B36)
+#define TCF0_CCABUF _SFR_MEM16(0x0B38)
+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR1 bit masks and bit positions */
+#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+
+/* CPU - CPU */
+/* CPU.CCP bit masks and bit positions */
+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+#define CPU_CCP_gp 0 /* CCP signature group position. */
+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+
+/* CPU.SREG bit masks and bit positions */
+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+
+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
+#define CPU_T_bp 6 /* Transfer Bit bit position. */
+
+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
+#define CPU_H_bp 5 /* Half Carry Flag bit position. */
+
+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
+
+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
+
+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
+#define CPU_N_bp 2 /* Negative Flag bit position. */
+
+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
+#define CPU_Z_bp 1 /* Zero Flag bit position. */
+
+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+#define CPU_C_bp 0 /* Carry Flag bit position. */
+
+
+/* CLK - Clock System */
+/* CLK.CTRL bit masks and bit positions */
+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+
+/* CLK.PSCTRL bit masks and bit positions */
+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
+
+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+
+/* CLK.LOCK bit masks and bit positions */
+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+
+/* CLK.RTCCTRL bit masks and bit positions */
+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
+
+#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
+
+
+/* PR.PRGEN bit masks and bit positions */
+#define PR_AES_bm 0x10 /* AES bit mask. */
+#define PR_AES_bp 4 /* AES bit position. */
+
+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
+#define PR_EBI_bp 3 /* External Bus Interface bit position. */
+
+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
+#define PR_RTC_bp 2 /* Real-time Counter bit position. */
+
+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
+#define PR_EVSYS_bp 1 /* Event System bit position. */
+
+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
+#define PR_DMA_bp 0 /* DMA-Controller bit position. */
+
+
+/* PR.PRPA bit masks and bit positions */
+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
+#define PR_DAC_bp 2 /* Port A DAC bit position. */
+
+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
+#define PR_ADC_bp 1 /* Port A ADC bit position. */
+
+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+
+/* PR.PRPB bit masks and bit positions */
+/* PR_DAC_bm Predefined. */
+/* PR_DAC_bp Predefined. */
+
+/* PR_ADC_bm Predefined. */
+/* PR_ADC_bp Predefined. */
+
+/* PR_AC_bm Predefined. */
+/* PR_AC_bp Predefined. */
+
+
+/* PR.PRPC bit masks and bit positions */
+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
+
+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
+#define PR_USART1_bp 5 /* Port C USART1 bit position. */
+
+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
+#define PR_USART0_bp 4 /* Port C USART0 bit position. */
+
+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
+#define PR_SPI_bp 3 /* Port C SPI bit position. */
+
+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+
+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
+
+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+
+/* PR.PRPD bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPE bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPF bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL bit masks and bit positions */
+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
+
+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+
+/* OSC - Oscillator */
+/* OSC.CTRL bit masks and bit positions */
+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
+
+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
+
+#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
+
+#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
+
+#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
+
+
+/* OSC.STATUS bit masks and bit positions */
+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+
+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
+
+#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
+
+#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
+
+#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
+
+
+/* OSC.XOSCCTRL bit masks and bit positions */
+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
+
+#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
+
+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+
+/* OSC.XOSCFAIL bit masks and bit positions */
+#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
+
+#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
+
+
+/* OSC.PLLCTRL bit masks and bit positions */
+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+
+/* OSC.DFLLCTRL bit masks and bit positions */
+#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
+#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
+
+#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL bit masks and bit positions */
+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+
+/* DFLL.CALA bit masks and bit positions */
+#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
+#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
+#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
+#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
+#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
+#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
+#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
+#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
+#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
+
+
+/* DFLL.CALB bit masks and bit positions */
+#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
+#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
+#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
+#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
+#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
+#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
+#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
+#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
+
+
+/* RST - Reset */
+/* RST.STATUS bit masks and bit positions */
+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
+
+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
+
+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
+
+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
+
+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
+
+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
+
+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+
+/* RST.CTRL bit masks and bit positions */
+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+#define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL bit masks and bit positions */
+#define WDT_PER_gm 0x3C /* Period group mask. */
+#define WDT_PER_gp 2 /* Period group position. */
+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
+#define WDT_PER0_bp 2 /* Period bit 0 position. */
+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
+#define WDT_PER1_bp 3 /* Period bit 1 position. */
+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
+#define WDT_PER2_bp 4 /* Period bit 2 position. */
+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
+#define WDT_PER3_bp 5 /* Period bit 3 position. */
+
+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
+#define WDT_ENABLE_bp 1 /* Enable bit position. */
+
+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+#define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+
+/* WDT.WINCTRL bit masks and bit positions */
+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
+
+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
+
+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+
+/* WDT.STATUS bit masks and bit positions */
+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR bit masks and bit positions */
+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+
+/* MCU.EVSYSLOCK bit masks and bit positions */
+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
+
+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+
+/* MCU.AWEXLOCK bit masks and bit positions */
+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS bit masks and bit positions */
+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
+
+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
+
+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
+
+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+
+/* PMIC.CTRL bit masks and bit positions */
+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+
+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
+
+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
+
+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
+
+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX bit masks and bit positions */
+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+
+/* EVSYS.CH1MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH2MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH3MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH0CTRL bit masks and bit positions */
+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
+
+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
+
+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+
+/* EVSYS.CH1CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH2CTRL bit masks and bit positions */
+/* EVSYS_QDIRM_gm Predefined. */
+/* EVSYS_QDIRM_gp Predefined. */
+/* EVSYS_QDIRM0_bm Predefined. */
+/* EVSYS_QDIRM0_bp Predefined. */
+/* EVSYS_QDIRM1_bm Predefined. */
+/* EVSYS_QDIRM1_bp Predefined. */
+
+/* EVSYS_QDIEN_bm Predefined. */
+/* EVSYS_QDIEN_bp Predefined. */
+
+/* EVSYS_QDEN_bm Predefined. */
+/* EVSYS_QDEN_bp Predefined. */
+
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH3CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD bit masks and bit positions */
+#define NVM_CMD_gm 0xFF /* Command group mask. */
+#define NVM_CMD_gp 0 /* Command group position. */
+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define NVM_CMD0_bp 0 /* Command bit 0 position. */
+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define NVM_CMD1_bp 1 /* Command bit 1 position. */
+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
+#define NVM_CMD2_bp 2 /* Command bit 2 position. */
+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
+#define NVM_CMD3_bp 3 /* Command bit 3 position. */
+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
+#define NVM_CMD4_bp 4 /* Command bit 4 position. */
+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
+#define NVM_CMD5_bp 5 /* Command bit 5 position. */
+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+#define NVM_CMD6_bp 6 /* Command bit 6 position. */
+#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
+#define NVM_CMD7_bp 7 /* Command bit 7 position. */
+
+
+/* NVM.CTRLA bit masks and bit positions */
+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+
+/* NVM.CTRLB bit masks and bit positions */
+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+
+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
+
+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
+
+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+
+/* NVM.INTCTRL bit masks and bit positions */
+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
+
+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+
+/* NVM.STATUS bit masks and bit positions */
+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+
+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
+
+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
+
+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+
+/* NVM.LOCKBITS bit masks and bit positions */
+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
+#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
+#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
+#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
+#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
+#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
+#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
+#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
+#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
+#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
+#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
+#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
+#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
+#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
+#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
+#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
+#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
+#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
+#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
+
+
+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
+
+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
+
+
+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
+#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
+#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
+
+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
+
+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
+
+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
+
+
+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
+
+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
+
+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
+
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL bit masks and bit positions */
+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
+
+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
+
+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
+
+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
+
+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+#define AC_ENABLE_bp 0 /* Enable bit position. */
+
+
+/* AC.AC1CTRL bit masks and bit positions */
+/* AC_INTMODE_gm Predefined. */
+/* AC_INTMODE_gp Predefined. */
+/* AC_INTMODE0_bm Predefined. */
+/* AC_INTMODE0_bp Predefined. */
+/* AC_INTMODE1_bm Predefined. */
+/* AC_INTMODE1_bp Predefined. */
+
+/* AC_INTLVL_gm Predefined. */
+/* AC_INTLVL_gp Predefined. */
+/* AC_INTLVL0_bm Predefined. */
+/* AC_INTLVL0_bp Predefined. */
+/* AC_INTLVL1_bm Predefined. */
+/* AC_INTLVL1_bp Predefined. */
+
+/* AC_HSMODE_bm Predefined. */
+/* AC_HSMODE_bp Predefined. */
+
+/* AC_HYSMODE_gm Predefined. */
+/* AC_HYSMODE_gp Predefined. */
+/* AC_HYSMODE0_bm Predefined. */
+/* AC_HYSMODE0_bp Predefined. */
+/* AC_HYSMODE1_bm Predefined. */
+/* AC_HYSMODE1_bp Predefined. */
+
+/* AC_ENABLE_bm Predefined. */
+/* AC_ENABLE_bp Predefined. */
+
+
+/* AC.AC0MUXCTRL bit masks and bit positions */
+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
+
+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+
+/* AC.AC1MUXCTRL bit masks and bit positions */
+/* AC_MUXPOS_gm Predefined. */
+/* AC_MUXPOS_gp Predefined. */
+/* AC_MUXPOS0_bm Predefined. */
+/* AC_MUXPOS0_bp Predefined. */
+/* AC_MUXPOS1_bm Predefined. */
+/* AC_MUXPOS1_bp Predefined. */
+/* AC_MUXPOS2_bm Predefined. */
+/* AC_MUXPOS2_bp Predefined. */
+
+/* AC_MUXNEG_gm Predefined. */
+/* AC_MUXNEG_gp Predefined. */
+/* AC_MUXNEG0_bm Predefined. */
+/* AC_MUXNEG0_bp Predefined. */
+/* AC_MUXNEG1_bm Predefined. */
+/* AC_MUXNEG1_bp Predefined. */
+/* AC_MUXNEG2_bm Predefined. */
+/* AC_MUXNEG2_bp Predefined. */
+
+
+/* AC.CTRLA bit masks and bit positions */
+#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
+
+
+/* AC.CTRLB bit masks and bit positions */
+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+
+/* AC.WINCTRL bit masks and bit positions */
+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+
+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
+
+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+
+/* AC.STATUS bit masks and bit positions */
+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+#define AC_WSTATE_gp 6 /* Window Mode State group position. */
+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
+
+#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
+
+#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
+
+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
+
+#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
+
+#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
+
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL bit masks and bit positions */
+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
+
+#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
+#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
+#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
+#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
+#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
+
+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+
+/* ADC_CH.MUXCTRL bit masks and bit positions */
+#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
+#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
+#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
+#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
+#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
+#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
+
+#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
+#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
+#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
+#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
+#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
+#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
+#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
+#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
+#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
+#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
+
+#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
+#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
+#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
+#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
+
+
+/* ADC_CH.INTCTRL bit masks and bit positions */
+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
+
+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+
+/* ADC_CH.INTFLAGS bit masks and bit positions */
+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
+
+/* ADC.CTRLA bit masks and bit positions */
+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
+
+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+
+/* ADC.CTRLB bit masks and bit positions */
+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+
+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
+
+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+
+/* ADC.REFCTRL bit masks and bit positions */
+#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
+
+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
+
+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+
+/* ADC.EVCTRL bit masks and bit positions */
+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
+
+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
+
+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
+#define ADC_EVACT_gp 0 /* Event Action Select group position. */
+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
+
+
+/* ADC.PRESCALER bit masks and bit positions */
+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+
+/* ADC.CALCTRL bit masks and bit positions */
+#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
+#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
+
+
+/* ADC.INTFLAGS bit masks and bit positions */
+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+
+/* RTC - Real-Time Clounter */
+/* RTC.CTRL bit masks and bit positions */
+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+
+/* RTC.STATUS bit masks and bit positions */
+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+
+/* RTC.INTCTRL bit masks and bit positions */
+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
+
+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+
+/* RTC.INTFLAGS bit masks and bit positions */
+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+
+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* EBI - External Bus Interface */
+/* EBI_CS.CTRLA bit masks and bit positions */
+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
+#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
+#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+
+/* EBI_CS.CTRLB bit masks and bit positions */
+#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
+#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
+#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
+#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
+#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
+#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
+
+#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
+#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
+
+#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
+#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
+
+#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
+#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
+#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
+#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
+#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+
+/* EBI.CTRL bit masks and bit positions */
+#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
+#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
+#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
+#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
+
+#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
+#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
+#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
+#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
+#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
+#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
+
+#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
+#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
+#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
+#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
+#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
+#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
+
+#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
+#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
+#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
+#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
+#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+
+/* EBI.SDRAMCTRLA bit masks and bit positions */
+#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+
+#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
+#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
+
+#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
+#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
+#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
+#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
+#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+
+/* EBI.SDRAMCTRLB bit masks and bit positions */
+#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
+#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
+#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
+#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
+
+#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
+#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
+#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
+#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
+#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
+#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
+#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
+#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
+
+#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
+#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
+#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
+#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
+#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
+#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
+#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+
+/* EBI.SDRAMCTRLC bit masks and bit positions */
+#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
+#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
+#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
+#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
+
+#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+
+#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
+#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
+#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
+#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
+#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
+#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
+#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA bit masks and bit positions */
+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
+
+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
+
+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+
+/* TWI_MASTER.CTRLB bit masks and bit positions */
+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
+
+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
+
+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_MASTER.CTRLC bit masks and bit positions */
+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
+#define TWI_MASTER_CMD_gp 0 /* Command group position. */
+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_MASTER.STATUS bit masks and bit positions */
+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+
+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
+
+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
+
+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+
+/* TWI_SLAVE.CTRLA bit masks and bit positions */
+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
+
+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
+
+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
+
+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_SLAVE.CTRLB bit masks and bit positions */
+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_SLAVE.STATUS bit masks and bit positions */
+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+
+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
+
+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
+
+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
+
+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+
+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
+
+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+
+/* TWI.CTRL bit masks and bit positions */
+#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+
+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+
+/* PORT - Port Configuration */
+/* PORTCFG.VPCTRLA bit masks and bit positions */
+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
+
+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+
+/* PORTCFG.VPCTRLB bit masks and bit positions */
+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
+
+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+
+/* PORTCFG.CLKEVOUT bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
+
+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
+
+
+/* VPORT.INTFLAGS bit masks and bit positions */
+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.INTCTRL bit masks and bit positions */
+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
+
+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+
+/* PORT.INTFLAGS bit masks and bit positions */
+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.PIN0CTRL bit masks and bit positions */
+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
+
+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
+
+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
+
+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+
+/* PORT.PIN1CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN2CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN3CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN4CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN5CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN6CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN7CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA bit masks and bit positions */
+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC0.CTRLB bit masks and bit positions */
+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+
+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
+
+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC0.CTRLC bit masks and bit positions */
+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+
+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
+
+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC0.CTRLD bit masks and bit positions */
+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC0_EVACT_gp 5 /* Event Action group position. */
+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC0.CTRLE bit masks and bit positions */
+#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC0.INTCTRLA bit masks and bit positions */
+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC0.INTCTRLB bit masks and bit positions */
+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
+
+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
+
+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC0.CTRLFCLR bit masks and bit positions */
+#define TC0_CMD_gm 0x0C /* Command group mask. */
+#define TC0_CMD_gp 2 /* Command group position. */
+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC0_CMD0_bp 2 /* Command bit 0 position. */
+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC0_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC0_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC0_DIR_bm 0x01 /* Direction bit mask. */
+#define TC0_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC0.CTRLFSET bit masks and bit positions */
+/* TC0_CMD_gm Predefined. */
+/* TC0_CMD_gp Predefined. */
+/* TC0_CMD0_bm Predefined. */
+/* TC0_CMD0_bp Predefined. */
+/* TC0_CMD1_bm Predefined. */
+/* TC0_CMD1_bp Predefined. */
+
+/* TC0_LUPD_bm Predefined. */
+/* TC0_LUPD_bp Predefined. */
+
+/* TC0_DIR_bm Predefined. */
+/* TC0_DIR_bp Predefined. */
+
+
+/* TC0.CTRLGCLR bit masks and bit positions */
+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
+
+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
+
+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC0.CTRLGSET bit masks and bit positions */
+/* TC0_CCDBV_bm Predefined. */
+/* TC0_CCDBV_bp Predefined. */
+
+/* TC0_CCCBV_bm Predefined. */
+/* TC0_CCCBV_bp Predefined. */
+
+/* TC0_CCBBV_bm Predefined. */
+/* TC0_CCBBV_bp Predefined. */
+
+/* TC0_CCABV_bm Predefined. */
+/* TC0_CCABV_bp Predefined. */
+
+/* TC0_PERBV_bm Predefined. */
+/* TC0_PERBV_bp Predefined. */
+
+
+/* TC0.INTFLAGS bit masks and bit positions */
+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
+
+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
+
+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* TC1.CTRLA bit masks and bit positions */
+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC1.CTRLB bit masks and bit positions */
+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC1.CTRLC bit masks and bit positions */
+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC1.CTRLD bit masks and bit positions */
+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC1_EVACT_gp 5 /* Event Action group position. */
+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC1.CTRLE bit masks and bit positions */
+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC1.INTCTRLA bit masks and bit positions */
+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC1.INTCTRLB bit masks and bit positions */
+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC1.CTRLFCLR bit masks and bit positions */
+#define TC1_CMD_gm 0x0C /* Command group mask. */
+#define TC1_CMD_gp 2 /* Command group position. */
+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC1_CMD0_bp 2 /* Command bit 0 position. */
+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC1_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC1_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC1_DIR_bm 0x01 /* Direction bit mask. */
+#define TC1_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC1.CTRLFSET bit masks and bit positions */
+/* TC1_CMD_gm Predefined. */
+/* TC1_CMD_gp Predefined. */
+/* TC1_CMD0_bm Predefined. */
+/* TC1_CMD0_bp Predefined. */
+/* TC1_CMD1_bm Predefined. */
+/* TC1_CMD1_bp Predefined. */
+
+/* TC1_LUPD_bm Predefined. */
+/* TC1_LUPD_bp Predefined. */
+
+/* TC1_DIR_bm Predefined. */
+/* TC1_DIR_bp Predefined. */
+
+
+/* TC1.CTRLGCLR bit masks and bit positions */
+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC1.CTRLGSET bit masks and bit positions */
+/* TC1_CCBBV_bm Predefined. */
+/* TC1_CCBBV_bp Predefined. */
+
+/* TC1_CCABV_bm Predefined. */
+/* TC1_CCABV_bp Predefined. */
+
+/* TC1_PERBV_bm Predefined. */
+/* TC1_PERBV_bp Predefined. */
+
+
+/* TC1.INTFLAGS bit masks and bit positions */
+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* AWEX.CTRL bit masks and bit positions */
+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
+
+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
+
+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
+
+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
+
+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
+
+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+
+/* AWEX.FDCTRL bit masks and bit positions */
+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+
+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
+
+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+
+/* AWEX.STATUS bit masks and bit positions */
+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+
+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
+
+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
+
+/* HIRES.CTRLA bit masks and bit positions */
+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS bit masks and bit positions */
+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
+
+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
+
+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
+
+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
+#define USART_FERR_bp 4 /* Frame Error bit position. */
+
+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
+
+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
+#define USART_PERR_bp 2 /* Parity Error bit position. */
+
+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+
+/* USART.CTRLA bit masks and bit positions */
+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
+
+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
+
+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+
+/* USART.CTRLB bit masks and bit positions */
+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+
+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
+
+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
+
+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
+
+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+
+/* USART.CTRLC bit masks and bit positions */
+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+#define USART_CMODE_gp 6 /* Communication Mode group position. */
+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
+
+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
+#define USART_PMODE_gp 4 /* Parity Mode group position. */
+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
+
+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
+
+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
+#define USART_CHSIZE_gp 0 /* Character Size group position. */
+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+
+/* USART.BAUDCTRLA bit masks and bit positions */
+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+
+/* USART.BAUDCTRLB bit masks and bit positions */
+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+/* USART_BSEL_gm Predefined. */
+/* USART_BSEL_gp Predefined. */
+/* USART_BSEL0_bm Predefined. */
+/* USART_BSEL0_bp Predefined. */
+/* USART_BSEL1_bm Predefined. */
+/* USART_BSEL1_bp Predefined. */
+/* USART_BSEL2_bm Predefined. */
+/* USART_BSEL2_bp Predefined. */
+/* USART_BSEL3_bm Predefined. */
+/* USART_BSEL3_bp Predefined. */
+
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL bit masks and bit positions */
+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
+
+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
+
+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
+
+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
+
+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
+#define SPI_MODE_gp 2 /* SPI Mode group position. */
+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
+
+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+
+/* SPI.INTCTRL bit masks and bit positions */
+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+
+/* SPI.STATUS bit masks and bit positions */
+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+
+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL bit masks and bit positions */
+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_XOSCF_vect_num 1
+#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num 2
+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
+#define PORTC_INT1_vect_num 3
+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num 4
+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
+#define PORTR_INT1_vect_num 5
+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num 10
+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
+#define RTC_COMP_vect_num 11
+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num 12
+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num 13
+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num 14
+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
+#define TCC0_ERR_vect_num 15
+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
+#define TCC0_CCA_vect_num 16
+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
+#define TCC0_CCB_vect_num 17
+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
+#define TCC0_CCC_vect_num 18
+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
+#define TCC0_CCD_vect_num 19
+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num 20
+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+#define TCC1_ERR_vect_num 21
+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
+#define TCC1_CCA_vect_num 22
+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num 23
+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num 24
+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num 25
+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num 26
+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num 27
+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num 32
+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
+#define NVM_SPM_vect_num 33
+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num 34
+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
+#define PORTB_INT1_vect_num 35
+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num 43
+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
+#define PORTE_INT1_vect_num 44
+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num 47
+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
+#define TCE0_ERR_vect_num 48
+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
+#define TCE0_CCA_vect_num 49
+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
+#define TCE0_CCB_vect_num 50
+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
+#define TCE0_CCC_vect_num 51
+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
+#define TCE0_CCD_vect_num 52
+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num 58
+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num 59
+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num 60
+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num 64
+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
+#define PORTD_INT1_vect_num 65
+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num 66
+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
+#define PORTA_INT1_vect_num 67
+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num 68
+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
+#define ACA_AC1_vect_num 69
+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
+#define ACA_ACW_vect_num 70
+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num 71
+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num 77
+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
+#define TCD0_ERR_vect_num 78
+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
+#define TCD0_CCA_vect_num 79
+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
+#define TCD0_CCB_vect_num 80
+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
+#define TCD0_CCC_vect_num 81
+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
+#define TCD0_CCD_vect_num 82
+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num 87
+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num 88
+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num 89
+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num 90
+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num 104
+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
+#define PORTF_INT1_vect_num 105
+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num 108
+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
+#define TCF0_ERR_vect_num 109
+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
+#define TCF0_CCA_vect_num 110
+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
+#define TCF0_CCB_vect_num 111
+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
+#define TCF0_CCC_vect_num 112
+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
+#define TCF0_CCD_vect_num 113
+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#define PROGMEM_START (0x0000)
+#define PROGMEM_SIZE (204800)
+#define PROGMEM_PAGE_SIZE (512)
+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#define APP_SECTION_START (0x0000)
+#define APP_SECTION_SIZE (196608)
+#define APP_SECTION_PAGE_SIZE (512)
+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#define APPTABLE_SECTION_START (0x2E000)
+#define APPTABLE_SECTION_SIZE (8192)
+#define APPTABLE_SECTION_PAGE_SIZE (512)
+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#define BOOT_SECTION_START (0x30000)
+#define BOOT_SECTION_SIZE (8192)
+#define BOOT_SECTION_PAGE_SIZE (512)
+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#define DATAMEM_START (0x0000)
+#define DATAMEM_SIZE (24576)
+#define DATAMEM_PAGE_SIZE (0)
+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#define IO_START (0x0000)
+#define IO_SIZE (4096)
+#define IO_PAGE_SIZE (0)
+#define IO_END (IO_START + IO_SIZE - 1)
+
+#define MAPPED_EEPROM_START (0x1000)
+#define MAPPED_EEPROM_SIZE (2048)
+#define MAPPED_EEPROM_PAGE_SIZE (0)
+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#define INTERNAL_SRAM_START (0x2000)
+#define INTERNAL_SRAM_SIZE (16384)
+#define INTERNAL_SRAM_PAGE_SIZE (0)
+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#define EEPROM_START (0x0000)
+#define EEPROM_SIZE (2048)
+#define EEPROM_PAGE_SIZE (32)
+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+#define FUSE_START (0x0000)
+#define FUSE_SIZE (6)
+#define FUSE_PAGE_SIZE (0)
+#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+
+#define LOCKBIT_START (0x0000)
+#define LOCKBIT_SIZE (1)
+#define LOCKBIT_PAGE_SIZE (0)
+#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
+
+#define SIGNATURES_START (0x0000)
+#define SIGNATURES_SIZE (3)
+#define SIGNATURES_PAGE_SIZE (0)
+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#define USER_SIGNATURES_START (0x0000)
+#define USER_SIGNATURES_SIZE (512)
+#define USER_SIGNATURES_PAGE_SIZE (0)
+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#define PROD_SIGNATURES_START (0x0000)
+#define PROD_SIGNATURES_SIZE (52)
+#define PROD_SIGNATURES_PAGE_SIZE (0)
+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHEND PROGMEM_END
+#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
+#define RAMSTART INTERNAL_SRAM_START
+#define RAMSIZE INTERNAL_SRAM_SIZE
+#define RAMEND INTERNAL_SRAM_END
+#define XRAMSTART EXTERNAL_SRAM_START
+#define XRAMSIZE EXTERNAL_SRAM_SIZE
+#define XRAMEND INTERNAL_SRAM_END
+#define E2END EEPROM_END
+#define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
+#define FUSE0_DEFAULT (0xFF)
+
+/* Fuse Byte 1 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT (0xFF)
+
+/* Fuse Byte 2 */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
+#define FUSE2_DEFAULT (0xFF)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE4_DEFAULT (0xFF)
+
+/* Fuse Byte 5 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT (0xFF)
+
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x49
+
+
+#endif /* _AVR_ATxmega192D3_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iox256a3.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox256a3.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox256a3.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox256a3.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox256a3.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega256A3_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6438,21 +6438,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -6826,50 +6826,50 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0 ~_BV(0) /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1 ~_BV(1) /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2 ~_BV(2) /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3 ~_BV(3) /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4 ~_BV(4) /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5 ~_BV(5) /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6 ~_BV(6) /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7 ~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_JTAGEN ~_BV(0) /* JTAG Interface Enable */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iox256a3b.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox256a3b.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox256a3b.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox256a3b.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox256a3b.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega256A3B_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6452,21 +6452,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -6828,50 +6828,50 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0 ~_BV(0) /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1 ~_BV(1) /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2 ~_BV(2) /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3 ~_BV(3) /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4 ~_BV(4) /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5 ~_BV(5) /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6 ~_BV(6) /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7 ~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_JTAGEN ~_BV(0) /* JTAG Interface Enable */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iox256d3.h:1.1
--- /dev/null Mon May 10 12:11:02 2010
+++ rtems/cpukit/score/cpu/avr/avr/iox256d3.h Mon May 10 11:31:23 2010
@@ -0,0 +1,5456 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iox256d3.h - definitions for ATxmega256D3 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iox256d3.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATxmega256D3_H_
+#define _AVR_ATxmega256D3_H_ 1
+
+
+/* Ungrouped common registers */
+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+#define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register16_t regname; \
+ struct \
+ { \
+ register8_t regname ## L; \
+ register8_t regname ## H; \
+ }; \
+ }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register32_t regname; \
+ struct \
+ { \
+ register8_t regname ## 0; \
+ register8_t regname ## 1; \
+ register8_t regname ## 2; \
+ register8_t regname ## 3; \
+ }; \
+ }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+ register8_t OCDR0; /* OCD Register 0 */
+ register8_t OCDR1; /* OCD Register 1 */
+} OCD_t;
+
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
+} CCP_t;
+
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t PSCTRL; /* Prescaler Control Register */
+ register8_t LOCK; /* Lock register */
+ register8_t RTCCTRL; /* RTC Control Register */
+} CLK_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
+} CLK_RTCSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+ register8_t CTRL; /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
+ register8_t PLLCTRL; /* PLL Control REgister */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+} OSC_PLLSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t CALA; /* Calibration Register A */
+ register8_t CALB; /* Calibration Register B */
+ register8_t COMP0; /* Oscillator Compare Register 0 */
+ register8_t COMP1; /* Oscillator Compare Register 1 */
+ register8_t COMP2; /* Oscillator Compare Register 2 */
+ register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t CTRL; /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t WINCTRL; /* Windowed Mode Control */
+ register8_t STATUS; /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+ register8_t DEVID0; /* Device ID byte 0 */
+ register8_t DEVID1; /* Device ID byte 1 */
+ register8_t DEVID2; /* Device ID byte 2 */
+ register8_t REVID; /* Revision ID */
+ register8_t JTAGUID; /* JTAG User ID */
+ register8_t reserved_0x05;
+ register8_t MCUCR; /* MCU Control */
+ register8_t reserved_0x07;
+ register8_t EVSYSLOCK; /* Event System Lock */
+ register8_t AWEXLOCK; /* AWEX Lock */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t INTPRI; /* Interrupt Priority */
+ register8_t CTRL; /* Control Register */
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
+ register8_t CH0CTRL; /* Channel 0 Control Register */
+ register8_t CH1CTRL; /* Channel 1 Control Register */
+ register8_t CH2CTRL; /* Channel 2 Control Register */
+ register8_t CH3CTRL; /* Channel 3 Control Register */
+ register8_t STROBE; /* Event Strobe */
+ register8_t DATA; /* Event Data */
+} EVSYS_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+ register8_t ADDR0; /* Address Register 0 */
+ register8_t ADDR1; /* Address Register 1 */
+ register8_t ADDR2; /* Address Register 2 */
+ register8_t reserved_0x03;
+ register8_t DATA0; /* Data Register 0 */
+ register8_t DATA1; /* Data Register 1 */
+ register8_t DATA2; /* Data Register 2 */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t CMD; /* Command */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t INTCTRL; /* Interrupt Control */
+ register8_t reserved_0x0E;
+ register8_t STATUS; /* Status */
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_LOCKBITS_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+ register8_t FUSEBYTE0; /* User ID */
+ register8_t FUSEBYTE1; /* Watchdog Configuration */
+ register8_t FUSEBYTE2; /* Reset Configuration */
+ register8_t reserved_0x03;
+ register8_t FUSEBYTE4; /* Start-up Configuration */
+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
+ register8_t reserved_0x01;
+ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
+ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
+ register8_t reserved_0x04;
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t WAFNUM; /* Wafer Number */
+ register8_t reserved_0x11;
+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
+ register8_t reserved_0x26;
+ register8_t reserved_0x27;
+ register8_t reserved_0x28;
+ register8_t reserved_0x29;
+ register8_t reserved_0x2A;
+ register8_t reserved_0x2B;
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ register8_t reserved_0x36;
+ register8_t reserved_0x37;
+ register8_t reserved_0x38;
+ register8_t reserved_0x39;
+ register8_t reserved_0x3A;
+ register8_t reserved_0x3B;
+ register8_t reserved_0x3C;
+ register8_t reserved_0x3D;
+ register8_t reserved_0x3E;
+} NVM_PROD_SIGNATURES_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
+} NVM_CMD_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
+} NVM_SPMLVL_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
+} NVM_EELVL_t;
+
+/* Boot lock bits - boot setcion */
+typedef enum NVM_BLBB_enum
+{
+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
+} NVM_BLBB_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
+} NVM_BLBAT_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
+} NVM_LB_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
+} BOOTRST_t;
+
+/* BOD operation */
+typedef enum BOD_enum
+{
+ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
+ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
+} BOD_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WD_enum
+{
+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
+} WD_t;
+
+/* Start-up Time */
+typedef enum SUT_enum
+{
+ SUT_0MS_gc = (0x03<<2), /* 0 ms */
+ SUT_4MS_gc = (0x01<<2), /* 4 ms */
+ SUT_64MS_gc = (0x00<<2), /* 64 ms */
+} SUT_t;
+
+/* Brown Out Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
+ BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */
+ BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */
+ BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */
+ BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */
+ BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */
+ BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */
+} BODLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+ register8_t AC0CTRL; /* Comparator 0 Control */
+ register8_t AC1CTRL; /* Comparator 1 Control */
+ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
+ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t WINCTRL; /* Window Mode Control */
+ register8_t STATUS; /* Status */
+} AC_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
+} AC_INTLVL_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
+} AC_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
+} AC_WINTLVL_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
+} AC_WSTATE_t;
+
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+ register8_t INTCTRL; /* Channel Interrupt Control */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+ register8_t reserved_0x6;
+ register8_t reserved_0x7;
+} ADC_CH_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t REFCTRL; /* Reference Control */
+ register8_t EVCTRL; /* Event Control */
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t reserved_0x05;
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* ACD Temporary Register */
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ _WORDREGISTER(CAL); /* Calibration Value */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ _WORDREGISTER(CH0RES); /* Channel 0 Result */
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ _WORDREGISTER(CMP); /* Compare Value */
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ ADC_CH_t CH0; /* ADC Channel 0 */
+} ADC_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
+} ADC_CH_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
+ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
+ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
+ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
+ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
+} ADC_CH_MUXNEG_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+} ADC_CH_GAIN_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
+ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
+} ADC_REFSEL_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
+} ADC_EVACT_t;
+
+/* Interupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
+} ADC_CH_INTLVL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Clounter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ _WORDREGISTER(CNT); /* Count Register */
+ _WORDREGISTER(PER); /* Period Register */
+ _WORDREGISTER(COMP); /* Compare Register */
+} RTC_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} RTC_OVFINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+ register8_t CTRLA; /* Chip Select Control Register A */
+ register8_t CTRLB; /* Chip Select Control Register B */
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+} EBI_CS_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t SDRAMCTRLA; /* SDRAM Control Register A */
+ register8_t reserved_0x02;
+ register8_t reserved_0x03;
+ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
+ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
+ register8_t SDRAMCTRLB; /* SDRAM Control Register B */
+ register8_t SDRAMCTRLC; /* SDRAM Control Register C */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ EBI_CS_t CS0; /* Chip Select 0 */
+ EBI_CS_t CS1; /* Chip Select 1 */
+ EBI_CS_t CS2; /* Chip Select 2 */
+ EBI_CS_t CS3; /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select adress space */
+typedef enum EBI_CS_ASPACE_enum
+{
+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* */
+typedef enum EBI_CS_SRWS_enum
+{
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
+ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
+ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
+ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
+ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* */
+typedef enum EBI_SDDATAW_enum
+{
+ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
+ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/* */
+typedef enum EBI_LPCMODE_enum
+{
+ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
+ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* */
+typedef enum EBI_SRMODE_enum
+{
+ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
+ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
+ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
+ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* */
+typedef enum EBI_IFMODE_enum
+{
+ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
+ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
+ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
+ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
+} EBI_IFMODE_t;
+
+/* */
+typedef enum EBI_SDCOL_enum
+{
+ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
+ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
+ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+} EBI_SDCOL_t;
+
+/* */
+typedef enum EBI_MRDLY_enum
+{
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* */
+typedef enum EBI_ROWCYCDLY_enum
+{
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* */
+typedef enum EBI_RPDLY_enum
+{
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_RPDLY_t;
+
+/* */
+typedef enum EBI_WRDLY_enum
+{
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_WRDLY_t;
+
+/* */
+typedef enum EBI_ESRDLY_enum
+{
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/* */
+typedef enum EBI_ROWCOLDLY_enum
+{
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_MASTER_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t STATUS; /* Status Register */
+ register8_t BAUD; /* Baurd Rate Control Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+} TWI_MASTER_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_SLAVE_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+ register8_t ADDRMASK; /* Address Mask Register */
+} TWI_SLAVE_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+ register8_t CTRL; /* TWI Common Control Register */
+ TWI_MASTER_t MASTER; /* TWI master module */
+ TWI_SLAVE_t SLAVE; /* TWI slave module */
+} TWI_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+ register8_t MPCMASK; /* Multi-pin Configuration Mask */
+ register8_t reserved_0x01;
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
+} PORTCFG_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t OUT; /* I/O Port Output */
+ register8_t IN; /* I/O Port Input */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+} VPORT_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t DIRSET; /* I/O Port Data Direction Set */
+ register8_t DIRCLR; /* I/O Port Data Direction Clear */
+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
+ register8_t OUT; /* I/O Port Output */
+ register8_t OUTSET; /* I/O Port Output Set */
+ register8_t OUTCLR; /* I/O Port Output Clear */
+ register8_t OUTTGL; /* I/O Port Output Toggle */
+ register8_t IN; /* I/O port Input */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INT0MASK; /* Port Interrupt 0 Mask */
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+ register8_t PIN2CTRL; /* Pin 2 Control Register */
+ register8_t PIN3CTRL; /* Pin 3 Control Register */
+ register8_t PIN4CTRL; /* Pin 4 Control Register */
+ register8_t PIN5CTRL; /* Pin 5 Control Register */
+ register8_t PIN6CTRL; /* Pin 6 Control Register */
+ register8_t PIN7CTRL; /* Pin 7 Control Register */
+} PORT_t;
+
+/* Virtual Port 0 Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Virtual Port 1 Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Virtual Port 2 Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port 3 Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/* Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
+} PORT_INT1LVL_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ _WORDREGISTER(CCC); /* Compare or Capture C */
+ _WORDREGISTER(CCD); /* Compare or Capture D */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+} TC0_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x05;
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+ register8_t DTHS; /* Dead Time High Side */
+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
+ register8_t DTHSBUF; /* Dead Time High Side Buffer */
+ register8_t OUTOVEN; /* Output Override Enable */
+} AWEX_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+ register8_t CTRLA; /* Control Register */
+} HIRES_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+ register8_t DATA; /* Data Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
+} USART_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
+} USART_TXCINTLVL_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
+} USART_DREINTLVL_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
+} USART_PMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t DATA; /* Data Register */
+} SPI_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} SPI_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRDA_EVSEL_enum
+{
+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
+} IRDA_EVSEL_t;
+
+
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
+#define CLK (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
+#define RST (*(RST_t *) 0x0078) /* Reset Controller */
+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
+#define GPIO_GPIORA _SFR_MEM8(0x000A)
+#define GPIO_GPIORB _SFR_MEM8(0x000B)
+#define GPIO_GPIORC _SFR_MEM8(0x000C)
+#define GPIO_GPIORD _SFR_MEM8(0x000D)
+#define GPIO_GPIORE _SFR_MEM8(0x000E)
+#define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+/* VPORT0 - Virtual Port 0 */
+#define VPORT0_DIR _SFR_MEM8(0x0010)
+#define VPORT0_OUT _SFR_MEM8(0x0011)
+#define VPORT0_IN _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+/* VPORT1 - Virtual Port 1 */
+#define VPORT1_DIR _SFR_MEM8(0x0014)
+#define VPORT1_OUT _SFR_MEM8(0x0015)
+#define VPORT1_IN _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+/* VPORT2 - Virtual Port 2 */
+#define VPORT2_DIR _SFR_MEM8(0x0018)
+#define VPORT2_OUT _SFR_MEM8(0x0019)
+#define VPORT2_IN _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+/* VPORT3 - Virtual Port 3 */
+#define VPORT3_DIR _SFR_MEM8(0x001C)
+#define VPORT3_OUT _SFR_MEM8(0x001D)
+#define VPORT3_IN _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0 _SFR_MEM8(0x002E)
+#define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+/* CPU - CPU Registers */
+#define CPU_CCP _SFR_MEM8(0x0034)
+#define CPU_RAMPD _SFR_MEM8(0x0038)
+#define CPU_RAMPX _SFR_MEM8(0x0039)
+#define CPU_RAMPY _SFR_MEM8(0x003A)
+#define CPU_RAMPZ _SFR_MEM8(0x003B)
+#define CPU_EIND _SFR_MEM8(0x003C)
+#define CPU_SPL _SFR_MEM8(0x003D)
+#define CPU_SPH _SFR_MEM8(0x003E)
+#define CPU_SREG _SFR_MEM8(0x003F)
+
+/* CLK - Clock System */
+#define CLK_CTRL _SFR_MEM8(0x0040)
+#define CLK_PSCTRL _SFR_MEM8(0x0041)
+#define CLK_LOCK _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL _SFR_MEM8(0x0043)
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+/* OSC - Oscillator Control */
+#define OSC_CTRL _SFR_MEM8(0x0050)
+#define OSC_STATUS _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+
+/* RST - Reset Controller */
+#define RST_STATUS _SFR_MEM8(0x0078)
+#define RST_CTRL _SFR_MEM8(0x0079)
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL _SFR_MEM8(0x0080)
+#define WDT_WINCTRL _SFR_MEM8(0x0081)
+#define WDT_STATUS _SFR_MEM8(0x0082)
+
+/* MCU - MCU Control */
+#define MCU_DEVID0 _SFR_MEM8(0x0090)
+#define MCU_DEVID1 _SFR_MEM8(0x0091)
+#define MCU_DEVID2 _SFR_MEM8(0x0092)
+#define MCU_REVID _SFR_MEM8(0x0093)
+#define MCU_JTAGUID _SFR_MEM8(0x0094)
+#define MCU_MCUCR _SFR_MEM8(0x0096)
+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+/* PMIC - Programmable Interrupt Controller */
+#define PMIC_STATUS _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI _SFR_MEM8(0x00A1)
+#define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+/* PORTCFG - Port Configuration */
+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
+#define EVSYS_STROBE _SFR_MEM8(0x0190)
+#define EVSYS_DATA _SFR_MEM8(0x0191)
+
+/* NVM - Non Volatile Memory Controller */
+#define NVM_ADDR0 _SFR_MEM8(0x01C0)
+#define NVM_ADDR1 _SFR_MEM8(0x01C1)
+#define NVM_ADDR2 _SFR_MEM8(0x01C2)
+#define NVM_DATA0 _SFR_MEM8(0x01C4)
+#define NVM_DATA1 _SFR_MEM8(0x01C5)
+#define NVM_DATA2 _SFR_MEM8(0x01C6)
+#define NVM_CMD _SFR_MEM8(0x01CA)
+#define NVM_CTRLA _SFR_MEM8(0x01CB)
+#define NVM_CTRLB _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL _SFR_MEM8(0x01CD)
+#define NVM_STATUS _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+/* ADCA - Analog to Digital Converter A */
+#define ADCA_CTRLA _SFR_MEM8(0x0200)
+#define ADCA_CTRLB _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER _SFR_MEM8(0x0204)
+#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
+#define ADCA_TEMP _SFR_MEM8(0x0207)
+#define ADCA_CAL _SFR_MEM16(0x020C)
+#define ADCA_CH0RES _SFR_MEM16(0x0210)
+#define ADCA_CMP _SFR_MEM16(0x0218)
+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES _SFR_MEM16(0x0224)
+
+/* ACA - Analog Comparator A */
+#define ACA_AC0CTRL _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
+#define ACA_CTRLA _SFR_MEM8(0x0384)
+#define ACA_CTRLB _SFR_MEM8(0x0385)
+#define ACA_WINCTRL _SFR_MEM8(0x0386)
+#define ACA_STATUS _SFR_MEM8(0x0387)
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL _SFR_MEM8(0x0400)
+#define RTC_STATUS _SFR_MEM8(0x0401)
+#define RTC_INTCTRL _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS _SFR_MEM8(0x0403)
+#define RTC_TEMP _SFR_MEM8(0x0404)
+#define RTC_CNT _SFR_MEM16(0x0408)
+#define RTC_PER _SFR_MEM16(0x040A)
+#define RTC_COMP _SFR_MEM16(0x040C)
+
+/* TWIC - Two-Wire Interface C */
+#define TWIC_CTRL _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+/* PORTA - Port A */
+#define PORTA_DIR _SFR_MEM8(0x0600)
+#define PORTA_DIRSET _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL _SFR_MEM8(0x0603)
+#define PORTA_OUT _SFR_MEM8(0x0604)
+#define PORTA_OUTSET _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL _SFR_MEM8(0x0607)
+#define PORTA_IN _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+/* PORTB - Port B */
+#define PORTB_DIR _SFR_MEM8(0x0620)
+#define PORTB_DIRSET _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL _SFR_MEM8(0x0623)
+#define PORTB_OUT _SFR_MEM8(0x0624)
+#define PORTB_OUTSET _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL _SFR_MEM8(0x0627)
+#define PORTB_IN _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+/* PORTC - Port C */
+#define PORTC_DIR _SFR_MEM8(0x0640)
+#define PORTC_DIRSET _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL _SFR_MEM8(0x0643)
+#define PORTC_OUT _SFR_MEM8(0x0644)
+#define PORTC_OUTSET _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL _SFR_MEM8(0x0647)
+#define PORTC_IN _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+/* PORTD - Port D */
+#define PORTD_DIR _SFR_MEM8(0x0660)
+#define PORTD_DIRSET _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL _SFR_MEM8(0x0663)
+#define PORTD_OUT _SFR_MEM8(0x0664)
+#define PORTD_OUTSET _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL _SFR_MEM8(0x0667)
+#define PORTD_IN _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+/* PORTE - Port E */
+#define PORTE_DIR _SFR_MEM8(0x0680)
+#define PORTE_DIRSET _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL _SFR_MEM8(0x0683)
+#define PORTE_OUT _SFR_MEM8(0x0684)
+#define PORTE_OUTSET _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL _SFR_MEM8(0x0687)
+#define PORTE_IN _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+/* PORTF - Port F */
+#define PORTF_DIR _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
+#define PORTF_OUT _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
+#define PORTF_IN _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+/* PORTR - Port R */
+#define PORTR_DIR _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
+#define PORTR_OUT _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
+#define PORTR_IN _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+/* TCC0 - Timer/Counter C0 */
+#define TCC0_CTRLA _SFR_MEM8(0x0800)
+#define TCC0_CTRLB _SFR_MEM8(0x0801)
+#define TCC0_CTRLC _SFR_MEM8(0x0802)
+#define TCC0_CTRLD _SFR_MEM8(0x0803)
+#define TCC0_CTRLE _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
+#define TCC0_TEMP _SFR_MEM8(0x080F)
+#define TCC0_CNT _SFR_MEM16(0x0820)
+#define TCC0_PER _SFR_MEM16(0x0826)
+#define TCC0_CCA _SFR_MEM16(0x0828)
+#define TCC0_CCB _SFR_MEM16(0x082A)
+#define TCC0_CCC _SFR_MEM16(0x082C)
+#define TCC0_CCD _SFR_MEM16(0x082E)
+#define TCC0_PERBUF _SFR_MEM16(0x0836)
+#define TCC0_CCABUF _SFR_MEM16(0x0838)
+#define TCC0_CCBBUF _SFR_MEM16(0x083A)
+#define TCC0_CCCBUF _SFR_MEM16(0x083C)
+#define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+/* TCC1 - Timer/Counter C1 */
+#define TCC1_CTRLA _SFR_MEM8(0x0840)
+#define TCC1_CTRLB _SFR_MEM8(0x0841)
+#define TCC1_CTRLC _SFR_MEM8(0x0842)
+#define TCC1_CTRLD _SFR_MEM8(0x0843)
+#define TCC1_CTRLE _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
+#define TCC1_TEMP _SFR_MEM8(0x084F)
+#define TCC1_CNT _SFR_MEM16(0x0860)
+#define TCC1_PER _SFR_MEM16(0x0866)
+#define TCC1_CCA _SFR_MEM16(0x0868)
+#define TCC1_CCB _SFR_MEM16(0x086A)
+#define TCC1_PERBUF _SFR_MEM16(0x0876)
+#define TCC1_CCABUF _SFR_MEM16(0x0878)
+#define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+/* AWEXC - Advanced Waveform Extension C */
+#define AWEXC_CTRL _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+#define AWEXC_STATUS _SFR_MEM8(0x0884)
+#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+#define AWEXC_DTLS _SFR_MEM8(0x0888)
+#define AWEXC_DTHS _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+/* HIRESC - High-Resolution Extension C */
+#define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0_DATA _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+/* SPIC - Serial Peripheral Interface C */
+#define SPIC_CTRL _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+#define SPIC_STATUS _SFR_MEM8(0x08C2)
+#define SPIC_DATA _SFR_MEM8(0x08C3)
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_CTRL _SFR_MEM8(0x08F8)
+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
+
+/* TCD0 - Timer/Counter D0 */
+#define TCD0_CTRLA _SFR_MEM8(0x0900)
+#define TCD0_CTRLB _SFR_MEM8(0x0901)
+#define TCD0_CTRLC _SFR_MEM8(0x0902)
+#define TCD0_CTRLD _SFR_MEM8(0x0903)
+#define TCD0_CTRLE _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
+#define TCD0_TEMP _SFR_MEM8(0x090F)
+#define TCD0_CNT _SFR_MEM16(0x0920)
+#define TCD0_PER _SFR_MEM16(0x0926)
+#define TCD0_CCA _SFR_MEM16(0x0928)
+#define TCD0_CCB _SFR_MEM16(0x092A)
+#define TCD0_CCC _SFR_MEM16(0x092C)
+#define TCD0_CCD _SFR_MEM16(0x092E)
+#define TCD0_PERBUF _SFR_MEM16(0x0936)
+#define TCD0_CCABUF _SFR_MEM16(0x0938)
+#define TCD0_CCBBUF _SFR_MEM16(0x093A)
+#define TCD0_CCCBUF _SFR_MEM16(0x093C)
+#define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0_DATA _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+/* SPID - Serial Peripheral Interface D */
+#define SPID_CTRL _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL _SFR_MEM8(0x09C1)
+#define SPID_STATUS _SFR_MEM8(0x09C2)
+#define SPID_DATA _SFR_MEM8(0x09C3)
+
+/* TCE0 - Timer/Counter E0 */
+#define TCE0_CTRLA _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP _SFR_MEM8(0x0A0F)
+#define TCE0_CNT _SFR_MEM16(0x0A20)
+#define TCE0_PER _SFR_MEM16(0x0A26)
+#define TCE0_CCA _SFR_MEM16(0x0A28)
+#define TCE0_CCB _SFR_MEM16(0x0A2A)
+#define TCE0_CCC _SFR_MEM16(0x0A2C)
+#define TCE0_CCD _SFR_MEM16(0x0A2E)
+#define TCE0_PERBUF _SFR_MEM16(0x0A36)
+#define TCE0_CCABUF _SFR_MEM16(0x0A38)
+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+/* AWEXE - Advanced Waveform Extension E */
+#define AWEXE_CTRL _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS _SFR_MEM8(0x0A84)
+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0_DATA _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+/* SPIE - Serial Peripheral Interface E */
+#define SPIE_CTRL _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS _SFR_MEM8(0x0AC2)
+#define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+/* TCF0 - Timer/Counter F0 */
+#define TCF0_CTRLA _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP _SFR_MEM8(0x0B0F)
+#define TCF0_CNT _SFR_MEM16(0x0B20)
+#define TCF0_PER _SFR_MEM16(0x0B26)
+#define TCF0_CCA _SFR_MEM16(0x0B28)
+#define TCF0_CCB _SFR_MEM16(0x0B2A)
+#define TCF0_CCC _SFR_MEM16(0x0B2C)
+#define TCF0_CCD _SFR_MEM16(0x0B2E)
+#define TCF0_PERBUF _SFR_MEM16(0x0B36)
+#define TCF0_CCABUF _SFR_MEM16(0x0B38)
+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR1 bit masks and bit positions */
+#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+
+/* CPU - CPU */
+/* CPU.CCP bit masks and bit positions */
+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+#define CPU_CCP_gp 0 /* CCP signature group position. */
+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+
+/* CPU.SREG bit masks and bit positions */
+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+
+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
+#define CPU_T_bp 6 /* Transfer Bit bit position. */
+
+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
+#define CPU_H_bp 5 /* Half Carry Flag bit position. */
+
+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
+
+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
+
+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
+#define CPU_N_bp 2 /* Negative Flag bit position. */
+
+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
+#define CPU_Z_bp 1 /* Zero Flag bit position. */
+
+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+#define CPU_C_bp 0 /* Carry Flag bit position. */
+
+
+/* CLK - Clock System */
+/* CLK.CTRL bit masks and bit positions */
+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+
+/* CLK.PSCTRL bit masks and bit positions */
+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
+
+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+
+/* CLK.LOCK bit masks and bit positions */
+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+
+/* CLK.RTCCTRL bit masks and bit positions */
+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
+
+#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL bit masks and bit positions */
+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
+
+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+
+/* OSC - Oscillator */
+/* OSC.CTRL bit masks and bit positions */
+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
+
+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
+
+#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
+
+#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
+
+#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
+
+
+/* OSC.STATUS bit masks and bit positions */
+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+
+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
+
+#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
+
+#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
+
+#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
+
+
+/* OSC.XOSCCTRL bit masks and bit positions */
+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
+
+#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
+
+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+
+/* OSC.XOSCFAIL bit masks and bit positions */
+#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
+
+#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
+
+
+/* OSC.PLLCTRL bit masks and bit positions */
+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+
+/* OSC.DFLLCTRL bit masks and bit positions */
+#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
+#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
+
+#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL bit masks and bit positions */
+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+
+/* DFLL.CALA bit masks and bit positions */
+#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
+#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
+#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
+#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
+#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
+#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
+#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
+#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
+#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
+
+
+/* DFLL.CALB bit masks and bit positions */
+#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
+#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
+#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
+#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
+#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
+#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
+#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
+#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
+
+
+/* RST - Reset */
+/* RST.STATUS bit masks and bit positions */
+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
+
+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
+
+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
+
+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
+
+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
+
+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
+
+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+
+/* RST.CTRL bit masks and bit positions */
+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+#define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL bit masks and bit positions */
+#define WDT_PER_gm 0x3C /* Period group mask. */
+#define WDT_PER_gp 2 /* Period group position. */
+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
+#define WDT_PER0_bp 2 /* Period bit 0 position. */
+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
+#define WDT_PER1_bp 3 /* Period bit 1 position. */
+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
+#define WDT_PER2_bp 4 /* Period bit 2 position. */
+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
+#define WDT_PER3_bp 5 /* Period bit 3 position. */
+
+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
+#define WDT_ENABLE_bp 1 /* Enable bit position. */
+
+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+#define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+
+/* WDT.WINCTRL bit masks and bit positions */
+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
+
+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
+
+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+
+/* WDT.STATUS bit masks and bit positions */
+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR bit masks and bit positions */
+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+
+/* MCU.EVSYSLOCK bit masks and bit positions */
+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
+
+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+
+/* MCU.AWEXLOCK bit masks and bit positions */
+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS bit masks and bit positions */
+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
+
+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
+
+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
+
+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+
+/* PMIC.CTRL bit masks and bit positions */
+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+
+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
+
+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
+
+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
+
+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX bit masks and bit positions */
+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+
+/* EVSYS.CH1MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH2MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH3MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH0CTRL bit masks and bit positions */
+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
+
+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
+
+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+
+/* EVSYS.CH1CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH2CTRL bit masks and bit positions */
+/* EVSYS_QDIRM_gm Predefined. */
+/* EVSYS_QDIRM_gp Predefined. */
+/* EVSYS_QDIRM0_bm Predefined. */
+/* EVSYS_QDIRM0_bp Predefined. */
+/* EVSYS_QDIRM1_bm Predefined. */
+/* EVSYS_QDIRM1_bp Predefined. */
+
+/* EVSYS_QDIEN_bm Predefined. */
+/* EVSYS_QDIEN_bp Predefined. */
+
+/* EVSYS_QDEN_bm Predefined. */
+/* EVSYS_QDEN_bp Predefined. */
+
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH3CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD bit masks and bit positions */
+#define NVM_CMD_gm 0xFF /* Command group mask. */
+#define NVM_CMD_gp 0 /* Command group position. */
+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define NVM_CMD0_bp 0 /* Command bit 0 position. */
+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define NVM_CMD1_bp 1 /* Command bit 1 position. */
+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
+#define NVM_CMD2_bp 2 /* Command bit 2 position. */
+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
+#define NVM_CMD3_bp 3 /* Command bit 3 position. */
+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
+#define NVM_CMD4_bp 4 /* Command bit 4 position. */
+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
+#define NVM_CMD5_bp 5 /* Command bit 5 position. */
+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+#define NVM_CMD6_bp 6 /* Command bit 6 position. */
+#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
+#define NVM_CMD7_bp 7 /* Command bit 7 position. */
+
+
+/* NVM.CTRLA bit masks and bit positions */
+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+
+/* NVM.CTRLB bit masks and bit positions */
+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+
+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
+
+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
+
+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+
+/* NVM.INTCTRL bit masks and bit positions */
+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
+
+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+
+/* NVM.STATUS bit masks and bit positions */
+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+
+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
+
+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
+
+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+
+/* NVM.LOCKBITS bit masks and bit positions */
+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
+#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
+#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
+#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
+#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
+#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
+#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
+#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
+#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
+#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
+#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
+#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
+#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
+#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
+#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
+#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
+#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
+#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
+#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
+
+
+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
+
+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
+
+
+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
+#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
+#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
+
+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
+
+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
+
+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
+
+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
+
+
+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
+
+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
+
+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
+
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL bit masks and bit positions */
+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
+
+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
+
+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
+
+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
+
+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+#define AC_ENABLE_bp 0 /* Enable bit position. */
+
+
+/* AC.AC1CTRL bit masks and bit positions */
+/* AC_INTMODE_gm Predefined. */
+/* AC_INTMODE_gp Predefined. */
+/* AC_INTMODE0_bm Predefined. */
+/* AC_INTMODE0_bp Predefined. */
+/* AC_INTMODE1_bm Predefined. */
+/* AC_INTMODE1_bp Predefined. */
+
+/* AC_INTLVL_gm Predefined. */
+/* AC_INTLVL_gp Predefined. */
+/* AC_INTLVL0_bm Predefined. */
+/* AC_INTLVL0_bp Predefined. */
+/* AC_INTLVL1_bm Predefined. */
+/* AC_INTLVL1_bp Predefined. */
+
+/* AC_HSMODE_bm Predefined. */
+/* AC_HSMODE_bp Predefined. */
+
+/* AC_HYSMODE_gm Predefined. */
+/* AC_HYSMODE_gp Predefined. */
+/* AC_HYSMODE0_bm Predefined. */
+/* AC_HYSMODE0_bp Predefined. */
+/* AC_HYSMODE1_bm Predefined. */
+/* AC_HYSMODE1_bp Predefined. */
+
+/* AC_ENABLE_bm Predefined. */
+/* AC_ENABLE_bp Predefined. */
+
+
+/* AC.AC0MUXCTRL bit masks and bit positions */
+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
+
+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+
+/* AC.AC1MUXCTRL bit masks and bit positions */
+/* AC_MUXPOS_gm Predefined. */
+/* AC_MUXPOS_gp Predefined. */
+/* AC_MUXPOS0_bm Predefined. */
+/* AC_MUXPOS0_bp Predefined. */
+/* AC_MUXPOS1_bm Predefined. */
+/* AC_MUXPOS1_bp Predefined. */
+/* AC_MUXPOS2_bm Predefined. */
+/* AC_MUXPOS2_bp Predefined. */
+
+/* AC_MUXNEG_gm Predefined. */
+/* AC_MUXNEG_gp Predefined. */
+/* AC_MUXNEG0_bm Predefined. */
+/* AC_MUXNEG0_bp Predefined. */
+/* AC_MUXNEG1_bm Predefined. */
+/* AC_MUXNEG1_bp Predefined. */
+/* AC_MUXNEG2_bm Predefined. */
+/* AC_MUXNEG2_bp Predefined. */
+
+
+/* AC.CTRLA bit masks and bit positions */
+#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
+
+
+/* AC.CTRLB bit masks and bit positions */
+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+
+/* AC.WINCTRL bit masks and bit positions */
+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+
+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
+
+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+
+/* AC.STATUS bit masks and bit positions */
+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+#define AC_WSTATE_gp 6 /* Window Mode State group position. */
+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
+
+#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
+
+#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
+
+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
+
+#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
+
+#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
+
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL bit masks and bit positions */
+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
+
+#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
+#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
+#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
+#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
+#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
+
+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+
+/* ADC_CH.MUXCTRL bit masks and bit positions */
+#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
+#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
+#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
+#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
+#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
+#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
+
+#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
+#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
+#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
+#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
+
+
+/* ADC_CH.INTCTRL bit masks and bit positions */
+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
+
+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+
+/* ADC_CH.INTFLAGS bit masks and bit positions */
+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
+
+/* ADC.CTRLA bit masks and bit positions */
+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
+
+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
+
+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+
+/* ADC.CTRLB bit masks and bit positions */
+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+
+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
+
+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+
+/* ADC.REFCTRL bit masks and bit positions */
+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
+
+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
+
+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+
+/* ADC.EVCTRL bit masks and bit positions */
+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
+
+#define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */
+#define ADC_EVACT_bp 0 /* Event Action Select bit position. */
+
+
+/* ADC.PRESCALER bit masks and bit positions */
+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+
+/* ADC.INTFLAGS bit masks and bit positions */
+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+
+/* RTC - Real-Time Clounter */
+/* RTC.CTRL bit masks and bit positions */
+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+
+/* RTC.STATUS bit masks and bit positions */
+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+
+/* RTC.INTCTRL bit masks and bit positions */
+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
+
+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+
+/* RTC.INTFLAGS bit masks and bit positions */
+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+
+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* EBI - External Bus Interface */
+/* EBI_CS.CTRLA bit masks and bit positions */
+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
+#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
+#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+
+/* EBI_CS.CTRLB bit masks and bit positions */
+#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
+#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
+#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
+#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
+#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
+#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
+
+#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
+#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
+
+#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
+#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
+
+#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
+#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
+#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
+#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
+#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+
+/* EBI.CTRL bit masks and bit positions */
+#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
+#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
+#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
+#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
+
+#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
+#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
+#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
+#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
+#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
+#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
+
+#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
+#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
+#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
+#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
+#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
+#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
+
+#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
+#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
+#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
+#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
+#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+
+/* EBI.SDRAMCTRLA bit masks and bit positions */
+#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+
+#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
+#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
+
+#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
+#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
+#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
+#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
+#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+
+/* EBI.SDRAMCTRLB bit masks and bit positions */
+#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
+#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
+#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
+#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
+
+#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
+#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
+#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
+#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
+#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
+#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
+#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
+#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
+
+#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
+#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
+#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
+#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
+#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
+#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
+#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+
+/* EBI.SDRAMCTRLC bit masks and bit positions */
+#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
+#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
+#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
+#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
+
+#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+
+#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
+#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
+#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
+#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
+#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
+#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
+#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA bit masks and bit positions */
+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
+
+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
+
+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+
+/* TWI_MASTER.CTRLB bit masks and bit positions */
+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
+
+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
+
+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_MASTER.CTRLC bit masks and bit positions */
+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
+#define TWI_MASTER_CMD_gp 0 /* Command group position. */
+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_MASTER.STATUS bit masks and bit positions */
+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+
+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
+
+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
+
+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+
+/* TWI_SLAVE.CTRLA bit masks and bit positions */
+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
+
+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
+
+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
+
+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_SLAVE.CTRLB bit masks and bit positions */
+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_SLAVE.STATUS bit masks and bit positions */
+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+
+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
+
+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
+
+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
+
+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+
+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
+
+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+
+/* TWI.CTRL bit masks and bit positions */
+#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+
+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+
+/* PORT - Port Configuration */
+/* PORTCFG.VPCTRLA bit masks and bit positions */
+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
+
+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+
+/* PORTCFG.VPCTRLB bit masks and bit positions */
+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
+
+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+
+/* PORTCFG.CLKEVOUT bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
+
+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
+
+
+/* VPORT.INTFLAGS bit masks and bit positions */
+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.INTCTRL bit masks and bit positions */
+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
+
+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+
+/* PORT.INTFLAGS bit masks and bit positions */
+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.PIN0CTRL bit masks and bit positions */
+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
+
+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
+
+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
+
+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+
+/* PORT.PIN1CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN2CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN3CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN4CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN5CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN6CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN7CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA bit masks and bit positions */
+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC0.CTRLB bit masks and bit positions */
+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+
+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
+
+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC0.CTRLC bit masks and bit positions */
+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+
+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
+
+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC0.CTRLD bit masks and bit positions */
+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC0_EVACT_gp 5 /* Event Action group position. */
+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC0.CTRLE bit masks and bit positions */
+#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC0.INTCTRLA bit masks and bit positions */
+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC0.INTCTRLB bit masks and bit positions */
+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
+
+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
+
+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC0.CTRLFCLR bit masks and bit positions */
+#define TC0_CMD_gm 0x0C /* Command group mask. */
+#define TC0_CMD_gp 2 /* Command group position. */
+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC0_CMD0_bp 2 /* Command bit 0 position. */
+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC0_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC0_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC0_DIR_bm 0x01 /* Direction bit mask. */
+#define TC0_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC0.CTRLFSET bit masks and bit positions */
+/* TC0_CMD_gm Predefined. */
+/* TC0_CMD_gp Predefined. */
+/* TC0_CMD0_bm Predefined. */
+/* TC0_CMD0_bp Predefined. */
+/* TC0_CMD1_bm Predefined. */
+/* TC0_CMD1_bp Predefined. */
+
+/* TC0_LUPD_bm Predefined. */
+/* TC0_LUPD_bp Predefined. */
+
+/* TC0_DIR_bm Predefined. */
+/* TC0_DIR_bp Predefined. */
+
+
+/* TC0.CTRLGCLR bit masks and bit positions */
+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
+
+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
+
+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC0.CTRLGSET bit masks and bit positions */
+/* TC0_CCDBV_bm Predefined. */
+/* TC0_CCDBV_bp Predefined. */
+
+/* TC0_CCCBV_bm Predefined. */
+/* TC0_CCCBV_bp Predefined. */
+
+/* TC0_CCBBV_bm Predefined. */
+/* TC0_CCBBV_bp Predefined. */
+
+/* TC0_CCABV_bm Predefined. */
+/* TC0_CCABV_bp Predefined. */
+
+/* TC0_PERBV_bm Predefined. */
+/* TC0_PERBV_bp Predefined. */
+
+
+/* TC0.INTFLAGS bit masks and bit positions */
+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
+
+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
+
+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* TC1.CTRLA bit masks and bit positions */
+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC1.CTRLB bit masks and bit positions */
+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC1.CTRLC bit masks and bit positions */
+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC1.CTRLD bit masks and bit positions */
+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC1_EVACT_gp 5 /* Event Action group position. */
+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC1.CTRLE bit masks and bit positions */
+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC1.INTCTRLA bit masks and bit positions */
+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC1.INTCTRLB bit masks and bit positions */
+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC1.CTRLFCLR bit masks and bit positions */
+#define TC1_CMD_gm 0x0C /* Command group mask. */
+#define TC1_CMD_gp 2 /* Command group position. */
+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC1_CMD0_bp 2 /* Command bit 0 position. */
+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC1_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC1_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC1_DIR_bm 0x01 /* Direction bit mask. */
+#define TC1_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC1.CTRLFSET bit masks and bit positions */
+/* TC1_CMD_gm Predefined. */
+/* TC1_CMD_gp Predefined. */
+/* TC1_CMD0_bm Predefined. */
+/* TC1_CMD0_bp Predefined. */
+/* TC1_CMD1_bm Predefined. */
+/* TC1_CMD1_bp Predefined. */
+
+/* TC1_LUPD_bm Predefined. */
+/* TC1_LUPD_bp Predefined. */
+
+/* TC1_DIR_bm Predefined. */
+/* TC1_DIR_bp Predefined. */
+
+
+/* TC1.CTRLGCLR bit masks and bit positions */
+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC1.CTRLGSET bit masks and bit positions */
+/* TC1_CCBBV_bm Predefined. */
+/* TC1_CCBBV_bp Predefined. */
+
+/* TC1_CCABV_bm Predefined. */
+/* TC1_CCABV_bp Predefined. */
+
+/* TC1_PERBV_bm Predefined. */
+/* TC1_PERBV_bp Predefined. */
+
+
+/* TC1.INTFLAGS bit masks and bit positions */
+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* AWEX.CTRL bit masks and bit positions */
+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
+
+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
+
+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
+
+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
+
+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
+
+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+
+/* AWEX.FDCTRL bit masks and bit positions */
+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+
+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
+
+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+
+/* AWEX.STATUS bit masks and bit positions */
+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+
+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
+
+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
+
+/* HIRES.CTRLA bit masks and bit positions */
+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS bit masks and bit positions */
+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
+
+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
+
+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
+
+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
+#define USART_FERR_bp 4 /* Frame Error bit position. */
+
+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
+
+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
+#define USART_PERR_bp 2 /* Parity Error bit position. */
+
+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+
+/* USART.CTRLA bit masks and bit positions */
+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
+
+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
+
+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+
+/* USART.CTRLB bit masks and bit positions */
+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+
+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
+
+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
+
+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
+
+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+
+/* USART.CTRLC bit masks and bit positions */
+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+#define USART_CMODE_gp 6 /* Communication Mode group position. */
+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
+
+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
+#define USART_PMODE_gp 4 /* Parity Mode group position. */
+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
+
+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
+
+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
+#define USART_CHSIZE_gp 0 /* Character Size group position. */
+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+
+/* USART.BAUDCTRLA bit masks and bit positions */
+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+
+/* USART.BAUDCTRLB bit masks and bit positions */
+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+/* USART_BSEL_gm Predefined. */
+/* USART_BSEL_gp Predefined. */
+/* USART_BSEL0_bm Predefined. */
+/* USART_BSEL0_bp Predefined. */
+/* USART_BSEL1_bm Predefined. */
+/* USART_BSEL1_bp Predefined. */
+/* USART_BSEL2_bm Predefined. */
+/* USART_BSEL2_bp Predefined. */
+/* USART_BSEL3_bm Predefined. */
+/* USART_BSEL3_bp Predefined. */
+
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL bit masks and bit positions */
+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
+
+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
+
+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
+
+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
+
+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
+#define SPI_MODE_gp 2 /* SPI Mode group position. */
+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
+
+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+
+/* SPI.INTCTRL bit masks and bit positions */
+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+
+/* SPI.STATUS bit masks and bit positions */
+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+
+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL bit masks and bit positions */
+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_XOSCF_vect_num 1
+#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num 2
+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
+#define PORTC_INT1_vect_num 3
+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num 4
+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
+#define PORTR_INT1_vect_num 5
+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num 10
+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
+#define RTC_COMP_vect_num 11
+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num 12
+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num 13
+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num 14
+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
+#define TCC0_ERR_vect_num 15
+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
+#define TCC0_CCA_vect_num 16
+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
+#define TCC0_CCB_vect_num 17
+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
+#define TCC0_CCC_vect_num 18
+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
+#define TCC0_CCD_vect_num 19
+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num 20
+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+#define TCC1_ERR_vect_num 21
+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
+#define TCC1_CCA_vect_num 22
+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num 23
+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num 24
+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num 25
+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num 26
+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num 27
+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num 32
+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
+#define NVM_SPM_vect_num 33
+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num 34
+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
+#define PORTB_INT1_vect_num 35
+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num 43
+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
+#define PORTE_INT1_vect_num 44
+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num 47
+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
+#define TCE0_ERR_vect_num 48
+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
+#define TCE0_CCA_vect_num 49
+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
+#define TCE0_CCB_vect_num 50
+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
+#define TCE0_CCC_vect_num 51
+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
+#define TCE0_CCD_vect_num 52
+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num 58
+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num 59
+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num 60
+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num 64
+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
+#define PORTD_INT1_vect_num 65
+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num 66
+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
+#define PORTA_INT1_vect_num 67
+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num 68
+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
+#define ACA_AC1_vect_num 69
+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
+#define ACA_ACW_vect_num 70
+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num 71
+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num 77
+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
+#define TCD0_ERR_vect_num 78
+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
+#define TCD0_CCA_vect_num 79
+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
+#define TCD0_CCB_vect_num 80
+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
+#define TCD0_CCC_vect_num 81
+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
+#define TCD0_CCD_vect_num 82
+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num 87
+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num 88
+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num 89
+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num 90
+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num 104
+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
+#define PORTF_INT1_vect_num 105
+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num 108
+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
+#define TCF0_ERR_vect_num 109
+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
+#define TCF0_CCA_vect_num 110
+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
+#define TCF0_CCB_vect_num 111
+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
+#define TCF0_CCC_vect_num 112
+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
+#define TCF0_CCD_vect_num 113
+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#define PROGMEM_START (0x0000)
+#define PROGMEM_SIZE (270336)
+#define PROGMEM_PAGE_SIZE (512)
+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#define APP_SECTION_START (0x0000)
+#define APP_SECTION_SIZE (262144)
+#define APP_SECTION_PAGE_SIZE (512)
+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#define APPTABLE_SECTION_START (0x3E000)
+#define APPTABLE_SECTION_SIZE (8192)
+#define APPTABLE_SECTION_PAGE_SIZE (512)
+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#define BOOT_SECTION_START (0x40000)
+#define BOOT_SECTION_SIZE (8192)
+#define BOOT_SECTION_PAGE_SIZE (512)
+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#define DATAMEM_START (0x0000)
+#define DATAMEM_SIZE (24576)
+#define DATAMEM_PAGE_SIZE (0)
+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#define IO_START (0x0000)
+#define IO_SIZE (4096)
+#define IO_PAGE_SIZE (0)
+#define IO_END (IO_START + IO_SIZE - 1)
+
+#define MAPPED_EEPROM_START (0x1000)
+#define MAPPED_EEPROM_SIZE (4096)
+#define MAPPED_EEPROM_PAGE_SIZE (0)
+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#define INTERNAL_SRAM_START (0x2000)
+#define INTERNAL_SRAM_SIZE (16384)
+#define INTERNAL_SRAM_PAGE_SIZE (0)
+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#define EEPROM_START (0x0000)
+#define EEPROM_SIZE (4096)
+#define EEPROM_PAGE_SIZE (32)
+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+#define FUSE_START (0x0000)
+#define FUSE_SIZE (6)
+#define FUSE_PAGE_SIZE (0)
+#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+
+#define LOCKBIT_START (0x0000)
+#define LOCKBIT_SIZE (1)
+#define LOCKBIT_PAGE_SIZE (0)
+#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
+
+#define SIGNATURES_START (0x0000)
+#define SIGNATURES_SIZE (3)
+#define SIGNATURES_PAGE_SIZE (0)
+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#define USER_SIGNATURES_START (0x0000)
+#define USER_SIGNATURES_SIZE (512)
+#define USER_SIGNATURES_PAGE_SIZE (0)
+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#define PROD_SIGNATURES_START (0x0000)
+#define PROD_SIGNATURES_SIZE (52)
+#define PROD_SIGNATURES_PAGE_SIZE (0)
+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHEND PROGMEM_END
+#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
+#define RAMSTART INTERNAL_SRAM_START
+#define RAMSIZE INTERNAL_SRAM_SIZE
+#define RAMEND INTERNAL_SRAM_END
+#define XRAMSTART EXTERNAL_SRAM_START
+#define XRAMSIZE EXTERNAL_SRAM_SIZE
+#define XRAMEND INTERNAL_SRAM_END
+#define E2END EEPROM_END
+#define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
+#define FUSE0_DEFAULT (0xFF)
+
+/* Fuse Byte 1 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT (0xFF)
+
+/* Fuse Byte 2 */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
+#define FUSE2_DEFAULT (0xFF)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
+#define FUSE4_DEFAULT (0xFF)
+
+/* Fuse Byte 5 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT (0xFF)
+
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x98
+#define SIGNATURE_2 0x44
+
+
+#endif /* _AVR_ATxmega256D3_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/iox32a4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox32a4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox32a4.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox32a4.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox32a4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega32A4_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6252,21 +6252,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -6582,49 +6582,49 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_USERID0 ~_BV(0) /* User ID Bit 0 */
-#define FUSE_USERID1 ~_BV(1) /* User ID Bit 1 */
-#define FUSE_USERID2 ~_BV(2) /* User ID Bit 2 */
-#define FUSE_USERID3 ~_BV(3) /* User ID Bit 3 */
-#define FUSE_USERID4 ~_BV(4) /* User ID Bit 4 */
-#define FUSE_USERID5 ~_BV(5) /* User ID Bit 5 */
-#define FUSE_USERID6 ~_BV(6) /* User ID Bit 6 */
-#define FUSE_USERID7 ~_BV(7) /* User ID Bit 7 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iox32d4.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox32d4.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox32d4.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox32d4.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox32d4.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega32D4_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -689,7 +689,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -5222,21 +5222,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -5482,49 +5482,49 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_USERID0 ~_BV(0) /* User ID Bit 0 */
-#define FUSE_USERID1 ~_BV(1) /* User ID Bit 1 */
-#define FUSE_USERID2 ~_BV(2) /* User ID Bit 2 */
-#define FUSE_USERID3 ~_BV(3) /* User ID Bit 3 */
-#define FUSE_USERID4 ~_BV(4) /* User ID Bit 4 */
-#define FUSE_USERID5 ~_BV(5) /* User ID Bit 5 */
-#define FUSE_USERID6 ~_BV(6) /* User ID Bit 6 */
-#define FUSE_USERID7 ~_BV(7) /* User ID Bit 7 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iox64a1.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox64a1.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox64a1.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox64a1.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox64a1.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega64A1_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6625,21 +6625,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -7076,50 +7076,50 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0 ~_BV(0) /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1 ~_BV(1) /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2 ~_BV(2) /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3 ~_BV(3) /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4 ~_BV(4) /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5 ~_BV(5) /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6 ~_BV(6) /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7 ~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BODACT0 ~_BV(2) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(3) /* BOD Operation in Active Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_JTAGEN ~_BV(0) /* JTAG Interface Enable */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
#define FUSE5_DEFAULT (0xFF)
diff -u rtems/cpukit/score/cpu/avr/avr/iox64a3.h:1.2 rtems/cpukit/score/cpu/avr/avr/iox64a3.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/iox64a3.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/iox64a3.h Mon May 10 11:31:23 2010
@@ -42,7 +42,7 @@
# define _AVR_IOXXX_H_ "iox64a3.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
+#endif
#ifndef _AVR_ATxmega64A3_H_
@@ -92,7 +92,7 @@
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register16_t regname; \
struct \
@@ -106,7 +106,7 @@
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
- union \
+ __extension__ union \
{ \
register32_t regname; \
struct \
@@ -926,7 +926,7 @@
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
- register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
@@ -6438,21 +6438,21 @@
// Generic Port Pins
-#define PIN0_bm 0x01
+#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
-#define PIN2_bm 0x04
+#define PIN2_bm 0x04
#define PIN2_bp 2
-#define PIN3_bm 0x08
+#define PIN3_bm 0x08
#define PIN3_bp 3
-#define PIN4_bm 0x10
+#define PIN4_bm 0x10
#define PIN4_bp 4
-#define PIN5_bm 0x20
+#define PIN5_bm 0x20
#define PIN5_bp 5
-#define PIN6_bm 0x40
+#define PIN6_bm 0x40
#define PIN6_bp 6
-#define PIN7_bm 0x80
+#define PIN7_bm 0x80
#define PIN7_bp 7
@@ -6826,50 +6826,50 @@
#define FUSE_MEMORY_SIZE 6
/* Fuse Byte 0 */
-#define FUSE_JTAGUSERID0 ~_BV(0) /* JTAG User ID Bit 0 */
-#define FUSE_JTAGUSERID1 ~_BV(1) /* JTAG User ID Bit 1 */
-#define FUSE_JTAGUSERID2 ~_BV(2) /* JTAG User ID Bit 2 */
-#define FUSE_JTAGUSERID3 ~_BV(3) /* JTAG User ID Bit 3 */
-#define FUSE_JTAGUSERID4 ~_BV(4) /* JTAG User ID Bit 4 */
-#define FUSE_JTAGUSERID5 ~_BV(5) /* JTAG User ID Bit 5 */
-#define FUSE_JTAGUSERID6 ~_BV(6) /* JTAG User ID Bit 6 */
-#define FUSE_JTAGUSERID7 ~_BV(7) /* JTAG User ID Bit 7 */
+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)
/* Fuse Byte 1 */
-#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
-#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
-#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
-#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)
/* Fuse Byte 2 */
-#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
-#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)
/* Fuse Byte 3 Reserved */
/* Fuse Byte 4 */
-#define FUSE_JTAGEN ~_BV(0) /* JTAG Interface Enable */
-#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
-#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
-#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)
/* Fuse Byte 5 */
-#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
-#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
#define FUSE5_DEFAULT (0xFF)
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/iox64d3.h:1.1
--- /dev/null Mon May 10 12:11:03 2010
+++ rtems/cpukit/score/cpu/avr/avr/iox64d3.h Mon May 10 11:31:23 2010
@@ -0,0 +1,5660 @@
+/* Copyright (c) 2009 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iox64d3.h - definitions for ATxmega64D3 */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iox64d3.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATxmega64D3_H_
+#define _AVR_ATxmega64D3_H_ 1
+
+
+/* Ungrouped common registers */
+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+#define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register16_t regname; \
+ struct \
+ { \
+ register8_t regname ## L; \
+ register8_t regname ## H; \
+ }; \
+ }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register32_t regname; \
+ struct \
+ { \
+ register8_t regname ## 0; \
+ register8_t regname ## 1; \
+ register8_t regname ## 2; \
+ register8_t regname ## 3; \
+ }; \
+ }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+ register8_t OCDR0; /* OCD Register 0 */
+ register8_t OCDR1; /* OCD Register 1 */
+} OCD_t;
+
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
+} CCP_t;
+
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t PSCTRL; /* Prescaler Control Register */
+ register8_t LOCK; /* Lock register */
+ register8_t RTCCTRL; /* RTC Control Register */
+} CLK_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+ register8_t PRGEN; /* General Power Reduction */
+ register8_t PRPA; /* Power Reduction Port A */
+ register8_t PRPB; /* Power Reduction Port B */
+ register8_t PRPC; /* Power Reduction Port C */
+ register8_t PRPD; /* Power Reduction Port D */
+ register8_t PRPE; /* Power Reduction Port E */
+ register8_t PRPF; /* Power Reduction Port F */
+} PR_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
+} CLK_RTCSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+ register8_t CTRL; /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
+ register8_t PLLCTRL; /* PLL Control REgister */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+} OSC_PLLSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t CALA; /* Calibration Register A */
+ register8_t CALB; /* Calibration Register B */
+ register8_t COMP0; /* Oscillator Compare Register 0 */
+ register8_t COMP1; /* Oscillator Compare Register 1 */
+ register8_t COMP2; /* Oscillator Compare Register 2 */
+ register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t CTRL; /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t WINCTRL; /* Windowed Mode Control */
+ register8_t STATUS; /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+ register8_t DEVID0; /* Device ID byte 0 */
+ register8_t DEVID1; /* Device ID byte 1 */
+ register8_t DEVID2; /* Device ID byte 2 */
+ register8_t REVID; /* Revision ID */
+ register8_t JTAGUID; /* JTAG User ID */
+ register8_t reserved_0x05;
+ register8_t MCUCR; /* MCU Control */
+ register8_t reserved_0x07;
+ register8_t EVSYSLOCK; /* Event System Lock */
+ register8_t AWEXLOCK; /* AWEX Lock */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t INTPRI; /* Interrupt Priority */
+ register8_t CTRL; /* Control Register */
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
+ register8_t CH0CTRL; /* Channel 0 Control Register */
+ register8_t CH1CTRL; /* Channel 1 Control Register */
+ register8_t CH2CTRL; /* Channel 2 Control Register */
+ register8_t CH3CTRL; /* Channel 3 Control Register */
+ register8_t STROBE; /* Event Strobe */
+ register8_t DATA; /* Event Data */
+} EVSYS_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
+} EVSYS_CHMUX_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+ register8_t ADDR0; /* Address Register 0 */
+ register8_t ADDR1; /* Address Register 1 */
+ register8_t ADDR2; /* Address Register 2 */
+ register8_t reserved_0x03;
+ register8_t DATA0; /* Data Register 0 */
+ register8_t DATA1; /* Data Register 1 */
+ register8_t DATA2; /* Data Register 2 */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t CMD; /* Command */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t INTCTRL; /* Interrupt Control */
+ register8_t reserved_0x0E;
+ register8_t STATUS; /* Status */
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Lock Bits */
+typedef struct NVM_LOCKBITS_struct
+{
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_LOCKBITS_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Fuses */
+typedef struct NVM_FUSES_struct
+{
+ register8_t FUSEBYTE0; /* User ID */
+ register8_t FUSEBYTE1; /* Watchdog Configuration */
+ register8_t FUSEBYTE2; /* Reset Configuration */
+ register8_t reserved_0x03;
+ register8_t FUSEBYTE4; /* Start-up Configuration */
+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */
+} NVM_FUSES_t;
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Production Signatures */
+typedef struct NVM_PROD_SIGNATURES_struct
+{
+ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
+ register8_t reserved_0x01;
+ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
+ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
+ register8_t reserved_0x04;
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t WAFNUM; /* Wafer Number */
+ register8_t reserved_0x11;
+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
+ register8_t reserved_0x26;
+ register8_t reserved_0x27;
+ register8_t reserved_0x28;
+ register8_t reserved_0x29;
+ register8_t reserved_0x2A;
+ register8_t reserved_0x2B;
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
+ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
+ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
+ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
+ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ register8_t reserved_0x36;
+ register8_t reserved_0x37;
+ register8_t reserved_0x38;
+ register8_t reserved_0x39;
+ register8_t reserved_0x3A;
+ register8_t reserved_0x3B;
+ register8_t reserved_0x3C;
+ register8_t reserved_0x3D;
+ register8_t reserved_0x3E;
+} NVM_PROD_SIGNATURES_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
+} NVM_CMD_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
+} NVM_SPMLVL_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
+} NVM_EELVL_t;
+
+/* Boot lock bits - boot setcion */
+typedef enum NVM_BLBB_enum
+{
+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
+} NVM_BLBB_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
+} NVM_BLBAT_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
+} NVM_LB_t;
+
+/* Boot Loader Section Reset Vector */
+typedef enum BOOTRST_enum
+{
+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
+} BOOTRST_t;
+
+/* BOD operation */
+typedef enum BOD_enum
+{
+ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
+ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
+} BOD_t;
+
+/* Watchdog (Window) Timeout Period */
+typedef enum WD_enum
+{
+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
+} WD_t;
+
+/* Start-up Time */
+typedef enum SUT_enum
+{
+ SUT_0MS_gc = (0x03<<2), /* 0 ms */
+ SUT_4MS_gc = (0x01<<2), /* 4 ms */
+ SUT_64MS_gc = (0x00<<2), /* 64 ms */
+} SUT_t;
+
+/* Brown Out Detection Voltage Level */
+typedef enum BODLVL_enum
+{
+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
+ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */
+ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */
+ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */
+ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */
+ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */
+ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */
+} BODLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+ register8_t AC0CTRL; /* Comparator 0 Control */
+ register8_t AC1CTRL; /* Comparator 1 Control */
+ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
+ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t WINCTRL; /* Window Mode Control */
+ register8_t STATUS; /* Status */
+} AC_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
+} AC_INTLVL_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
+} AC_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
+} AC_WINTLVL_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
+} AC_WSTATE_t;
+
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+ register8_t INTCTRL; /* Channel Interrupt Control */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+ register8_t reserved_0x6;
+ register8_t reserved_0x7;
+} ADC_CH_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t REFCTRL; /* Reference Control */
+ register8_t EVCTRL; /* Event Control */
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t CALCTRL; /* Calibration Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ _WORDREGISTER(CAL); /* Calibration Value */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ _WORDREGISTER(CH0RES); /* Channel 0 Result */
+ _WORDREGISTER(CMP); /* Compare Value */
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ ADC_CH_t CH0; /* ADC Channel 0 */
+} ADC_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
+} ADC_CH_MUXPOS_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
+ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
+ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
+ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
+ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
+} ADC_CH_MUXNEG_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+} ADC_CH_GAIN_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
+ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
+} ADC_REFSEL_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
+} ADC_SWEEP_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
+} ADC_EVACT_t;
+
+/* Interupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
+} ADC_CH_INTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
+} ADC_CH_INTLVL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Clounter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ _WORDREGISTER(CNT); /* Count Register */
+ _WORDREGISTER(PER); /* Period Register */
+ _WORDREGISTER(COMP); /* Compare Register */
+} RTC_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} RTC_OVFINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+ register8_t CTRLA; /* Chip Select Control Register A */
+ register8_t CTRLB; /* Chip Select Control Register B */
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+} EBI_CS_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t SDRAMCTRLA; /* SDRAM Control Register A */
+ register8_t reserved_0x02;
+ register8_t reserved_0x03;
+ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
+ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
+ register8_t SDRAMCTRLB; /* SDRAM Control Register B */
+ register8_t SDRAMCTRLC; /* SDRAM Control Register C */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ EBI_CS_t CS0; /* Chip Select 0 */
+ EBI_CS_t CS1; /* Chip Select 1 */
+ EBI_CS_t CS2; /* Chip Select 2 */
+ EBI_CS_t CS3; /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select adress space */
+typedef enum EBI_CS_ASPACE_enum
+{
+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* */
+typedef enum EBI_CS_SRWS_enum
+{
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
+ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
+ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
+ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
+ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* */
+typedef enum EBI_SDDATAW_enum
+{
+ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
+ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/* */
+typedef enum EBI_LPCMODE_enum
+{
+ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
+ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* */
+typedef enum EBI_SRMODE_enum
+{
+ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
+ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
+ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
+ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* */
+typedef enum EBI_IFMODE_enum
+{
+ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
+ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
+ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
+ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
+} EBI_IFMODE_t;
+
+/* */
+typedef enum EBI_SDCOL_enum
+{
+ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
+ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
+ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+} EBI_SDCOL_t;
+
+/* */
+typedef enum EBI_MRDLY_enum
+{
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* */
+typedef enum EBI_ROWCYCDLY_enum
+{
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* */
+typedef enum EBI_RPDLY_enum
+{
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_RPDLY_t;
+
+/* */
+typedef enum EBI_WRDLY_enum
+{
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_WRDLY_t;
+
+/* */
+typedef enum EBI_ESRDLY_enum
+{
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/* */
+typedef enum EBI_ROWCOLDLY_enum
+{
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_MASTER_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t STATUS; /* Status Register */
+ register8_t BAUD; /* Baurd Rate Control Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+} TWI_MASTER_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_SLAVE_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+ register8_t ADDRMASK; /* Address Mask Register */
+} TWI_SLAVE_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+ register8_t CTRL; /* TWI Common Control Register */
+ TWI_MASTER_t MASTER; /* TWI master module */
+ TWI_SLAVE_t SLAVE; /* TWI slave module */
+} TWI_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+ register8_t MPCMASK; /* Multi-pin Configuration Mask */
+ register8_t reserved_0x01;
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
+} PORTCFG_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t OUT; /* I/O Port Output */
+ register8_t IN; /* I/O Port Input */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+} VPORT_t;
+
+/*
+--------------------------------------------------------------------------
+PORT - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t DIRSET; /* I/O Port Data Direction Set */
+ register8_t DIRCLR; /* I/O Port Data Direction Clear */
+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
+ register8_t OUT; /* I/O Port Output */
+ register8_t OUTSET; /* I/O Port Output Set */
+ register8_t OUTCLR; /* I/O Port Output Clear */
+ register8_t OUTTGL; /* I/O Port Output Toggle */
+ register8_t IN; /* I/O port Input */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INT0MASK; /* Port Interrupt 0 Mask */
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+ register8_t PIN2CTRL; /* Pin 2 Control Register */
+ register8_t PIN3CTRL; /* Pin 3 Control Register */
+ register8_t PIN4CTRL; /* Pin 4 Control Register */
+ register8_t PIN5CTRL; /* Pin 5 Control Register */
+ register8_t PIN6CTRL; /* Pin 6 Control Register */
+ register8_t PIN7CTRL; /* Pin 7 Control Register */
+} PORT_t;
+
+/* Virtual Port 0 Mapping */
+typedef enum PORTCFG_VP0MAP_enum
+{
+ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP0MAP_t;
+
+/* Virtual Port 1 Mapping */
+typedef enum PORTCFG_VP1MAP_enum
+{
+ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP1MAP_t;
+
+/* Virtual Port 2 Mapping */
+typedef enum PORTCFG_VP2MAP_enum
+{
+ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP2MAP_t;
+
+/* Virtual Port 3 Mapping */
+typedef enum PORTCFG_VP3MAP_enum
+{
+ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP3MAP_t;
+
+/* Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
+} PORTCFG_CLKOUT_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
+} PORTCFG_EVOUT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
+} PORT_INT1LVL_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ _WORDREGISTER(CCC); /* Compare or Capture C */
+ _WORDREGISTER(CCD); /* Compare or Capture D */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+} TC0_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x05;
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+ register8_t DTHS; /* Dead Time High Side */
+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
+ register8_t DTHSBUF; /* Dead Time High Side Buffer */
+ register8_t OUTOVEN; /* Output Override Enable */
+} AWEX_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+ register8_t CTRLA; /* Control Register */
+} HIRES_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
+} TC_CMD_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
+} HIRES_HREN_t;
+
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+ register8_t DATA; /* Data Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
+} USART_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
+} USART_TXCINTLVL_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
+} USART_DREINTLVL_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
+} USART_PMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t DATA; /* Data Register */
+} SPI_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} SPI_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
+ register8_t CTRL; /* Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRDA_EVSEL_enum
+{
+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
+} IRDA_EVSEL_t;
+
+
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
+#define CLK (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
+#define PR (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST (*(RST_t *) 0x0078) /* Reset Controller */
+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
+#define GPIO_GPIORA _SFR_MEM8(0x000A)
+#define GPIO_GPIORB _SFR_MEM8(0x000B)
+#define GPIO_GPIORC _SFR_MEM8(0x000C)
+#define GPIO_GPIORD _SFR_MEM8(0x000D)
+#define GPIO_GPIORE _SFR_MEM8(0x000E)
+#define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+/* VPORT0 - Virtual Port 0 */
+#define VPORT0_DIR _SFR_MEM8(0x0010)
+#define VPORT0_OUT _SFR_MEM8(0x0011)
+#define VPORT0_IN _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+/* VPORT1 - Virtual Port 1 */
+#define VPORT1_DIR _SFR_MEM8(0x0014)
+#define VPORT1_OUT _SFR_MEM8(0x0015)
+#define VPORT1_IN _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+/* VPORT2 - Virtual Port 2 */
+#define VPORT2_DIR _SFR_MEM8(0x0018)
+#define VPORT2_OUT _SFR_MEM8(0x0019)
+#define VPORT2_IN _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+/* VPORT3 - Virtual Port 3 */
+#define VPORT3_DIR _SFR_MEM8(0x001C)
+#define VPORT3_OUT _SFR_MEM8(0x001D)
+#define VPORT3_IN _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0 _SFR_MEM8(0x002E)
+#define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+/* CPU - CPU Registers */
+#define CPU_CCP _SFR_MEM8(0x0034)
+#define CPU_RAMPD _SFR_MEM8(0x0038)
+#define CPU_RAMPX _SFR_MEM8(0x0039)
+#define CPU_RAMPY _SFR_MEM8(0x003A)
+#define CPU_RAMPZ _SFR_MEM8(0x003B)
+#define CPU_EIND _SFR_MEM8(0x003C)
+#define CPU_SPL _SFR_MEM8(0x003D)
+#define CPU_SPH _SFR_MEM8(0x003E)
+#define CPU_SREG _SFR_MEM8(0x003F)
+
+/* CLK - Clock System */
+#define CLK_CTRL _SFR_MEM8(0x0040)
+#define CLK_PSCTRL _SFR_MEM8(0x0041)
+#define CLK_LOCK _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL _SFR_MEM8(0x0043)
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+/* OSC - Oscillator Control */
+#define OSC_CTRL _SFR_MEM8(0x0050)
+#define OSC_STATUS _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
+#define OSC_RC32KCAL _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+
+/* PR - Power Reduction */
+#define PR_PRGEN _SFR_MEM8(0x0070)
+#define PR_PRPA _SFR_MEM8(0x0071)
+#define PR_PRPB _SFR_MEM8(0x0072)
+#define PR_PRPC _SFR_MEM8(0x0073)
+#define PR_PRPD _SFR_MEM8(0x0074)
+#define PR_PRPE _SFR_MEM8(0x0075)
+#define PR_PRPF _SFR_MEM8(0x0076)
+
+/* RST - Reset Controller */
+#define RST_STATUS _SFR_MEM8(0x0078)
+#define RST_CTRL _SFR_MEM8(0x0079)
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL _SFR_MEM8(0x0080)
+#define WDT_WINCTRL _SFR_MEM8(0x0081)
+#define WDT_STATUS _SFR_MEM8(0x0082)
+
+/* MCU - MCU Control */
+#define MCU_DEVID0 _SFR_MEM8(0x0090)
+#define MCU_DEVID1 _SFR_MEM8(0x0091)
+#define MCU_DEVID2 _SFR_MEM8(0x0092)
+#define MCU_REVID _SFR_MEM8(0x0093)
+#define MCU_JTAGUID _SFR_MEM8(0x0094)
+#define MCU_MCUCR _SFR_MEM8(0x0096)
+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+/* PMIC - Programmable Interrupt Controller */
+#define PMIC_STATUS _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI _SFR_MEM8(0x00A1)
+#define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+/* PORTCFG - Port Configuration */
+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
+#define EVSYS_STROBE _SFR_MEM8(0x0190)
+#define EVSYS_DATA _SFR_MEM8(0x0191)
+
+/* NVM - Non Volatile Memory Controller */
+#define NVM_ADDR0 _SFR_MEM8(0x01C0)
+#define NVM_ADDR1 _SFR_MEM8(0x01C1)
+#define NVM_ADDR2 _SFR_MEM8(0x01C2)
+#define NVM_DATA0 _SFR_MEM8(0x01C4)
+#define NVM_DATA1 _SFR_MEM8(0x01C5)
+#define NVM_DATA2 _SFR_MEM8(0x01C6)
+#define NVM_CMD _SFR_MEM8(0x01CA)
+#define NVM_CTRLA _SFR_MEM8(0x01CB)
+#define NVM_CTRLB _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL _SFR_MEM8(0x01CD)
+#define NVM_STATUS _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+/* ADCA - Analog to Digital Converter A */
+#define ADCA_CTRLA _SFR_MEM8(0x0200)
+#define ADCA_CTRLB _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER _SFR_MEM8(0x0204)
+#define ADCA_CALCTRL _SFR_MEM8(0x0205)
+#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
+#define ADCA_CAL _SFR_MEM16(0x020C)
+#define ADCA_CH0RES _SFR_MEM16(0x0210)
+#define ADCA_CMP _SFR_MEM16(0x0218)
+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES _SFR_MEM16(0x0224)
+
+/* DACB - Digital to Analog Converter B */
+
+/* ACA - Analog Comparator A */
+#define ACA_AC0CTRL _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
+#define ACA_CTRLA _SFR_MEM8(0x0384)
+#define ACA_CTRLB _SFR_MEM8(0x0385)
+#define ACA_WINCTRL _SFR_MEM8(0x0386)
+#define ACA_STATUS _SFR_MEM8(0x0387)
+
+/* ACB - Analog Comparator B */
+#define ACB_AC0CTRL _SFR_MEM8(0x0390)
+#define ACB_AC1CTRL _SFR_MEM8(0x0391)
+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
+#define ACB_CTRLA _SFR_MEM8(0x0394)
+#define ACB_CTRLB _SFR_MEM8(0x0395)
+#define ACB_WINCTRL _SFR_MEM8(0x0396)
+#define ACB_STATUS _SFR_MEM8(0x0397)
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL _SFR_MEM8(0x0400)
+#define RTC_STATUS _SFR_MEM8(0x0401)
+#define RTC_INTCTRL _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS _SFR_MEM8(0x0403)
+#define RTC_TEMP _SFR_MEM8(0x0404)
+#define RTC_CNT _SFR_MEM16(0x0408)
+#define RTC_PER _SFR_MEM16(0x040A)
+#define RTC_COMP _SFR_MEM16(0x040C)
+
+/* TWIC - Two-Wire Interface C */
+#define TWIC_CTRL _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483)
+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484)
+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485)
+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486)
+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487)
+#define TWIC_MASTER_DATA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+/* PORTA - Port A */
+#define PORTA_DIR _SFR_MEM8(0x0600)
+#define PORTA_DIRSET _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL _SFR_MEM8(0x0603)
+#define PORTA_OUT _SFR_MEM8(0x0604)
+#define PORTA_OUTSET _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL _SFR_MEM8(0x0607)
+#define PORTA_IN _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+/* PORTB - Port B */
+#define PORTB_DIR _SFR_MEM8(0x0620)
+#define PORTB_DIRSET _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL _SFR_MEM8(0x0623)
+#define PORTB_OUT _SFR_MEM8(0x0624)
+#define PORTB_OUTSET _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL _SFR_MEM8(0x0627)
+#define PORTB_IN _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+/* PORTC - Port C */
+#define PORTC_DIR _SFR_MEM8(0x0640)
+#define PORTC_DIRSET _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL _SFR_MEM8(0x0643)
+#define PORTC_OUT _SFR_MEM8(0x0644)
+#define PORTC_OUTSET _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL _SFR_MEM8(0x0647)
+#define PORTC_IN _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+/* PORTD - Port D */
+#define PORTD_DIR _SFR_MEM8(0x0660)
+#define PORTD_DIRSET _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL _SFR_MEM8(0x0663)
+#define PORTD_OUT _SFR_MEM8(0x0664)
+#define PORTD_OUTSET _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL _SFR_MEM8(0x0667)
+#define PORTD_IN _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+/* PORTE - Port E */
+#define PORTE_DIR _SFR_MEM8(0x0680)
+#define PORTE_DIRSET _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL _SFR_MEM8(0x0683)
+#define PORTE_OUT _SFR_MEM8(0x0684)
+#define PORTE_OUTSET _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL _SFR_MEM8(0x0687)
+#define PORTE_IN _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+/* PORTF - Port F */
+#define PORTF_DIR _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
+#define PORTF_OUT _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
+#define PORTF_IN _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+/* PORTR - Port R */
+#define PORTR_DIR _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
+#define PORTR_OUT _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
+#define PORTR_IN _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+/* TCC0 - Timer/Counter C0 */
+#define TCC0_CTRLA _SFR_MEM8(0x0800)
+#define TCC0_CTRLB _SFR_MEM8(0x0801)
+#define TCC0_CTRLC _SFR_MEM8(0x0802)
+#define TCC0_CTRLD _SFR_MEM8(0x0803)
+#define TCC0_CTRLE _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
+#define TCC0_TEMP _SFR_MEM8(0x080F)
+#define TCC0_CNT _SFR_MEM16(0x0820)
+#define TCC0_PER _SFR_MEM16(0x0826)
+#define TCC0_CCA _SFR_MEM16(0x0828)
+#define TCC0_CCB _SFR_MEM16(0x082A)
+#define TCC0_CCC _SFR_MEM16(0x082C)
+#define TCC0_CCD _SFR_MEM16(0x082E)
+#define TCC0_PERBUF _SFR_MEM16(0x0836)
+#define TCC0_CCABUF _SFR_MEM16(0x0838)
+#define TCC0_CCBBUF _SFR_MEM16(0x083A)
+#define TCC0_CCCBUF _SFR_MEM16(0x083C)
+#define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+/* TCC1 - Timer/Counter C1 */
+#define TCC1_CTRLA _SFR_MEM8(0x0840)
+#define TCC1_CTRLB _SFR_MEM8(0x0841)
+#define TCC1_CTRLC _SFR_MEM8(0x0842)
+#define TCC1_CTRLD _SFR_MEM8(0x0843)
+#define TCC1_CTRLE _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
+#define TCC1_TEMP _SFR_MEM8(0x084F)
+#define TCC1_CNT _SFR_MEM16(0x0860)
+#define TCC1_PER _SFR_MEM16(0x0866)
+#define TCC1_CCA _SFR_MEM16(0x0868)
+#define TCC1_CCB _SFR_MEM16(0x086A)
+#define TCC1_PERBUF _SFR_MEM16(0x0876)
+#define TCC1_CCABUF _SFR_MEM16(0x0878)
+#define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+/* AWEXC - Advanced Waveform Extension C */
+#define AWEXC_CTRL _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+#define AWEXC_STATUS _SFR_MEM8(0x0884)
+#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+#define AWEXC_DTLS _SFR_MEM8(0x0888)
+#define AWEXC_DTHS _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+/* HIRESC - High-Resolution Extension C */
+#define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0_DATA _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+/* SPIC - Serial Peripheral Interface C */
+#define SPIC_CTRL _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+#define SPIC_STATUS _SFR_MEM8(0x08C2)
+#define SPIC_DATA _SFR_MEM8(0x08C3)
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8)
+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9)
+#define IRCOM_CTRL _SFR_MEM8(0x08FA)
+
+/* TCD0 - Timer/Counter D0 */
+#define TCD0_CTRLA _SFR_MEM8(0x0900)
+#define TCD0_CTRLB _SFR_MEM8(0x0901)
+#define TCD0_CTRLC _SFR_MEM8(0x0902)
+#define TCD0_CTRLD _SFR_MEM8(0x0903)
+#define TCD0_CTRLE _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
+#define TCD0_TEMP _SFR_MEM8(0x090F)
+#define TCD0_CNT _SFR_MEM16(0x0920)
+#define TCD0_PER _SFR_MEM16(0x0926)
+#define TCD0_CCA _SFR_MEM16(0x0928)
+#define TCD0_CCB _SFR_MEM16(0x092A)
+#define TCD0_CCC _SFR_MEM16(0x092C)
+#define TCD0_CCD _SFR_MEM16(0x092E)
+#define TCD0_PERBUF _SFR_MEM16(0x0936)
+#define TCD0_CCABUF _SFR_MEM16(0x0938)
+#define TCD0_CCBBUF _SFR_MEM16(0x093A)
+#define TCD0_CCCBUF _SFR_MEM16(0x093C)
+#define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0_DATA _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+/* SPID - Serial Peripheral Interface D */
+#define SPID_CTRL _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL _SFR_MEM8(0x09C1)
+#define SPID_STATUS _SFR_MEM8(0x09C2)
+#define SPID_DATA _SFR_MEM8(0x09C3)
+
+/* TCE0 - Timer/Counter E0 */
+#define TCE0_CTRLA _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP _SFR_MEM8(0x0A0F)
+#define TCE0_CNT _SFR_MEM16(0x0A20)
+#define TCE0_PER _SFR_MEM16(0x0A26)
+#define TCE0_CCA _SFR_MEM16(0x0A28)
+#define TCE0_CCB _SFR_MEM16(0x0A2A)
+#define TCE0_CCC _SFR_MEM16(0x0A2C)
+#define TCE0_CCD _SFR_MEM16(0x0A2E)
+#define TCE0_PERBUF _SFR_MEM16(0x0A36)
+#define TCE0_CCABUF _SFR_MEM16(0x0A38)
+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+/* AWEXE - Advanced Waveform Extension E */
+#define AWEXE_CTRL _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS _SFR_MEM8(0x0A84)
+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0_DATA _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+/* SPIE - Serial Peripheral Interface E */
+#define SPIE_CTRL _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS _SFR_MEM8(0x0AC2)
+#define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+/* TCF0 - Timer/Counter F0 */
+#define TCF0_CTRLA _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP _SFR_MEM8(0x0B0F)
+#define TCF0_CNT _SFR_MEM16(0x0B20)
+#define TCF0_PER _SFR_MEM16(0x0B26)
+#define TCF0_CCA _SFR_MEM16(0x0B28)
+#define TCF0_CCB _SFR_MEM16(0x0B2A)
+#define TCF0_CCC _SFR_MEM16(0x0B2C)
+#define TCF0_CCD _SFR_MEM16(0x0B2E)
+#define TCF0_PERBUF _SFR_MEM16(0x0B36)
+#define TCF0_CCABUF _SFR_MEM16(0x0B38)
+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR1 bit masks and bit positions */
+#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+
+/* CPU - CPU */
+/* CPU.CCP bit masks and bit positions */
+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+#define CPU_CCP_gp 0 /* CCP signature group position. */
+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+
+/* CPU.SREG bit masks and bit positions */
+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+
+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
+#define CPU_T_bp 6 /* Transfer Bit bit position. */
+
+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
+#define CPU_H_bp 5 /* Half Carry Flag bit position. */
+
+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
+
+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
+
+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
+#define CPU_N_bp 2 /* Negative Flag bit position. */
+
+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
+#define CPU_Z_bp 1 /* Zero Flag bit position. */
+
+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+#define CPU_C_bp 0 /* Carry Flag bit position. */
+
+
+/* CLK - Clock System */
+/* CLK.CTRL bit masks and bit positions */
+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
+
+
+/* CLK.PSCTRL bit masks and bit positions */
+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
+
+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
+
+
+/* CLK.LOCK bit masks and bit positions */
+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
+
+
+/* CLK.RTCCTRL bit masks and bit positions */
+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
+
+#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
+#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
+
+
+/* PR.PRGEN bit masks and bit positions */
+#define PR_AES_bm 0x10 /* AES bit mask. */
+#define PR_AES_bp 4 /* AES bit position. */
+
+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
+#define PR_EBI_bp 3 /* External Bus Interface bit position. */
+
+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
+#define PR_RTC_bp 2 /* Real-time Counter bit position. */
+
+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
+#define PR_EVSYS_bp 1 /* Event System bit position. */
+
+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
+#define PR_DMA_bp 0 /* DMA-Controller bit position. */
+
+
+/* PR.PRPA bit masks and bit positions */
+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
+#define PR_DAC_bp 2 /* Port A DAC bit position. */
+
+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
+#define PR_ADC_bp 1 /* Port A ADC bit position. */
+
+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
+
+
+/* PR.PRPB bit masks and bit positions */
+/* PR_DAC_bm Predefined. */
+/* PR_DAC_bp Predefined. */
+
+/* PR_ADC_bm Predefined. */
+/* PR_ADC_bp Predefined. */
+
+/* PR_AC_bm Predefined. */
+/* PR_AC_bp Predefined. */
+
+
+/* PR.PRPC bit masks and bit positions */
+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
+
+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
+#define PR_USART1_bp 5 /* Port C USART1 bit position. */
+
+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
+#define PR_USART0_bp 4 /* Port C USART0 bit position. */
+
+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
+#define PR_SPI_bp 3 /* Port C SPI bit position. */
+
+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
+
+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
+
+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
+
+
+/* PR.PRPD bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPE bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* PR.PRPF bit masks and bit positions */
+/* PR_TWI_bm Predefined. */
+/* PR_TWI_bp Predefined. */
+
+/* PR_USART1_bm Predefined. */
+/* PR_USART1_bp Predefined. */
+
+/* PR_USART0_bm Predefined. */
+/* PR_USART0_bp Predefined. */
+
+/* PR_SPI_bm Predefined. */
+/* PR_SPI_bp Predefined. */
+
+/* PR_HIRES_bm Predefined. */
+/* PR_HIRES_bp Predefined. */
+
+/* PR_TC1_bm Predefined. */
+/* PR_TC1_bp Predefined. */
+
+/* PR_TC0_bm Predefined. */
+/* PR_TC0_bp Predefined. */
+
+
+/* SLEEP - Sleep Controller */
+/* SLEEP.CTRL bit masks and bit positions */
+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
+
+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
+
+
+/* OSC - Oscillator */
+/* OSC.CTRL bit masks and bit positions */
+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
+
+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
+
+#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
+
+#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
+
+#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
+
+
+/* OSC.STATUS bit masks and bit positions */
+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
+
+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
+
+#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
+
+#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
+
+#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
+
+
+/* OSC.XOSCCTRL bit masks and bit positions */
+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
+
+#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
+#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
+
+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
+
+
+/* OSC.XOSCFAIL bit masks and bit positions */
+#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
+
+#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
+#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
+
+
+/* OSC.PLLCTRL bit masks and bit positions */
+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
+
+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
+
+
+/* OSC.DFLLCTRL bit masks and bit positions */
+#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
+#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
+
+#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
+#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
+
+
+/* DFLL - DFLL */
+/* DFLL.CTRL bit masks and bit positions */
+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
+
+
+/* DFLL.CALA bit masks and bit positions */
+#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
+#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
+#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
+#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
+#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
+#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
+#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
+#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
+#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
+
+
+/* DFLL.CALB bit masks and bit positions */
+#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
+#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
+#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
+#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
+#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
+#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
+#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
+#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
+
+
+/* RST - Reset */
+/* RST.STATUS bit masks and bit positions */
+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
+
+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
+
+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
+
+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
+
+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
+
+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
+
+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
+
+
+/* RST.CTRL bit masks and bit positions */
+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
+#define RST_SWRST_bp 0 /* Software Reset bit position. */
+
+
+/* WDT - Watch-Dog Timer */
+/* WDT.CTRL bit masks and bit positions */
+#define WDT_PER_gm 0x3C /* Period group mask. */
+#define WDT_PER_gp 2 /* Period group position. */
+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
+#define WDT_PER0_bp 2 /* Period bit 0 position. */
+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
+#define WDT_PER1_bp 3 /* Period bit 1 position. */
+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
+#define WDT_PER2_bp 4 /* Period bit 2 position. */
+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
+#define WDT_PER3_bp 5 /* Period bit 3 position. */
+
+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
+#define WDT_ENABLE_bp 1 /* Enable bit position. */
+
+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
+#define WDT_CEN_bp 0 /* Change Enable bit position. */
+
+
+/* WDT.WINCTRL bit masks and bit positions */
+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
+
+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
+
+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
+
+
+/* WDT.STATUS bit masks and bit positions */
+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
+
+
+/* MCU - MCU Control */
+/* MCU.MCUCR bit masks and bit positions */
+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
+
+
+/* MCU.EVSYSLOCK bit masks and bit positions */
+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
+
+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
+
+
+/* MCU.AWEXLOCK bit masks and bit positions */
+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
+
+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
+
+
+/* PMIC - Programmable Multi-level Interrupt Controller */
+/* PMIC.STATUS bit masks and bit positions */
+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
+
+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
+
+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
+
+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
+
+
+/* PMIC.CTRL bit masks and bit positions */
+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
+
+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
+
+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
+
+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
+
+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
+
+
+/* EVSYS - Event System */
+/* EVSYS.CH0MUX bit masks and bit positions */
+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
+
+
+/* EVSYS.CH1MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH2MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH3MUX bit masks and bit positions */
+/* EVSYS_CHMUX_gm Predefined. */
+/* EVSYS_CHMUX_gp Predefined. */
+/* EVSYS_CHMUX0_bm Predefined. */
+/* EVSYS_CHMUX0_bp Predefined. */
+/* EVSYS_CHMUX1_bm Predefined. */
+/* EVSYS_CHMUX1_bp Predefined. */
+/* EVSYS_CHMUX2_bm Predefined. */
+/* EVSYS_CHMUX2_bp Predefined. */
+/* EVSYS_CHMUX3_bm Predefined. */
+/* EVSYS_CHMUX3_bp Predefined. */
+/* EVSYS_CHMUX4_bm Predefined. */
+/* EVSYS_CHMUX4_bp Predefined. */
+/* EVSYS_CHMUX5_bm Predefined. */
+/* EVSYS_CHMUX5_bp Predefined. */
+/* EVSYS_CHMUX6_bm Predefined. */
+/* EVSYS_CHMUX6_bp Predefined. */
+/* EVSYS_CHMUX7_bm Predefined. */
+/* EVSYS_CHMUX7_bp Predefined. */
+
+
+/* EVSYS.CH0CTRL bit masks and bit positions */
+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+
+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
+
+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
+
+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
+
+
+/* EVSYS.CH1CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH2CTRL bit masks and bit positions */
+/* EVSYS_QDIRM_gm Predefined. */
+/* EVSYS_QDIRM_gp Predefined. */
+/* EVSYS_QDIRM0_bm Predefined. */
+/* EVSYS_QDIRM0_bp Predefined. */
+/* EVSYS_QDIRM1_bm Predefined. */
+/* EVSYS_QDIRM1_bp Predefined. */
+
+/* EVSYS_QDIEN_bm Predefined. */
+/* EVSYS_QDIEN_bp Predefined. */
+
+/* EVSYS_QDEN_bm Predefined. */
+/* EVSYS_QDEN_bp Predefined. */
+
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* EVSYS.CH3CTRL bit masks and bit positions */
+/* EVSYS_DIGFILT_gm Predefined. */
+/* EVSYS_DIGFILT_gp Predefined. */
+/* EVSYS_DIGFILT0_bm Predefined. */
+/* EVSYS_DIGFILT0_bp Predefined. */
+/* EVSYS_DIGFILT1_bm Predefined. */
+/* EVSYS_DIGFILT1_bp Predefined. */
+/* EVSYS_DIGFILT2_bm Predefined. */
+/* EVSYS_DIGFILT2_bp Predefined. */
+
+
+/* NVM - Non Volatile Memory Controller */
+/* NVM.CMD bit masks and bit positions */
+#define NVM_CMD_gm 0xFF /* Command group mask. */
+#define NVM_CMD_gp 0 /* Command group position. */
+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define NVM_CMD0_bp 0 /* Command bit 0 position. */
+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define NVM_CMD1_bp 1 /* Command bit 1 position. */
+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
+#define NVM_CMD2_bp 2 /* Command bit 2 position. */
+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
+#define NVM_CMD3_bp 3 /* Command bit 3 position. */
+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
+#define NVM_CMD4_bp 4 /* Command bit 4 position. */
+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
+#define NVM_CMD5_bp 5 /* Command bit 5 position. */
+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
+#define NVM_CMD6_bp 6 /* Command bit 6 position. */
+#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
+#define NVM_CMD7_bp 7 /* Command bit 7 position. */
+
+
+/* NVM.CTRLA bit masks and bit positions */
+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
+
+
+/* NVM.CTRLB bit masks and bit positions */
+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
+
+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
+
+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
+
+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
+
+
+/* NVM.INTCTRL bit masks and bit positions */
+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
+
+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
+
+
+/* NVM.STATUS bit masks and bit positions */
+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
+
+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
+
+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
+
+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
+
+
+/* NVM.LOCKBITS bit masks and bit positions */
+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
+
+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
+
+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
+#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
+#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
+#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
+#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
+#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
+#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
+#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
+#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
+#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
+#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
+#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
+#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
+#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
+#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
+#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
+#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
+#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
+#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
+
+
+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
+
+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
+
+
+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
+#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
+#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
+
+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
+
+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
+
+
+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
+
+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
+
+
+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
+
+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
+
+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
+
+
+/* AC - Analog Comparator */
+/* AC.AC0CTRL bit masks and bit positions */
+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
+
+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
+
+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
+
+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
+
+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
+#define AC_ENABLE_bp 0 /* Enable bit position. */
+
+
+/* AC.AC1CTRL bit masks and bit positions */
+/* AC_INTMODE_gm Predefined. */
+/* AC_INTMODE_gp Predefined. */
+/* AC_INTMODE0_bm Predefined. */
+/* AC_INTMODE0_bp Predefined. */
+/* AC_INTMODE1_bm Predefined. */
+/* AC_INTMODE1_bp Predefined. */
+
+/* AC_INTLVL_gm Predefined. */
+/* AC_INTLVL_gp Predefined. */
+/* AC_INTLVL0_bm Predefined. */
+/* AC_INTLVL0_bp Predefined. */
+/* AC_INTLVL1_bm Predefined. */
+/* AC_INTLVL1_bp Predefined. */
+
+/* AC_HSMODE_bm Predefined. */
+/* AC_HSMODE_bp Predefined. */
+
+/* AC_HYSMODE_gm Predefined. */
+/* AC_HYSMODE_gp Predefined. */
+/* AC_HYSMODE0_bm Predefined. */
+/* AC_HYSMODE0_bp Predefined. */
+/* AC_HYSMODE1_bm Predefined. */
+/* AC_HYSMODE1_bp Predefined. */
+
+/* AC_ENABLE_bm Predefined. */
+/* AC_ENABLE_bp Predefined. */
+
+
+/* AC.AC0MUXCTRL bit masks and bit positions */
+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
+
+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
+
+
+/* AC.AC1MUXCTRL bit masks and bit positions */
+/* AC_MUXPOS_gm Predefined. */
+/* AC_MUXPOS_gp Predefined. */
+/* AC_MUXPOS0_bm Predefined. */
+/* AC_MUXPOS0_bp Predefined. */
+/* AC_MUXPOS1_bm Predefined. */
+/* AC_MUXPOS1_bp Predefined. */
+/* AC_MUXPOS2_bm Predefined. */
+/* AC_MUXPOS2_bp Predefined. */
+
+/* AC_MUXNEG_gm Predefined. */
+/* AC_MUXNEG_gp Predefined. */
+/* AC_MUXNEG0_bm Predefined. */
+/* AC_MUXNEG0_bp Predefined. */
+/* AC_MUXNEG1_bm Predefined. */
+/* AC_MUXNEG1_bp Predefined. */
+/* AC_MUXNEG2_bm Predefined. */
+/* AC_MUXNEG2_bp Predefined. */
+
+
+/* AC.CTRLA bit masks and bit positions */
+#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
+#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
+
+
+/* AC.CTRLB bit masks and bit positions */
+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
+
+
+/* AC.WINCTRL bit masks and bit positions */
+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
+
+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
+
+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
+
+
+/* AC.STATUS bit masks and bit positions */
+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
+#define AC_WSTATE_gp 6 /* Window Mode State group position. */
+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
+
+#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
+#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
+
+#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
+#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
+
+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
+
+#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
+#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
+
+#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
+#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
+
+
+/* ADC - Analog/Digital Converter */
+/* ADC_CH.CTRL bit masks and bit positions */
+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
+
+#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
+#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
+#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
+#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
+#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
+#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
+#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
+#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
+
+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
+
+
+/* ADC_CH.MUXCTRL bit masks and bit positions */
+#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
+#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
+#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
+#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
+#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
+#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
+#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
+#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
+#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
+#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
+
+#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
+#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
+#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
+#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
+#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
+#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
+#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
+#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
+#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
+#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
+
+#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
+#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
+#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
+#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
+#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
+#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
+
+
+/* ADC_CH.INTCTRL bit masks and bit positions */
+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
+
+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
+
+
+/* ADC_CH.INTFLAGS bit masks and bit positions */
+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
+
+
+/* ADC.CTRLA bit masks and bit positions */
+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
+
+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
+
+
+/* ADC.CTRLB bit masks and bit positions */
+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
+
+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
+
+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
+
+
+/* ADC.REFCTRL bit masks and bit positions */
+#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
+
+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
+
+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
+
+
+/* ADC.EVCTRL bit masks and bit positions */
+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
+
+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
+
+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
+#define ADC_EVACT_gp 0 /* Event Action Select group position. */
+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
+
+
+/* ADC.PRESCALER bit masks and bit positions */
+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
+
+
+/* ADC.CALCTRL bit masks and bit positions */
+#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
+#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
+
+
+/* ADC.INTFLAGS bit masks and bit positions */
+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
+
+
+/* RTC - Real-Time Clounter */
+/* RTC.CTRL bit masks and bit positions */
+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
+
+
+/* RTC.STATUS bit masks and bit positions */
+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
+
+
+/* RTC.INTCTRL bit masks and bit positions */
+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
+
+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
+
+
+/* RTC.INTFLAGS bit masks and bit positions */
+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
+
+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* EBI - External Bus Interface */
+/* EBI_CS.CTRLA bit masks and bit positions */
+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
+
+#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
+#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
+#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
+#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
+#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
+#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
+
+
+/* EBI_CS.CTRLB bit masks and bit positions */
+#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
+#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
+#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
+#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
+#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
+#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
+#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
+#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
+
+#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
+#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
+
+#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
+#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
+
+#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
+#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
+#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
+#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
+#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
+#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
+
+
+/* EBI.CTRL bit masks and bit positions */
+#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
+#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
+#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
+#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
+#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
+#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
+
+#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
+#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
+#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
+#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
+#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
+#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
+
+#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
+#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
+#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
+#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
+#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
+#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
+
+#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
+#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
+#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
+#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
+#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
+#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
+
+
+/* EBI.SDRAMCTRLA bit masks and bit positions */
+#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
+#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
+
+#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
+#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
+
+#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
+#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
+#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
+#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
+#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
+#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
+
+
+/* EBI.SDRAMCTRLB bit masks and bit positions */
+#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
+#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
+#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
+#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
+#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
+#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
+
+#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
+#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
+#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
+#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
+#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
+#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
+#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
+#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
+
+#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
+#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
+#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
+#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
+#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
+#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
+#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
+#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
+
+
+/* EBI.SDRAMCTRLC bit masks and bit positions */
+#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
+#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
+#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
+#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
+#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
+#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
+
+#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+
+#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
+#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
+#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
+#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
+#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
+#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
+#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
+#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
+
+
+/* TWI - Two-Wire Interface */
+/* TWI_MASTER.CTRLA bit masks and bit positions */
+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
+
+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
+
+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
+
+
+/* TWI_MASTER.CTRLB bit masks and bit positions */
+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
+
+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
+
+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_MASTER.CTRLC bit masks and bit positions */
+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
+#define TWI_MASTER_CMD_gp 0 /* Command group position. */
+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_MASTER.STATUS bit masks and bit positions */
+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
+
+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
+
+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
+
+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
+
+
+/* TWI_SLAVE.CTRLA bit masks and bit positions */
+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
+
+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
+
+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
+
+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
+
+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
+
+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
+
+
+/* TWI_SLAVE.CTRLB bit masks and bit positions */
+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
+
+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
+
+
+/* TWI_SLAVE.STATUS bit masks and bit positions */
+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
+
+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
+
+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
+
+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
+
+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
+
+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
+
+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
+
+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
+
+
+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
+
+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
+
+
+/* TWI.CTRL bit masks and bit positions */
+#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
+#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
+
+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
+
+
+/* PORT - Port Configuration */
+/* PORTCFG.VPCTRLA bit masks and bit positions */
+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
+
+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
+
+
+/* PORTCFG.VPCTRLB bit masks and bit positions */
+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
+
+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
+
+
+/* PORTCFG.CLKEVOUT bit masks and bit positions */
+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
+
+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
+
+
+/* VPORT.INTFLAGS bit masks and bit positions */
+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.INTCTRL bit masks and bit positions */
+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
+
+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
+
+
+/* PORT.INTFLAGS bit masks and bit positions */
+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* PORT.PIN0CTRL bit masks and bit positions */
+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
+
+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
+
+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
+
+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
+
+
+/* PORT.PIN1CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN2CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN3CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN4CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN5CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN6CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* PORT.PIN7CTRL bit masks and bit positions */
+/* PORT_SRLEN_bm Predefined. */
+/* PORT_SRLEN_bp Predefined. */
+
+/* PORT_INVEN_bm Predefined. */
+/* PORT_INVEN_bp Predefined. */
+
+/* PORT_OPC_gm Predefined. */
+/* PORT_OPC_gp Predefined. */
+/* PORT_OPC0_bm Predefined. */
+/* PORT_OPC0_bp Predefined. */
+/* PORT_OPC1_bm Predefined. */
+/* PORT_OPC1_bp Predefined. */
+/* PORT_OPC2_bm Predefined. */
+/* PORT_OPC2_bp Predefined. */
+
+/* PORT_ISC_gm Predefined. */
+/* PORT_ISC_gp Predefined. */
+/* PORT_ISC0_bm Predefined. */
+/* PORT_ISC0_bp Predefined. */
+/* PORT_ISC1_bm Predefined. */
+/* PORT_ISC1_bp Predefined. */
+/* PORT_ISC2_bm Predefined. */
+/* PORT_ISC2_bp Predefined. */
+
+
+/* TC - 16-bit Timer/Counter With PWM */
+/* TC0.CTRLA bit masks and bit positions */
+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC0.CTRLB bit masks and bit positions */
+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
+
+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
+
+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC0.CTRLC bit masks and bit positions */
+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
+
+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
+
+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC0.CTRLD bit masks and bit positions */
+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC0_EVACT_gp 5 /* Event Action group position. */
+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC0.CTRLE bit masks and bit positions */
+#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC0.INTCTRLA bit masks and bit positions */
+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC0.INTCTRLB bit masks and bit positions */
+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
+
+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
+
+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC0.CTRLFCLR bit masks and bit positions */
+#define TC0_CMD_gm 0x0C /* Command group mask. */
+#define TC0_CMD_gp 2 /* Command group position. */
+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC0_CMD0_bp 2 /* Command bit 0 position. */
+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC0_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC0_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC0_DIR_bm 0x01 /* Direction bit mask. */
+#define TC0_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC0.CTRLFSET bit masks and bit positions */
+/* TC0_CMD_gm Predefined. */
+/* TC0_CMD_gp Predefined. */
+/* TC0_CMD0_bm Predefined. */
+/* TC0_CMD0_bp Predefined. */
+/* TC0_CMD1_bm Predefined. */
+/* TC0_CMD1_bp Predefined. */
+
+/* TC0_LUPD_bm Predefined. */
+/* TC0_LUPD_bp Predefined. */
+
+/* TC0_DIR_bm Predefined. */
+/* TC0_DIR_bp Predefined. */
+
+
+/* TC0.CTRLGCLR bit masks and bit positions */
+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
+
+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
+
+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC0.CTRLGSET bit masks and bit positions */
+/* TC0_CCDBV_bm Predefined. */
+/* TC0_CCDBV_bp Predefined. */
+
+/* TC0_CCCBV_bm Predefined. */
+/* TC0_CCCBV_bp Predefined. */
+
+/* TC0_CCBBV_bm Predefined. */
+/* TC0_CCBBV_bp Predefined. */
+
+/* TC0_CCABV_bm Predefined. */
+/* TC0_CCABV_bp Predefined. */
+
+/* TC0_PERBV_bm Predefined. */
+/* TC0_PERBV_bp Predefined. */
+
+
+/* TC0.INTFLAGS bit masks and bit positions */
+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
+
+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
+
+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* TC1.CTRLA bit masks and bit positions */
+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
+
+
+/* TC1.CTRLB bit masks and bit positions */
+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
+
+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
+
+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
+
+
+/* TC1.CTRLC bit masks and bit positions */
+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
+
+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
+
+
+/* TC1.CTRLD bit masks and bit positions */
+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
+#define TC1_EVACT_gp 5 /* Event Action group position. */
+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
+
+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
+
+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
+
+
+/* TC1.CTRLE bit masks and bit positions */
+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
+
+
+/* TC1.INTCTRLA bit masks and bit positions */
+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
+
+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
+
+
+/* TC1.INTCTRLB bit masks and bit positions */
+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
+
+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
+
+
+/* TC1.CTRLFCLR bit masks and bit positions */
+#define TC1_CMD_gm 0x0C /* Command group mask. */
+#define TC1_CMD_gp 2 /* Command group position. */
+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
+#define TC1_CMD0_bp 2 /* Command bit 0 position. */
+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
+#define TC1_CMD1_bp 3 /* Command bit 1 position. */
+
+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
+#define TC1_LUPD_bp 1 /* Lock Update bit position. */
+
+#define TC1_DIR_bm 0x01 /* Direction bit mask. */
+#define TC1_DIR_bp 0 /* Direction bit position. */
+
+
+/* TC1.CTRLFSET bit masks and bit positions */
+/* TC1_CMD_gm Predefined. */
+/* TC1_CMD_gp Predefined. */
+/* TC1_CMD0_bm Predefined. */
+/* TC1_CMD0_bp Predefined. */
+/* TC1_CMD1_bm Predefined. */
+/* TC1_CMD1_bp Predefined. */
+
+/* TC1_LUPD_bm Predefined. */
+/* TC1_LUPD_bp Predefined. */
+
+/* TC1_DIR_bm Predefined. */
+/* TC1_DIR_bp Predefined. */
+
+
+/* TC1.CTRLGCLR bit masks and bit positions */
+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
+
+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
+
+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
+
+
+/* TC1.CTRLGSET bit masks and bit positions */
+/* TC1_CCBBV_bm Predefined. */
+/* TC1_CCBBV_bp Predefined. */
+
+/* TC1_CCABV_bm Predefined. */
+/* TC1_CCABV_bp Predefined. */
+
+/* TC1_PERBV_bm Predefined. */
+/* TC1_PERBV_bp Predefined. */
+
+
+/* TC1.INTFLAGS bit masks and bit positions */
+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
+
+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
+
+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
+
+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
+
+
+/* AWEX.CTRL bit masks and bit positions */
+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
+
+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
+
+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
+
+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
+
+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
+
+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
+
+
+/* AWEX.FDCTRL bit masks and bit positions */
+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
+
+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
+
+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
+
+
+/* AWEX.STATUS bit masks and bit positions */
+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
+
+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
+
+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
+
+
+/* HIRES.CTRLA bit masks and bit positions */
+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
+
+
+/* USART - Universal Asynchronous Receiver-Transmitter */
+/* USART.STATUS bit masks and bit positions */
+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
+
+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
+
+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
+
+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
+#define USART_FERR_bp 4 /* Frame Error bit position. */
+
+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
+
+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
+#define USART_PERR_bp 2 /* Parity Error bit position. */
+
+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
+
+
+/* USART.CTRLA bit masks and bit positions */
+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
+
+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
+
+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
+
+
+/* USART.CTRLB bit masks and bit positions */
+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
+
+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
+
+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
+
+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
+
+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
+
+
+/* USART.CTRLC bit masks and bit positions */
+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
+#define USART_CMODE_gp 6 /* Communication Mode group position. */
+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
+
+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
+#define USART_PMODE_gp 4 /* Parity Mode group position. */
+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
+
+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
+
+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
+#define USART_CHSIZE_gp 0 /* Character Size group position. */
+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
+
+
+/* USART.BAUDCTRLA bit masks and bit positions */
+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
+
+
+/* USART.BAUDCTRLB bit masks and bit positions */
+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
+
+/* USART_BSEL_gm Predefined. */
+/* USART_BSEL_gp Predefined. */
+/* USART_BSEL0_bm Predefined. */
+/* USART_BSEL0_bp Predefined. */
+/* USART_BSEL1_bm Predefined. */
+/* USART_BSEL1_bp Predefined. */
+/* USART_BSEL2_bm Predefined. */
+/* USART_BSEL2_bp Predefined. */
+/* USART_BSEL3_bm Predefined. */
+/* USART_BSEL3_bp Predefined. */
+
+
+/* SPI - Serial Peripheral Interface */
+/* SPI.CTRL bit masks and bit positions */
+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
+
+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
+
+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
+
+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
+
+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
+#define SPI_MODE_gp 2 /* SPI Mode group position. */
+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
+
+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
+
+
+/* SPI.INTCTRL bit masks and bit positions */
+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
+
+
+/* SPI.STATUS bit masks and bit positions */
+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
+
+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
+
+
+/* IRCOM - IR Communication Module */
+/* IRCOM.CTRL bit masks and bit positions */
+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
+
+
+
+// Generic Port Pins
+
+#define PIN0_bm 0x01
+#define PIN0_bp 0
+#define PIN1_bm 0x02
+#define PIN1_bp 1
+#define PIN2_bm 0x04
+#define PIN2_bp 2
+#define PIN3_bm 0x08
+#define PIN3_bp 3
+#define PIN4_bm 0x10
+#define PIN4_bp 4
+#define PIN5_bm 0x20
+#define PIN5_bp 5
+#define PIN6_bm 0x40
+#define PIN6_bp 6
+#define PIN7_bm 0x80
+#define PIN7_bp 7
+
+
+/* ========== Interrupt Vector Definitions ========== */
+/* Vector 0 is the reset vector */
+
+/* OSC interrupt vectors */
+#define OSC_XOSCF_vect_num 1
+#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
+
+/* PORTC interrupt vectors */
+#define PORTC_INT0_vect_num 2
+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
+#define PORTC_INT1_vect_num 3
+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
+
+/* PORTR interrupt vectors */
+#define PORTR_INT0_vect_num 4
+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
+#define PORTR_INT1_vect_num 5
+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
+
+/* RTC interrupt vectors */
+#define RTC_OVF_vect_num 10
+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
+#define RTC_COMP_vect_num 11
+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
+
+/* TWIC interrupt vectors */
+#define TWIC_TWIS_vect_num 12
+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
+#define TWIC_TWIM_vect_num 13
+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
+
+/* TCC0 interrupt vectors */
+#define TCC0_OVF_vect_num 14
+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
+#define TCC0_ERR_vect_num 15
+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
+#define TCC0_CCA_vect_num 16
+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
+#define TCC0_CCB_vect_num 17
+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
+#define TCC0_CCC_vect_num 18
+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
+#define TCC0_CCD_vect_num 19
+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
+
+/* TCC1 interrupt vectors */
+#define TCC1_OVF_vect_num 20
+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
+#define TCC1_ERR_vect_num 21
+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
+#define TCC1_CCA_vect_num 22
+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
+#define TCC1_CCB_vect_num 23
+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
+
+/* SPIC interrupt vectors */
+#define SPIC_INT_vect_num 24
+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
+
+/* USARTC0 interrupt vectors */
+#define USARTC0_RXC_vect_num 25
+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
+#define USARTC0_DRE_vect_num 26
+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
+#define USARTC0_TXC_vect_num 27
+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
+
+/* NVM interrupt vectors */
+#define NVM_EE_vect_num 32
+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
+#define NVM_SPM_vect_num 33
+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
+
+/* PORTB interrupt vectors */
+#define PORTB_INT0_vect_num 34
+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
+#define PORTB_INT1_vect_num 35
+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
+
+/* PORTE interrupt vectors */
+#define PORTE_INT0_vect_num 43
+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
+#define PORTE_INT1_vect_num 44
+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
+
+/* TCE0 interrupt vectors */
+#define TCE0_OVF_vect_num 47
+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
+#define TCE0_ERR_vect_num 48
+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
+#define TCE0_CCA_vect_num 49
+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
+#define TCE0_CCB_vect_num 50
+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
+#define TCE0_CCC_vect_num 51
+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
+#define TCE0_CCD_vect_num 52
+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
+
+/* USARTE0 interrupt vectors */
+#define USARTE0_RXC_vect_num 58
+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
+#define USARTE0_DRE_vect_num 59
+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
+#define USARTE0_TXC_vect_num 60
+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
+
+/* PORTD interrupt vectors */
+#define PORTD_INT0_vect_num 64
+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
+#define PORTD_INT1_vect_num 65
+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
+
+/* PORTA interrupt vectors */
+#define PORTA_INT0_vect_num 66
+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
+#define PORTA_INT1_vect_num 67
+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
+
+/* ACA interrupt vectors */
+#define ACA_AC0_vect_num 68
+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
+#define ACA_AC1_vect_num 69
+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
+#define ACA_ACW_vect_num 70
+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
+
+/* ADCA interrupt vectors */
+#define ADCA_CH0_vect_num 71
+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
+
+/* TCD0 interrupt vectors */
+#define TCD0_OVF_vect_num 77
+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
+#define TCD0_ERR_vect_num 78
+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
+#define TCD0_CCA_vect_num 79
+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
+#define TCD0_CCB_vect_num 80
+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
+#define TCD0_CCC_vect_num 81
+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
+#define TCD0_CCD_vect_num 82
+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
+
+/* SPID interrupt vectors */
+#define SPID_INT_vect_num 87
+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
+
+/* USARTD0 interrupt vectors */
+#define USARTD0_RXC_vect_num 88
+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
+#define USARTD0_DRE_vect_num 89
+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
+#define USARTD0_TXC_vect_num 90
+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
+
+/* PORTF interrupt vectors */
+#define PORTF_INT0_vect_num 104
+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
+#define PORTF_INT1_vect_num 105
+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
+
+/* TCF0 interrupt vectors */
+#define TCF0_OVF_vect_num 108
+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
+#define TCF0_ERR_vect_num 109
+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
+#define TCF0_CCA_vect_num 110
+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
+#define TCF0_CCB_vect_num 111
+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
+#define TCF0_CCC_vect_num 112
+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
+#define TCF0_CCD_vect_num 113
+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
+
+
+#define _VECTOR_SIZE 4 /* Size of individual vector. */
+#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
+
+
+/* ========== Constants ========== */
+
+#define PROGMEM_START (0x0000)
+#define PROGMEM_SIZE (69632)
+#define PROGMEM_PAGE_SIZE (256)
+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
+
+#define APP_SECTION_START (0x0000)
+#define APP_SECTION_SIZE (65536)
+#define APP_SECTION_PAGE_SIZE (256)
+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
+
+#define APPTABLE_SECTION_START (0x0F000)
+#define APPTABLE_SECTION_SIZE (4096)
+#define APPTABLE_SECTION_PAGE_SIZE (256)
+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+
+#define BOOT_SECTION_START (0x10000)
+#define BOOT_SECTION_SIZE (4096)
+#define BOOT_SECTION_PAGE_SIZE (256)
+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
+
+#define DATAMEM_START (0x0000)
+#define DATAMEM_SIZE (12288)
+#define DATAMEM_PAGE_SIZE (0)
+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
+
+#define IO_START (0x0000)
+#define IO_SIZE (4096)
+#define IO_PAGE_SIZE (0)
+#define IO_END (IO_START + IO_SIZE - 1)
+
+#define MAPPED_EEPROM_START (0x1000)
+#define MAPPED_EEPROM_SIZE (2048)
+#define MAPPED_EEPROM_PAGE_SIZE (0)
+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
+
+#define INTERNAL_SRAM_START (0x2000)
+#define INTERNAL_SRAM_SIZE (4096)
+#define INTERNAL_SRAM_PAGE_SIZE (0)
+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
+
+#define EEPROM_START (0x0000)
+#define EEPROM_SIZE (2048)
+#define EEPROM_PAGE_SIZE (32)
+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
+
+#define FUSE_START (0x0000)
+#define FUSE_SIZE (6)
+#define FUSE_PAGE_SIZE (0)
+#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
+
+#define LOCKBIT_START (0x0000)
+#define LOCKBIT_SIZE (1)
+#define LOCKBIT_PAGE_SIZE (0)
+#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
+
+#define SIGNATURES_START (0x0000)
+#define SIGNATURES_SIZE (3)
+#define SIGNATURES_PAGE_SIZE (0)
+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
+
+#define USER_SIGNATURES_START (0x0000)
+#define USER_SIGNATURES_SIZE (256)
+#define USER_SIGNATURES_PAGE_SIZE (0)
+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+
+#define PROD_SIGNATURES_START (0x0000)
+#define PROD_SIGNATURES_SIZE (52)
+#define PROD_SIGNATURES_PAGE_SIZE (0)
+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+
+#define FLASHEND PROGMEM_END
+#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
+#define RAMSTART INTERNAL_SRAM_START
+#define RAMSIZE INTERNAL_SRAM_SIZE
+#define RAMEND INTERNAL_SRAM_END
+#define XRAMSTART EXTERNAL_SRAM_START
+#define XRAMSIZE EXTERNAL_SRAM_SIZE
+#define XRAMEND INTERNAL_SRAM_END
+#define E2END EEPROM_END
+#define E2PAGESIZE EEPROM_PAGE_SIZE
+
+
+/* ========== Fuses ========== */
+#define FUSE_MEMORY_SIZE 6
+
+/* Fuse Byte 0 */
+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
+#define FUSE0_DEFAULT (0xFF)
+
+/* Fuse Byte 1 */
+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
+#define FUSE1_DEFAULT (0xFF)
+
+/* Fuse Byte 2 */
+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
+#define FUSE2_DEFAULT (0xFF)
+
+/* Fuse Byte 3 Reserved */
+
+/* Fuse Byte 4 */
+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
+#define FUSE4_DEFAULT (0xFF)
+
+/* Fuse Byte 5 */
+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
+#define FUSE5_DEFAULT (0xFF)
+
+
+/* ========== Lock Bits ========== */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
+#define __BOOT_LOCK_APPLICATION_BITS_EXIST
+#define __BOOT_LOCK_BOOT_BITS_EXIST
+
+
+/* ========== Signature ========== */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x96
+#define SIGNATURE_2 0x4A
+
+
+#endif /* _AVR_ATxmega64D3_H_ */
+
diff -u rtems/cpukit/score/cpu/avr/avr/lock.h:1.2 rtems/cpukit/score/cpu/avr/avr/lock.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/lock.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/lock.h Mon May 10 11:31:23 2010
@@ -41,72 +41,72 @@
\par Introduction
- The Lockbit API allows a user to specify the lockbit settings for the
- specific AVR device they are compiling for. These lockbit settings will be
+ The Lockbit API allows a user to specify the lockbit settings for the
+ specific AVR device they are compiling for. These lockbit settings will be
placed in a special section in the ELF output file, after linking.
Programming tools can take advantage of the lockbit information embedded in
the ELF file, by extracting this information and determining if the lockbits
need to be programmed after programming the Flash and EEPROM memories.
This also allows a single ELF file to contain all the
- information needed to program an AVR.
+ information needed to program an AVR.
To use the Lockbit API, include the <avr/io.h> header file, which in turn
automatically includes the individual I/O header file and the <avr/lock.h>
file. These other two files provides everything necessary to set the AVR
lockbits.
-
+
\par Lockbit API
-
+
Each I/O header file may define up to 3 macros that controls what kinds
of lockbits are available to the user.
-
+
If __LOCK_BITS_EXIST is defined, then two lock bits are available to the
user and 3 mode settings are defined for these two bits.
-
+
If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are
available to the user and 4 mode settings are defined for these two bits.
-
+
If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are
available to the user and 4 mode settings are defined for these two bits.
If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits
- are available to set the locking mode for the Application Table Section
+ are available to set the locking mode for the Application Table Section
(which is used in the XMEGA family).
-
+
If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are
available to set the locking mode for the Application Section (which is used
in the XMEGA family).
-
+
If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available
to set the locking mode for the Boot Loader Section (which is used in the
XMEGA family).
- The AVR lockbit modes have inverted values, logical 1 for an unprogrammed
- (disabled) bit and logical 0 for a programmed (enabled) bit. The defined
- macros for each individual lock bit represent this in their definition by a
- bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined
+ The AVR lockbit modes have inverted values, logical 1 for an unprogrammed
+ (disabled) bit and logical 0 for a programmed (enabled) bit. The defined
+ macros for each individual lock bit represent this in their definition by a
+ bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined
as:
\code
#define LB_MODE_3 (0xFC)
` \endcode
-
+
To combine the lockbit mode macros together to represent a whole byte,
use the bitwise AND operator, like so:
\code
(LB_MODE_3 & BLB0_MODE_2)
\endcode
-
+
<avr/lock.h> also defines a macro that provides a default lockbit value:
LOCKBITS_DEFAULT which is defined to be 0xFF.
See the AVR device specific datasheet for more details about these
lock bits and the available mode settings.
-
- A convenience macro, LOCKMEM, is defined as a GCC attribute for a
+
+ A convenience macro, LOCKMEM, is defined as a GCC attribute for a
custom-named section of ".lock".
-
- A convenience macro, LOCKBITS, is defined that declares a variable, __lock,
+
+ A convenience macro, LOCKBITS, is defined that declares a variable, __lock,
of type unsigned char with the attribute defined by LOCKMEM. This variable
allows the end user to easily set the lockbit data.
@@ -116,9 +116,9 @@
currently known to be defined in the I/O header files for the XMEGA devices.
\par API Usage Example
-
+
Putting all of this together is easy:
-
+
\code
#include <avr/io.h>
@@ -129,13 +129,13 @@
return 0;
}
\endcode
-
+
Or:
-
+
\code
#include <avr/io.h>
- unsigned char __lock __attribute__((section (".lock"))) =
+ unsigned char __lock __attribute__((section (".lock"))) =
(LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
int main(void)
@@ -143,36 +143,36 @@
return 0;
}
\endcode
-
-
-
+
+
+
However there are a number of caveats that you need to be aware of to
use this API properly.
-
+
Be sure to include <avr/io.h> to get all of the definitions for the API.
- The LOCKBITS macro defines a global variable to store the lockbit data. This
- variable is assigned to its own linker section. Assign the desired lockbit
+ The LOCKBITS macro defines a global variable to store the lockbit data. This
+ variable is assigned to its own linker section. Assign the desired lockbit
values immediately in the variable initialization.
-
- The .lock section in the ELF file will get its values from the initial
- variable assignment ONLY. This means that you can NOT assign values to
+
+ The .lock section in the ELF file will get its values from the initial
+ variable assignment ONLY. This means that you can NOT assign values to
this variable in functions and the new values will not be put into the
ELF .lock section.
-
- The global variable is declared in the LOCKBITS macro has two leading
+
+ The global variable is declared in the LOCKBITS macro has two leading
underscores, which means that it is reserved for the "implementation",
meaning the library, so it will not conflict with a user-named variable.
-
+
You must initialize the lockbit variable to some meaningful value, even
- if it is the default value. This is because the lockbits default to a
- logical 1, meaning unprogrammed. Normal uninitialized data defaults to all
- locgial zeros. So it is vital that all lockbits are initialized, even with
- default data. If they are not, then the lockbits may not programmed to the
- desired settings and can possibly put your device into an unrecoverable
+ if it is the default value. This is because the lockbits default to a
+ logical 1, meaning unprogrammed. Normal uninitialized data defaults to all
+ locgial zeros. So it is vital that all lockbits are initialized, even with
+ default data. If they are not, then the lockbits may not programmed to the
+ desired settings and can possibly put your device into an unrecoverable
state.
-
+
Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
- your linker command line to have the correct device selected and to have
+ your linker command line to have the correct device selected and to have
the correct I/O header file included when you include <avr/io.h>.
You can print out the contents of the .lock section in the ELF file by
diff -u rtems/cpukit/score/cpu/avr/avr/pgmspace.h:1.2 rtems/cpukit/score/cpu/avr/avr/pgmspace.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/pgmspace.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/pgmspace.h Mon May 10 11:31:24 2010
@@ -403,7 +403,7 @@
/** \ingroup avr_pgmspace
\def pgm_read_byte_near(address_short)
- Read a byte from the program space with a 16-bit (near) address.
+ Read a byte from the program space with a 16-bit (near) address.
\note The address is a byte address.
The address is in the program space. */
@@ -411,16 +411,16 @@
/** \ingroup avr_pgmspace
\def pgm_read_word_near(address_short)
- Read a word from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ Read a word from the program space with a 16-bit (near) address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short))
/** \ingroup avr_pgmspace
\def pgm_read_dword_near(address_short)
- Read a double word from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ Read a double word from the program space with a 16-bit (near) address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_dword_near(address_short) \
@@ -428,8 +428,8 @@
/** \ingroup avr_pgmspace
\def pgm_read_float_near(address_short)
- Read a float from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ Read a float from the program space with a 16-bit (near) address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_float_near(address_short) \
@@ -719,10 +719,10 @@
__result; \
}))
-/*
-Check for architectures that implement RAMPD (avrxmega3, avrxmega5,
+/*
+Check for architectures that implement RAMPD (avrxmega3, avrxmega5,
avrxmega7) as they need to save/restore RAMPZ for ELPM macros so it does
-not interfere with data accesses.
+not interfere with data accesses.
*/
#if defined (__AVR_HAVE_RAMPD__)
@@ -754,16 +754,16 @@
/** \ingroup avr_pgmspace
\def pgm_read_byte_far(address_long)
- Read a byte from the program space with a 32-bit (far) address.
+ Read a byte from the program space with a 32-bit (far) address.
- \note The address is a byte address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_byte_far(address_long) __ELPM((uint32_t)(address_long))
/** \ingroup avr_pgmspace
\def pgm_read_word_far(address_long)
- Read a word from the program space with a 32-bit (far) address.
+ Read a word from the program space with a 32-bit (far) address.
\note The address is a byte address.
The address is in the program space. */
@@ -772,7 +772,7 @@
/** \ingroup avr_pgmspace
\def pgm_read_dword_far(address_long)
- Read a double word from the program space with a 32-bit (far) address.
+ Read a double word from the program space with a 32-bit (far) address.
\note The address is a byte address.
The address is in the program space. */
@@ -781,7 +781,7 @@
/** \ingroup avr_pgmspace
\def pgm_read_float_far(address_long)
- Read a float from the program space with a 32-bit (far) address.
+ Read a float from the program space with a 32-bit (far) address.
\note The address is a byte address.
The address is in the program space. */
@@ -792,36 +792,36 @@
/** \ingroup avr_pgmspace
\def pgm_read_byte(address_short)
- Read a byte from the program space with a 16-bit (near) address.
+ Read a byte from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_byte(address_short) pgm_read_byte_near(address_short)
/** \ingroup avr_pgmspace
\def pgm_read_word(address_short)
- Read a word from the program space with a 16-bit (near) address.
+ Read a word from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_word(address_short) pgm_read_word_near(address_short)
/** \ingroup avr_pgmspace
\def pgm_read_dword(address_short)
- Read a double word from the program space with a 16-bit (near) address.
+ Read a double word from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_dword(address_short) pgm_read_dword_near(address_short)
/** \ingroup avr_pgmspace
\def pgm_read_float(address_short)
- Read a float from the program space with a 16-bit (near) address.
+ Read a float from the program space with a 16-bit (near) address.
- \note The address is a byte address.
+ \note The address is a byte address.
The address is in the program space. */
#define pgm_read_float(address_short) pgm_read_float_near(address_short)
@@ -847,6 +847,7 @@
extern PGM_VOID_P memchr_P(PGM_VOID_P, int __val, size_t __len) __ATTR_CONST__;
extern int memcmp_P(const void *, PGM_VOID_P, size_t) __ATTR_PURE__;
+extern void *memccpy_P(void *, PGM_VOID_P, int __val, size_t);
extern void *memcpy_P(void *, PGM_VOID_P, size_t);
extern void *memmem_P(const void *, size_t, PGM_VOID_P, size_t) __ATTR_PURE__;
extern PGM_VOID_P memrchr_P(PGM_VOID_P, int __val, size_t __len) __ATTR_CONST__;
@@ -871,6 +872,8 @@
extern char *strsep_P(char **__sp, PGM_P __delim);
extern size_t strspn_P(const char *__s, PGM_P __accept) __ATTR_PURE__;
extern char *strstr_P(const char *, PGM_P) __ATTR_PURE__;
+extern char *strtok_P(char *__s, PGM_P __delim);
+extern char *strtok_rP(char *__s, PGM_P __delim, char **__last);
#ifdef __cplusplus
}
diff -u rtems/cpukit/score/cpu/avr/avr/portpins.h:1.1 rtems/cpukit/score/cpu/avr/avr/portpins.h:1.2
--- rtems/cpukit/score/cpu/avr/avr/portpins.h:1.1 Thu Aug 6 09:52:06 2009
+++ rtems/cpukit/score/cpu/avr/avr/portpins.h Mon May 10 11:31:24 2010
@@ -71,303 +71,479 @@
#define PIN1 1
#define PIN0 0
-/* Define PORTxn values for all possible port pins. */
+/* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */
/* PORT A */
-#if defined(PA0)
+#if defined(PA0) && !defined(PORTA0)
# define PORTA0 PA0
+#elif defined(PORTA0) && !defined(PA0)
+# define PA0 PORTA0
#endif
-#if defined(PA1)
+#if defined(PA1) && !defined(PORTA1)
# define PORTA1 PA1
+#elif defined(PORTA1) && !defined(PA1)
+# define PA1 PORTA1
#endif
-#if defined(PA2)
+#if defined(PA2) && !defined(PORTA2)
# define PORTA2 PA2
+#elif defined(PORTA2) && !defined(PA2)
+# define PA2 PORTA2
#endif
-#if defined(PA3)
+#if defined(PA3) && !defined(PORTA3)
# define PORTA3 PA3
+#elif defined(PORTA3) && !defined(PA3)
+# define PA3 PORTA3
#endif
-#if defined(PA4)
+#if defined(PA4) && !defined(PORTA4)
# define PORTA4 PA4
+#elif defined(PORTA4) && !defined(PA4)
+# define PA4 PORTA4
#endif
-#if defined(PA5)
+#if defined(PA5) && !defined(PORTA5)
# define PORTA5 PA5
+#elif defined(PORTA5) && !defined(PA5)
+# define PA5 PORTA5
#endif
-#if defined(PA6)
+#if defined(PA6) && !defined(PORTA6)
# define PORTA6 PA6
+#elif defined(PORTA6) && !defined(PA6)
+# define PA6 PORTA6
#endif
-#if defined(PA7)
+#if defined(PA7) && !defined(PORTA7)
# define PORTA7 PA7
+#elif defined(PORTA7) && !defined(PA7)
+# define PA7 PORTA7
#endif
/* PORT B */
-#if defined(PB0)
+#if defined(PB0) && !defined(PORTB0)
# define PORTB0 PB0
+#elif defined(PORTB0) && !defined(PB0)
+# define PB0 PORTB0
#endif
-#if defined(PB1)
+#if defined(PB1) && !defined(PORTB1)
# define PORTB1 PB1
+#elif defined(PORTB1) && !defined(PB1)
+# define PB1 PORTB1
#endif
-#if defined(PB2)
+#if defined(PB2) && !defined(PORTB2)
# define PORTB2 PB2
+#elif defined(PORTB2) && !defined(PB2)
+# define PB2 PORTB2
#endif
-#if defined(PB3)
+#if defined(PB3) && !defined(PORTB3)
# define PORTB3 PB3
+#elif defined(PORTB3) && !defined(PB3)
+# define PB3 PORTB3
#endif
-#if defined(PB4)
+#if defined(PB4) && !defined(PORTB4)
# define PORTB4 PB4
+#elif defined(PORTB4) && !defined(PB4)
+# define PB4 PORTB4
#endif
-#if defined(PB5)
+#if defined(PB5) && !defined(PORTB5)
# define PORTB5 PB5
+#elif defined(PORTB5) && !defined(PB5)
+# define PB5 PORTB5
#endif
-#if defined(PB6)
+#if defined(PB6) && !defined(PORTB6)
# define PORTB6 PB6
+#elif defined(PORTB6) && !defined(PB6)
+# define PB6 PORTB6
#endif
-#if defined(PB7)
+#if defined(PB7) && !defined(PORTB7)
# define PORTB7 PB7
+#elif defined(PORTB7) && !defined(PB7)
+# define PB7 PORTB7
#endif
/* PORT C */
-#if defined(PC0)
+#if defined(PC0) && !defined(PORTC0)
# define PORTC0 PC0
+#elif defined(PORTC0) && !defined(PC0)
+# define PC0 PORTC0
#endif
-#if defined(PC1)
+#if defined(PC1) && !defined(PORTC1)
# define PORTC1 PC1
+#elif defined(PORTC1) && !defined(PC1)
+# define PC1 PORTC1
#endif
-#if defined(PC2)
+#if defined(PC2) && !defined(PORTC2)
# define PORTC2 PC2
+#elif defined(PORTC2) && !defined(PC2)
+# define PC2 PORTC2
#endif
-#if defined(PC3)
+#if defined(PC3) && !defined(PORTC3)
# define PORTC3 PC3
+#elif defined(PORTC3) && !defined(PC3)
+# define PC3 PORTC3
#endif
-#if defined(PC4)
+#if defined(PC4) && !defined(PORTC4)
# define PORTC4 PC4
+#elif defined(PORTC4) && !defined(PC4)
+# define PC4 PORTC4
#endif
-#if defined(PC5)
+#if defined(PC5) && !defined(PORTC5)
# define PORTC5 PC5
+#elif defined(PORTC5) && !defined(PC5)
+# define PC5 PORTC5
#endif
-#if defined(PC6)
+#if defined(PC6) && !defined(PORTC6)
# define PORTC6 PC6
+#elif defined(PORTC6) && !defined(PC6)
+# define PC6 PORTC6
#endif
-#if defined(PC7)
+#if defined(PC7) && !defined(PORTC7)
# define PORTC7 PC7
+#elif defined(PORTC7) && !defined(PC7)
+# define PC7 PORTC7
#endif
/* PORT D */
-#if defined(PD0)
+#if defined(PD0) && !defined(PORTD0)
# define PORTD0 PD0
+#elif defined(PORTD0) && !defined(PD0)
+# define PD0 PORTD0
#endif
-#if defined(PD1)
+#if defined(PD1) && !defined(PORTD1)
# define PORTD1 PD1
+#elif defined(PORTD1) && !defined(PD1)
+# define PD1 PORTD1
#endif
-#if defined(PD2)
+#if defined(PD2) && !defined(PORTD2)
# define PORTD2 PD2
+#elif defined(PORTD2) && !defined(PD2)
+# define PD2 PORTD2
#endif
-#if defined(PD3)
+#if defined(PD3) && !defined(PORTD3)
# define PORTD3 PD3
+#elif defined(PORTD3) && !defined(PD3)
+# define PD3 PORTD3
#endif
-#if defined(PD4)
+#if defined(PD4) && !defined(PORTD4)
# define PORTD4 PD4
+#elif defined(PORTD4) && !defined(PD4)
+# define PD4 PORTD4
#endif
-#if defined(PD5)
+#if defined(PD5) && !defined(PORTD5)
# define PORTD5 PD5
+#elif defined(PORTD5) && !defined(PD5)
+# define PD5 PORTD5
#endif
-#if defined(PD6)
+#if defined(PD6) && !defined(PORTD6)
# define PORTD6 PD6
+#elif defined(PORTD6) && !defined(PD6)
+# define PD6 PORTD6
#endif
-#if defined(PD7)
+#if defined(PD7) && !defined(PORTD7)
# define PORTD7 PD7
+#elif defined(PORTD7) && !defined(PD7)
+# define PD7 PORTD7
#endif
/* PORT E */
-#if defined(PE0)
+#if defined(PE0) && !defined(PORTE0)
# define PORTE0 PE0
+#elif defined(PORTE0) && !defined(PE0)
+# define PE0 PORTE0
#endif
-#if defined(PE1)
+#if defined(PE1) && !defined(PORTE1)
# define PORTE1 PE1
+#elif defined(PORTE1) && !defined(PE1)
+# define PE1 PORTE1
#endif
-#if defined(PE2)
+#if defined(PE2) && !defined(PORTE2)
# define PORTE2 PE2
+#elif defined(PORTE2) && !defined(PE2)
+# define PE2 PORTE2
#endif
-#if defined(PE3)
+#if defined(PE3) && !defined(PORTE3)
# define PORTE3 PE3
+#elif defined(PORTE3) && !defined(PE3)
+# define PE3 PORTE3
#endif
-#if defined(PE4)
+#if defined(PE4) && !defined(PORTE4)
# define PORTE4 PE4
+#elif defined(PORTE4) && !defined(PE4)
+# define PE4 PORTE4
#endif
-#if defined(PE5)
+#if defined(PE5) && !defined(PORTE5)
# define PORTE5 PE5
+#elif defined(PORTE5) && !defined(PE5)
+# define PE5 PORTE5
#endif
-#if defined(PE6)
+#if defined(PE6) && !defined(PORTE6)
# define PORTE6 PE6
+#elif defined(PORTE6) && !defined(PE6)
+# define PE6 PORTE6
#endif
-#if defined(PE7)
+#if defined(PE7) && !defined(PORTE7)
# define PORTE7 PE7
+#elif defined(PORTE7) && !defined(PE7)
+# define PE7 PORTE7
#endif
/* PORT F */
-#if defined(PF0)
+#if defined(PF0) && !defined(PORTF0)
# define PORTF0 PF0
+#elif defined(PORTF0) && !defined(PF0)
+# define PF0 PORTF0
#endif
-#if defined(PF1)
+#if defined(PF1) && !defined(PORTF1)
# define PORTF1 PF1
+#elif defined(PORTF1) && !defined(PF1)
+# define PF1 PORTF1
#endif
-#if defined(PF2)
+#if defined(PF2) && !defined(PORTF2)
# define PORTF2 PF2
+#elif defined(PORTF2) && !defined(PF2)
+# define PF2 PORTF2
#endif
-#if defined(PF3)
+#if defined(PF3) && !defined(PORTF3)
# define PORTF3 PF3
+#elif defined(PORTF3) && !defined(PF3)
+# define PF3 PORTF3
#endif
-#if defined(PF4)
+#if defined(PF4) && !defined(PORTF4)
# define PORTF4 PF4
+#elif defined(PORTF4) && !defined(PF4)
+# define PF4 PORTF4
#endif
-#if defined(PF5)
+#if defined(PF5) && !defined(PORTF5)
# define PORTF5 PF5
+#elif defined(PORTF5) && !defined(PF5)
+# define PF5 PORTF5
#endif
-#if defined(PF6)
+#if defined(PF6) && !defined(PORTF6)
# define PORTF6 PF6
+#elif defined(PORTF6) && !defined(PF6)
+# define PF6 PORTF6
#endif
-#if defined(PF7)
+#if defined(PF7) && !defined(PORTF7)
# define PORTF7 PF7
+#elif defined(PORTF7) && !defined(PF7)
+# define PF7 PORTF7
#endif
/* PORT G */
-#if defined(PG0)
+#if defined(PG0) && !defined(PORTG0)
# define PORTG0 PG0
+#elif defined(PORTG0) && !defined(PG0)
+# define PG0 PORTG0
#endif
-#if defined(PG1)
+#if defined(PG1) && !defined(PORTG1)
# define PORTG1 PG1
+#elif defined(PORTG1) && !defined(PG1)
+# define PG1 PORTG1
#endif
-#if defined(PG2)
+#if defined(PG2) && !defined(PORTG2)
# define PORTG2 PG2
+#elif defined(PORTG2) && !defined(PG2)
+# define PG2 PORTG2
#endif
-#if defined(PG3)
+#if defined(PG3) && !defined(PORTG3)
# define PORTG3 PG3
+#elif defined(PORTG3) && !defined(PG3)
+# define PG3 PORTG3
#endif
-#if defined(PG4)
+#if defined(PG4) && !defined(PORTG4)
# define PORTG4 PG4
+#elif defined(PORTG4) && !defined(PG4)
+# define PG4 PORTG4
#endif
-#if defined(PG5)
+#if defined(PG5) && !defined(PORTG5)
# define PORTG5 PG5
+#elif defined(PORTG5) && !defined(PG5)
+# define PG5 PORTG5
#endif
-#if defined(PG6)
+#if defined(PG6) && !defined(PORTG6)
# define PORTG6 PG6
+#elif defined(PORTG6) && !defined(PG6)
+# define PG6 PORTG6
#endif
-#if defined(PG7)
+#if defined(PG7) && !defined(PORTG7)
# define PORTG7 PG7
+#elif defined(PORTG7) && !defined(PG7)
+# define PG7 PORTG7
#endif
/* PORT H */
-#if defined(PH0)
+#if defined(PH0) && !defined(PORTH0)
# define PORTH0 PH0
+#elif defined(PORTH0) && !defined(PH0)
+# define PH0 PORTH0
#endif
-#if defined(PH1)
+#if defined(PH1) && !defined(PORTH1)
# define PORTH1 PH1
+#elif defined(PORTH1) && !defined(PH1)
+# define PH1 PORTH1
#endif
-#if defined(PH2)
+#if defined(PH2) && !defined(PORTH2)
# define PORTH2 PH2
+#elif defined(PORTH2) && !defined(PH2)
+# define PH2 PORTH2
#endif
-#if defined(PH3)
+#if defined(PH3) && !defined(PORTH3)
# define PORTH3 PH3
+#elif defined(PORTH3) && !defined(PH3)
+# define PH3 PORTH3
#endif
-#if defined(PH4)
+#if defined(PH4) && !defined(PORTH4)
# define PORTH4 PH4
+#elif defined(PORTH4) && !defined(PH4)
+# define PH4 PORTH4
#endif
-#if defined(PH5)
+#if defined(PH5) && !defined(PORTH5)
# define PORTH5 PH5
+#elif defined(PORTH5) && !defined(PH5)
+# define PH5 PORTH5
#endif
-#if defined(PH6)
+#if defined(PH6) && !defined(PORTH6)
# define PORTH6 PH6
+#elif defined(PORTH6) && !defined(PH6)
+# define PH6 PORTH6
#endif
-#if defined(PH7)
+#if defined(PH7) && !defined(PORTH7)
# define PORTH7 PH7
+#elif defined(PORTH7) && !defined(PH7)
+# define PH7 PORTH7
#endif
/* PORT J */
-#if defined(PJ0)
+#if defined(PJ0) && !defined(PORTJ0)
# define PORTJ0 PJ0
+#elif defined(PORTJ0) && !defined(PJ0)
+# define PJ0 PORTJ0
#endif
-#if defined(PJ1)
+#if defined(PJ1) && !defined(PORTJ1)
# define PORTJ1 PJ1
+#elif defined(PORTJ1) && !defined(PJ1)
+# define PJ1 PORTJ1
#endif
-#if defined(PJ2)
+#if defined(PJ2) && !defined(PORTJ2)
# define PORTJ2 PJ2
+#elif defined(PORTJ2) && !defined(PJ2)
+# define PJ2 PORTJ2
#endif
-#if defined(PJ3)
+#if defined(PJ3) && !defined(PORTJ3)
# define PORTJ3 PJ3
+#elif defined(PORTJ3) && !defined(PJ3)
+# define PJ3 PORTJ3
#endif
-#if defined(PJ4)
+#if defined(PJ4) && !defined(PORTJ4)
# define PORTJ4 PJ4
+#elif defined(PORTJ4) && !defined(PJ4)
+# define PJ4 PORTJ4
#endif
-#if defined(PJ5)
+#if defined(PJ5) && !defined(PORTJ5)
# define PORTJ5 PJ5
+#elif defined(PORTJ5) && !defined(PJ5)
+# define PJ5 PORTJ5
#endif
-#if defined(PJ6)
+#if defined(PJ6) && !defined(PORTJ6)
# define PORTJ6 PJ6
+#elif defined(PORTJ6) && !defined(PJ6)
+# define PJ6 PORTJ6
#endif
-#if defined(PJ7)
+#if defined(PJ7) && !defined(PORTJ7)
# define PORTJ7 PJ7
+#elif defined(PORTJ7) && !defined(PJ7)
+# define PJ7 PORTJ7
#endif
/* PORT K */
-#if defined(PK0)
+#if defined(PK0) && !defined(PORTK0)
# define PORTK0 PK0
+#elif defined(PORTK0) && !defined(PK0)
+# define PK0 PORTK0
#endif
-#if defined(PK1)
+#if defined(PK1) && !defined(PORTK1)
# define PORTK1 PK1
+#elif defined(PORTK1) && !defined(PK1)
+# define PK1 PORTK1
#endif
-#if defined(PK2)
+#if defined(PK2) && !defined(PORTK2)
# define PORTK2 PK2
+#elif defined(PORTK2) && !defined(PK2)
+# define PK2 PORTK2
#endif
-#if defined(PK3)
+#if defined(PK3) && !defined(PORTK3)
# define PORTK3 PK3
+#elif defined(PORTK3) && !defined(PK3)
+# define PK3 PORTK3
#endif
-#if defined(PK4)
+#if defined(PK4) && !defined(PORTK4)
# define PORTK4 PK4
+#elif defined(PORTK4) && !defined(PK4)
+# define PK4 PORTK4
#endif
-#if defined(PK5)
+#if defined(PK5) && !defined(PORTK5)
# define PORTK5 PK5
+#elif defined(PORTK5) && !defined(PK5)
+# define PK5 PORTK5
#endif
-#if defined(PK6)
+#if defined(PK6) && !defined(PORTK6)
# define PORTK6 PK6
+#elif defined(PORTK6) && !defined(PK6)
+# define PK6 PORTK6
#endif
-#if defined(PK7)
+#if defined(PK7) && !defined(PORTK7)
# define PORTK7 PK7
+#elif defined(PORTK7) && !defined(PK7)
+# define PK7 PORTK7
#endif
/* PORT L */
-#if defined(PL0)
+#if defined(PL0) && !defined(PORTL0)
# define PORTL0 PL0
+#elif defined(PORTL0) && !defined(PL0)
+# define PL0 PORTL0
#endif
-#if defined(PL1)
+#if defined(PL1) && !defined(PORTL1)
# define PORTL1 PL1
+#elif defined(PORTL1) && !defined(PL1)
+# define PL1 PORTL1
#endif
-#if defined(PL2)
+#if defined(PL2) && !defined(PORTL2)
# define PORTL2 PL2
+#elif defined(PORTL2) && !defined(PL2)
+# define PL2 PORTL2
#endif
-#if defined(PL3)
+#if defined(PL3) && !defined(PORTL3)
# define PORTL3 PL3
+#elif defined(PORTL3) && !defined(PL3)
+# define PL3 PORTL3
#endif
-#if defined(PL4)
+#if defined(PL4) && !defined(PORTL4)
# define PORTL4 PL4
+#elif defined(PORTL4) && !defined(PL4)
+# define PL4 PORTL4
#endif
-#if defined(PL5)
+#if defined(PL5) && !defined(PORTL5)
# define PORTL5 PL5
+#elif defined(PORTL5) && !defined(PL5)
+# define PL5 PORTL5
#endif
-#if defined(PL6)
+#if defined(PL6) && !defined(PORTL6)
# define PORTL6 PL6
+#elif defined(PORTL6) && !defined(PL6)
+# define PL6 PORTL6
#endif
-#if defined(PL7)
+#if defined(PL7) && !defined(PORTL7)
# define PORTL7 PL7
+#elif defined(PORTL7) && !defined(PL7)
+# define PL7 PORTL7
#endif
#endif /* _AVR_PORTPINS_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/power.h:1.2 rtems/cpukit/score/cpu/avr/avr/power.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/power.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/power.h Mon May 10 11:31:24 2010
@@ -40,20 +40,20 @@
\code #include <avr/power.h>\endcode
-Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
-allow you to reduce power consumption by disabling or enabling various on-board
+Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
+allow you to reduce power consumption by disabling or enabling various on-board
peripherals as needed.
There are many macros in this header file that provide an easy interface
to enable or disable on-board peripherals to reduce power. See the table below.
\note Not all AVR devices have a Power Reduction Register (for example
-the ATmega128). On those devices without a Power Reduction Register, these
+the ATmega128). On those devices without a Power Reduction Register, these
macros are not available.
\note Not all AVR devices contain the same peripherals (for example, the LCD
-interface), or they will be named differently (for example, USART and
-USART0). Please consult your device's datasheet, or the header file, to
+interface), or they will be named differently (for example, USART and
+USART0). Please consult your device's datasheet, or the header file, to
find out which macros are applicable to your device.
*/
@@ -347,10 +347,15 @@
|| defined(__AVR_ATxmega32D4__) \
|| defined(__AVR_ATxmega64A1__) \
|| defined(__AVR_ATxmega64A3__) \
+|| defined(__AVR_ATxmega64D3__) \
|| defined(__AVR_ATxmega128A1__) \
|| defined(__AVR_ATxmega128A3__) \
+|| defined(__AVR_ATxmega128D3__) \
+|| defined(__AVR_ATxmega192A3__) \
+|| defined(__AVR_ATxmega192D3__) \
+|| defined(__AVR_ATxmega256D3__) \
|| defined(__AVR_ATxmega256A3__) \
-|| defined(__AVR_ATxmega256A3b__)
+|| defined(__AVR_ATxmega256A3B__)
/*
#define power_aes_enable() (PR_PR &= (uint8_t)~(PR_AES_bm))
@@ -477,7 +482,7 @@
|| defined(__AVR_ATmega1280__) \
|| defined(__AVR_ATmega1281__) \
|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__)
+|| defined(__AVR_ATmega2561__)
#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
#define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
@@ -625,7 +630,7 @@
#elif defined(__AVR_ATmega32U4__) \
-defined(__AVR_ATmega16U4__)
+|| defined(__AVR_ATmega16U4__)
#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
@@ -806,11 +811,16 @@
#elif defined(__AVR_ATmega165__) \
+|| defined(__AVR_ATmega165A__) \
|| defined(__AVR_ATmega165P__) \
|| defined(__AVR_ATmega325__) \
|| defined(__AVR_ATmega3250__) \
|| defined(__AVR_ATmega645__) \
-|| defined(__AVR_ATmega6450__)
+|| defined(__AVR_ATmega645A__) \
+|| defined(__AVR_ATmega645P__) \
+|| defined(__AVR_ATmega6450__) \
+|| defined(__AVR_ATmega6450A__) \
+|| defined(__AVR_ATmega6450P__)
#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
@@ -829,13 +839,20 @@
#elif defined(__AVR_ATmega169__) \
+|| defined(__AVR_ATmega169A__) \
|| defined(__AVR_ATmega169P__) \
+|| defined(__AVR_ATmega169PA__) \
|| defined(__AVR_ATmega329__) \
|| defined(__AVR_ATmega329P__) \
+|| defined(__AVR_ATmega329PA__) \
|| defined(__AVR_ATmega3290__) \
|| defined(__AVR_ATmega3290P__) \
|| defined(__AVR_ATmega649__) \
-|| defined(__AVR_ATmega6490__)
+|| defined(__AVR_ATmega649A__) \
+|| defined(__AVR_ATmega649P__) \
+|| defined(__AVR_ATmega6490__) \
+|| defined(__AVR_ATmega6490A__) \
+|| defined(__AVR_ATmega6490P__)
#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
@@ -856,8 +873,11 @@
#define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRSPI)|(1<<PRUSART0)|(1<<PRTIM1)|(1<<PRLCD)))
-#elif defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega324P__)
+#elif defined(__AVR_ATmega164A__) \
+|| defined(__AVR_ATmega164P__) \
+|| defined(__AVR_ATmega324A__) \
+|| defined(__AVR_ATmega324P__) \
+|| defined(__AVR_ATmega324PA__)
#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
#define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC))
@@ -888,6 +908,7 @@
#elif defined(__AVR_ATmega644__) \
+|| defined(__AVR_ATmega644A__) \
|| defined(__AVR_ATmega644P__)
#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC))
@@ -935,11 +956,16 @@
#elif defined(__AVR_ATmega48__) \
+|| defined(__AVR_ATmega48A__) \
|| defined(__AVR_ATmega48P__) \
|| defined(__AVR_ATmega88__) \
+|| defined(__AVR_ATmega88A__) \
|| defined(__AVR_ATmega88P__) \
+|| defined(__AVR_ATmega88PA__) \
|| defined(__AVR_ATmega168__) \
+|| defined(__AVR_ATmega168A__) \
|| defined(__AVR_ATmega168P__) \
+|| defined(__AVR_ATmega328__) \
|| defined(__AVR_ATmega328P__) \
|| defined(__AVR_ATtiny48__) \
|| defined(__AVR_ATtiny88__)
@@ -970,14 +996,19 @@
#elif defined(__AVR_ATtiny24__) \
+|| defined(__AVR_ATtiny24A__) \
|| defined(__AVR_ATtiny44__) \
+|| defined(__AVR_ATtiny44A__) \
|| defined(__AVR_ATtiny84__) \
|| defined(__AVR_ATtiny25__) \
|| defined(__AVR_ATtiny45__) \
|| defined(__AVR_ATtiny85__) \
|| defined(__AVR_ATtiny261__) \
+|| defined(__AVR_ATtiny261A__) \
|| defined(__AVR_ATtiny461__) \
+|| defined(__AVR_ATtiny461A__) \
|| defined(__AVR_ATtiny861__) \
+|| defined(__AVR_ATtiny861A__) \
|| defined(__AVR_ATtiny43U__)
#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
@@ -1124,8 +1155,10 @@
#elif defined(__AVR_AT90USB82__) \
-|| defined(__AVR_AT90USB162__)
-
+|| defined(__AVR_AT90USB162__) \
+|| defined(__AVR_ATmega8U2__) \
+|| defined(__AVR_ATmega16U2__) \
+|| defined(__AVR_ATmega32U2__)
#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI))
#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI))
@@ -1134,7 +1167,7 @@
#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0))
#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1))
-#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
+#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1))
#define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB))
#define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB))
@@ -1205,21 +1238,22 @@
PRR1 |= (uint8_t)((1<<PRUSBH)|(1<<PRUSB)|(1<<PRHSSPI)|(1<<PRSCI)|(1<<PRAES)|(1<<PRKB)); \
}while(0)
+
+#elif defined(__AVR_ATtiny13A__)
+
+#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC))
+#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC))
+
+#define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0))
+#define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0))
+
+#define power_all_enable() (PRR &= (uint8_t)~((1<<PRADC)|(1<<PRTIM0)))
+#define power_all_disable() (PRR |= (uint8_t)((1<<PRADC)|(1<<PRTIM0)))
+
#endif
-#if defined(__AVR_ATmega640__) \
-|| defined(__AVR_ATmega1280__) \
-|| defined(__AVR_ATmega1281__) \
-|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__) \
-|| defined(__AVR_AT90USB646__) \
-|| defined(__AVR_AT90USB647__) \
-|| defined(__AVR_AT90USB82__) \
-|| defined(__AVR_AT90USB1286__) \
-|| defined(__AVR_AT90USB1287__) \
-|| defined(__AVR_AT90USB162__) \
-|| defined(__AVR_AT90CAN32__) \
+#if defined(__AVR_AT90CAN32__) \
|| defined(__AVR_AT90CAN64__) \
|| defined(__AVR_AT90CAN128__) \
|| defined(__AVR_AT90PWM1__) \
@@ -1229,38 +1263,69 @@
|| defined(__AVR_AT90PWM3B__) \
|| defined(__AVR_AT90PWM216__) \
|| defined(__AVR_AT90PWM316__) \
-|| defined(__AVR_ATmega32M1__) \
+|| defined(__AVR_AT90SCR100__) \
+|| defined(__AVR_AT90USB646__) \
+|| defined(__AVR_AT90USB647__) \
+|| defined(__AVR_AT90USB82__) \
+|| defined(__AVR_AT90USB1286__) \
+|| defined(__AVR_AT90USB1287__) \
+|| defined(__AVR_AT90USB162__) \
+|| defined(__AVR_ATmega1280__) \
+|| defined(__AVR_ATmega1281__) \
+|| defined(__AVR_ATmega128RFA1__) \
|| defined(__AVR_ATmega1284P__) \
|| defined(__AVR_ATmega162__) \
+|| defined(__AVR_ATmega164A__) \
+|| defined(__AVR_ATmega164P__) \
|| defined(__AVR_ATmega165__) \
+|| defined(__AVR_ATmega165A__) \
|| defined(__AVR_ATmega165P__) \
+|| defined(__AVR_ATmega168__) \
+|| defined(__AVR_ATmega168P__) \
+|| defined(__AVR_ATmega169__) \
+|| defined(__AVR_ATmega169A__) \
+|| defined(__AVR_ATmega169P__) \
+|| defined(__AVR_ATmega169PA__) \
+|| defined(__AVR_ATmega16U4__) \
+|| defined(__AVR_ATmega2560__) \
+|| defined(__AVR_ATmega2561__) \
+|| defined(__AVR_ATmega324A__) \
+|| defined(__AVR_ATmega324P__) \
|| defined(__AVR_ATmega325__) \
|| defined(__AVR_ATmega3250__) \
+|| defined(__AVR_ATmega328P__) \
+|| defined(__AVR_ATmega329__) \
+|| defined(__AVR_ATmega329P__) \
+|| defined(__AVR_ATmega329PA__) \
+|| defined(__AVR_ATmega3290__) \
+|| defined(__AVR_ATmega32C1__) \
|| defined(__AVR_ATmega32HVB__) \
+|| defined(__AVR_ATmega32M1__) \
+|| defined(__AVR_ATmega32U4__) \
+|| defined(__AVR_ATmega32U6__) \
+|| defined(__AVR_ATmega48__) \
+|| defined(__AVR_ATmega48P__) \
+|| defined(__AVR_ATmega640__) \
+|| defined(__AVR_ATmega649P__) \
+|| defined(__AVR_ATmega644__) \
+|| defined(__AVR_ATmega644A__) \
+|| defined(__AVR_ATmega644P__) \
+|| defined(__AVR_ATmega644PA__) \
|| defined(__AVR_ATmega645__) \
+|| defined(__AVR_ATmega645A__) \
+|| defined(__AVR_ATmega645P__) \
|| defined(__AVR_ATmega6450__) \
-|| defined(__AVR_ATmega169__) \
-|| defined(__AVR_ATmega169P__) \
-|| defined(__AVR_ATmega329__) \
-|| defined(__AVR_ATmega3290__) \
+|| defined(__AVR_ATmega6450A__) \
+|| defined(__AVR_ATmega6450P__) \
|| defined(__AVR_ATmega649__) \
+|| defined(__AVR_ATmega649A__) \
|| defined(__AVR_ATmega6490__) \
-|| defined(__AVR_ATmega48__) \
-|| defined(__AVR_ATmega48P__) \
+|| defined(__AVR_ATmega6490A__) \
+|| defined(__AVR_ATmega6490P__) \
|| defined(__AVR_ATmega88__) \
|| defined(__AVR_ATmega88P__) \
-|| defined(__AVR_ATmega168__) \
-|| defined(__AVR_ATmega168P__) \
-|| defined(__AVR_ATmega328P__) \
-|| defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega324P__) \
-|| defined(__AVR_ATmega644__) \
-|| defined(__AVR_ATmega644P__) \
|| defined(__AVR_ATtiny48__) \
|| defined(__AVR_ATtiny167__) \
-|| defined(__AVR_ATmega32U4__) \
-|| defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_AT90SCR100__) \
|| defined(__DOXYGEN__)
@@ -1277,7 +1342,7 @@
/** \addtogroup avr_power
-\code
+\code
typedef enum
{
clock_div_1 = 0,
@@ -1288,7 +1353,8 @@
clock_div_32 = 5,
clock_div_64 = 6,
clock_div_128 = 7,
- clock_div_256 = 8
+ clock_div_256 = 8,
+ clock_div_1_rc = 15, // ATmega128RFA1 only
} clock_div_t;
\endcode
Clock prescaler setting enumerations.
@@ -1304,29 +1370,38 @@
clock_div_32 = 5,
clock_div_64 = 6,
clock_div_128 = 7,
- clock_div_256 = 8
+ clock_div_256 = 8,
+#if defined(__AVR_ATmega128RFA1__)
+ clock_div_1_rc = 15,
+#endif
} clock_div_t;
+static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
+
/** \addtogroup avr_power
\code clock_prescale_set(x) \endcode
-Set the clock prescaler register select bits, selecting a system clock division setting. They type of x is clock_div_t.
+Set the clock prescaler register select bits, selecting a system clock
+division setting. This function is inlined, even if compiler
+optimizations are disabled.
+
+The type of x is clock_div_t.
*/
-#define clock_prescale_set(x) \
-{ \
- uint8_t tmp = _BV(CLKPCE); \
- __asm__ __volatile__ ( \
- "in __tmp_reg__,__SREG__" "\n\t" \
- "cli" "\n\t" \
- "sts %1, %0" "\n\t" \
- "sts %1, %2" "\n\t" \
- "out __SREG__, __tmp_reg__" \
- : /* no outputs */ \
- : "d" (tmp), \
- "M" (_SFR_MEM_ADDR(CLKPR)), \
- "d" (x) \
- : "r0"); \
+void clock_prescale_set(clock_div_t __x)
+{
+ uint8_t __tmp = _BV(CLKPCE);
+ __asm__ __volatile__ (
+ "in __tmp_reg__,__SREG__" "\n\t"
+ "cli" "\n\t"
+ "sts %1, %0" "\n\t"
+ "sts %1, %2" "\n\t"
+ "out __SREG__, __tmp_reg__"
+ : /* no outputs */
+ : "d" (__tmp),
+ "M" (_SFR_MEM_ADDR(CLKPR)),
+ "d" (__x)
+ : "r0");
}
/** \addtogroup avr_power
@@ -1338,15 +1413,22 @@
#elif defined(__AVR_ATtiny24__) \
+|| defined(__AVR_ATtiny24A__) \
|| defined(__AVR_ATtiny44__) \
+|| defined(__AVR_ATtiny44A__) \
|| defined(__AVR_ATtiny84__) \
|| defined(__AVR_ATtiny25__) \
|| defined(__AVR_ATtiny45__) \
|| defined(__AVR_ATtiny85__) \
+|| defined(__AVR_ATtiny261A__) \
|| defined(__AVR_ATtiny261__) \
|| defined(__AVR_ATtiny461__) \
+|| defined(__AVR_ATtiny461A__) \
|| defined(__AVR_ATtiny861__) \
+|| defined(__AVR_ATtiny861A__) \
|| defined(__AVR_ATtiny2313__) \
+|| defined(__AVR_ATtiny2313A__) \
+|| defined(__AVR_ATtiny4313__) \
|| defined(__AVR_ATtiny13__) \
|| defined(__AVR_ATtiny13A__) \
|| defined(__AVR_ATtiny43U__) \
@@ -1365,20 +1447,20 @@
} clock_div_t;
-#define clock_prescale_set(x) \
-{ \
- uint8_t tmp = _BV(CLKPCE); \
- __asm__ __volatile__ ( \
- "in __tmp_reg__,__SREG__" "\n\t" \
- "cli" "\n\t" \
- "out %1, %0" "\n\t" \
- "out %1, %2" "\n\t" \
- "out __SREG__, __tmp_reg__" \
- : /* no outputs */ \
- : "d" (tmp), \
- "I" (_SFR_IO_ADDR(CLKPR)), \
- "d" (x) \
- : "r0"); \
+void clock_prescale_set(clock_div_t __x)
+{
+ uint8_t __tmp = _BV(CLKPCE);
+ __asm__ __volatile__ (
+ "in __tmp_reg__,__SREG__" "\n\t"
+ "cli" "\n\t"
+ "out %1, %0" "\n\t"
+ "out %1, %2" "\n\t"
+ "out __SREG__, __tmp_reg__"
+ : /* no outputs */
+ : "d" (__tmp),
+ "I" (_SFR_IO_ADDR(CLKPR)),
+ "d" (__x)
+ : "r0");
}
diff -u rtems/cpukit/score/cpu/avr/avr/sfr_defs.h:1.2 rtems/cpukit/score/cpu/avr/avr/sfr_defs.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/sfr_defs.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/sfr_defs.h Mon May 10 11:31:24 2010
@@ -204,7 +204,7 @@
\note The bit shift is performed by the compiler which then inserts the
result into the code. Thus, there is no run-time overhead when using
_BV(). */
-
+
#define _BV(bit) (1 << (bit))
/*@}*/
@@ -227,7 +227,7 @@
\code #include <avr/io.h>\endcode
- Test whether bit \c bit in IO register \c sfr is set.
+ Test whether bit \c bit in IO register \c sfr is set.
This will return a 0 if the bit is clear, and non-zero
if the bit is set. */
@@ -238,7 +238,7 @@
\code #include <avr/io.h>\endcode
- Test whether bit \c bit in IO register \c sfr is clear.
+ Test whether bit \c bit in IO register \c sfr is clear.
This will return non-zero if the bit is clear, and a 0
if the bit is set. */
diff -u /dev/null rtems/cpukit/score/cpu/avr/avr/signature.h:1.1
--- /dev/null Mon May 10 12:11:03 2010
+++ rtems/cpukit/score/cpu/avr/avr/signature.h Mon May 10 11:31:24 2010
@@ -0,0 +1,84 @@
+/* Copyright (c) 2009, Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/signature.h - Signature API */
+
+#ifndef _AVR_SIGNATURE_H_
+#define _AVR_SIGNATURE_H_ 1
+
+/** \file */
+/** \defgroup avr_signature <avr/signature.h>: Signature Support
+
+ \par Introduction
+
+ The <avr/signature.h> header file allows the user to automatically
+ and easily include the device's signature data in a special section of
+ the final linked ELF file.
+
+ This value can then be used by programming software to compare the on-device
+ signature with the signature recorded in the ELF file to look for a match
+ before programming the device.
+
+ \par API Usage Example
+
+ Usage is very simple; just include the header file:
+
+ \code
+ #include <avr/signature.h>
+ \endcode
+
+ This will declare a constant unsigned char array and it is initialized with
+ the three signature bytes, MSB first, that are defined in the device I/O
+ header file. This array is then placed in the .signature section in the
+ resulting linked ELF file.
+
+ The three signature bytes that are used to initialize the array are
+ these defined macros in the device I/O header file, from MSB to LSB:
+ SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
+
+ This header file should only be included once in an application.
+*/
+
+#ifndef __ASSEMBLER__
+
+#include <avr/io.h>
+
+#if defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2)
+
+const unsigned char __signature[3] __attribute__((section (".signature"))) =
+ { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 };
+
+#endif /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _AVR_SIGNATURE_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/sleep.h:1.2 rtems/cpukit/score/cpu/avr/avr/sleep.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/sleep.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/sleep.h Mon May 10 11:31:24 2010
@@ -55,9 +55,9 @@
set the desired sleep mode using \c set_sleep_mode() (it usually
defaults to idle mode where the CPU is put on sleep but all
peripheral clocks are still running), and then call
- \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
+ \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
to sleep, and clears the sleep enable bit.
-
+
Example:
\code
#include <avr/sleep.h>
@@ -66,8 +66,8 @@
set_sleep_mode(<mode>);
sleep_mode();
\endcode
-
- Note that unless your purpose is to completely lock the CPU (until a
+
+ Note that unless your purpose is to completely lock the CPU (until a
hardware reset), interrupts need to be enabled before going to sleep.
As the \c sleep_mode() macro might cause race conditions in some
@@ -103,7 +103,7 @@
after the \c SEI is guaranteed to be executed before an interrupt
could trigger, it is sure the device will really be put to sleep.
- Some devices have the ability to disable the Brown Out Detector (BOD) before
+ Some devices have the ability to disable the Brown Out Detector (BOD) before
going to sleep. This will also reduce power while sleeping. If the
specific AVR device has this ability then an additional macro is defined:
\c sleep_bod_disable(). This macro generates inlined assembly code
@@ -231,15 +231,20 @@
|| defined(__AVR_ATtiny13A__) \
|| defined(__AVR_ATtiny15__) \
|| defined(__AVR_ATtiny24__) \
+|| defined(__AVR_ATtiny24A__) \
|| defined(__AVR_ATtiny44__) \
+|| defined(__AVR_ATtiny44A__) \
|| defined(__AVR_ATtiny84__) \
|| defined(__AVR_ATtiny25__) \
|| defined(__AVR_ATtiny45__) \
|| defined(__AVR_ATtiny48__) \
|| defined(__AVR_ATtiny85__) \
|| defined(__AVR_ATtiny261__) \
+|| defined(__AVR_ATtiny261A__) \
|| defined(__AVR_ATtiny461__) \
+|| defined(__AVR_ATtiny461A__) \
|| defined(__AVR_ATtiny861__) \
+|| defined(__AVR_ATtiny861A__) \
|| defined(__AVR_ATtiny88__)
#define SLEEP_MODE_IDLE 0
@@ -252,7 +257,9 @@
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
} while(0)
-#elif defined(__AVR_ATtiny2313__)
+#elif defined(__AVR_ATtiny2313__) \
+|| defined(__AVR_ATtiny2313A__) \
+|| defined(__AVR_ATtiny4313__)
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_PWR_DOWN (_BV(SM0) | _BV(SM1))
@@ -301,74 +308,103 @@
_SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
} while(0)
-#elif \
-defined(__AVR_AT90PWM1__) \
+#elif defined(__AVR_AT90CAN128__) \
+|| defined(__AVR_AT90CAN32__) \
+|| defined(__AVR_AT90CAN64__) \
+|| defined(__AVR_AT90PWM1__) \
|| defined(__AVR_AT90PWM2__) \
|| defined(__AVR_AT90PWM2B__) \
|| defined(__AVR_AT90PWM3__) \
|| defined(__AVR_AT90PWM3B__) \
+|| defined(__AVR_AT90USB162__) \
+|| defined(__AVR_AT90USB82__) \
+|| defined(__AVR_AT90USB1286__) \
+|| defined(__AVR_AT90USB1287__) \
+|| defined(__AVR_AT90USB646__) \
+|| defined(__AVR_AT90USB647__) \
|| defined(__AVR_ATmega128__) \
+|| defined(__AVR_ATmega1280__) \
+|| defined(__AVR_ATmega1281__) \
+|| defined(__AVR_ATmega1284P__) \
+|| defined(__AVR_ATmega128RFA1__) \
|| defined(__AVR_ATmega16__) \
+|| defined(__AVR_ATmega16A__) \
|| defined(__AVR_ATmega162__) \
+|| defined(__AVR_ATmega164A__) \
+|| defined(__AVR_ATmega164P__) \
|| defined(__AVR_ATmega165__) \
+|| defined(__AVR_ATmega165A__) \
|| defined(__AVR_ATmega165P__) \
+|| defined(__AVR_ATmega168__) \
+|| defined(__AVR_ATmega168A__) \
+|| defined(__AVR_ATmega168P__) \
|| defined(__AVR_ATmega169__) \
+|| defined(__AVR_ATmega169A__) \
|| defined(__AVR_ATmega169P__) \
+|| defined(__AVR_ATmega169PA__) \
+|| defined(__AVR_ATmega16HVA__) \
+|| defined(__AVR_ATmega16HVA2__) \
+|| defined(__AVR_ATmega16HVB__) \
+|| defined(__AVR_ATmega16M1__) \
+|| defined(__AVR_ATmega16U2__) \
+|| defined(__AVR_ATmega16U4__) \
+|| defined(__AVR_ATmega2560__) \
+|| defined(__AVR_ATmega2561__) \
|| defined(__AVR_ATmega32__) \
|| defined(__AVR_ATmega323__) \
+|| defined(__AVR_ATmega324A__) \
+|| defined(__AVR_ATmega324P__) \
+|| defined(__AVR_ATmega324PA__) \
|| defined(__AVR_ATmega325__) \
|| defined(__AVR_ATmega3250__) \
+|| defined(__AVR_ATmega328__) \
+|| defined(__AVR_ATmega328P__) \
|| defined(__AVR_ATmega329__) \
|| defined(__AVR_ATmega329P__) \
+|| defined(__AVR_ATmega329PA__) \
|| defined(__AVR_ATmega3290__) \
|| defined(__AVR_ATmega3290P__) \
+|| defined(__AVR_ATmega32C1__) \
+|| defined(__AVR_ATmega32HVB__) \
+|| defined(__AVR_ATmega32M1__) \
+|| defined(__AVR_ATmega32U2__) \
+|| defined(__AVR_ATmega32U4__) \
+|| defined(__AVR_ATmega32U6__) \
|| defined(__AVR_ATmega406__) \
+|| defined(__AVR_ATmega48__) \
+|| defined(__AVR_ATmega48A__) \
+|| defined(__AVR_ATmega48P__) \
|| defined(__AVR_ATmega64__) \
+|| defined(__AVR_ATmega640__) \
+|| defined(__AVR_ATmega644__) \
+|| defined(__AVR_ATmega644A__) \
+|| defined(__AVR_ATmega644P__) \
+|| defined(__AVR_ATmega644PA__) \
|| defined(__AVR_ATmega645__) \
+|| defined(__AVR_ATmega645A__) \
+|| defined(__AVR_ATmega645P__) \
|| defined(__AVR_ATmega6450__) \
+|| defined(__AVR_ATmega6450A__) \
+|| defined(__AVR_ATmega6450P__) \
|| defined(__AVR_ATmega649__) \
+|| defined(__AVR_ATmega649A__) \
|| defined(__AVR_ATmega6490__) \
+|| defined(__AVR_ATmega6490A__) \
+|| defined(__AVR_ATmega6490P__) \
+|| defined(__AVR_ATmega649P__) \
+|| defined(__AVR_ATmega64C1__) \
+|| defined(__AVR_ATmega64HVE__) \
+|| defined(__AVR_ATmega64M1__) \
|| defined(__AVR_ATmega8__) \
|| defined(__AVR_ATmega8515__) \
|| defined(__AVR_ATmega8535__) \
-|| defined(__AVR_AT90CAN128__) \
-|| defined(__AVR_AT90CAN32__) \
-|| defined(__AVR_AT90CAN64__) \
-|| defined(__AVR_ATmega1280__) \
-|| defined(__AVR_ATmega1281__) \
-|| defined(__AVR_ATmega1284P__) \
-|| defined(__AVR_ATmega128RFA1__) \
-|| defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__) \
-|| defined(__AVR_ATmega640__) \
-|| defined(__AVR_ATmega164P__) \
-|| defined(__AVR_ATmega324P__) \
-|| defined(__AVR_ATmega644__) \
-|| defined(__AVR_ATmega644P__) \
-|| defined(__AVR_ATmega16HVA__) \
-|| defined(__AVR_ATmega8HVA__) \
-|| defined(__AVR_ATmega32HVB__) \
-|| defined(__AVR_AT90USB162__) \
-|| defined(__AVR_AT90USB82__) \
-|| defined(__AVR_AT90USB1286__) \
-|| defined(__AVR_AT90USB1287__) \
-|| defined(__AVR_AT90USB646__) \
-|| defined(__AVR_AT90USB647__) \
-|| defined(__AVR_ATmega168__) \
-|| defined(__AVR_ATmega48__) \
|| defined(__AVR_ATmega88__) \
-|| defined(__AVR_ATmega16M1__) \
-|| defined(__AVR_ATmega16U4__) \
-|| defined(__AVR_ATmega32C1__) \
-|| defined(__AVR_ATmega32M1__) \
-|| defined(__AVR_ATmega32U4__) \
-|| defined(__AVR_ATmega32U6__) \
-|| defined(__AVR_ATmega64C1__) \
-|| defined(__AVR_ATmega64M1__) \
-|| defined(__AVR_ATmega48P__) \
+|| defined(__AVR_ATmega88A__) \
|| defined(__AVR_ATmega88P__) \
-|| defined(__AVR_ATmega168P__) \
-|| defined(__AVR_ATmega328P__)
+|| defined(__AVR_ATmega88PA__) \
+|| defined(__AVR_ATmega8HVA__) \
+|| defined(__AVR_ATmega8U2__)
+
#define SLEEP_MODE_IDLE (0)
#define SLEEP_MODE_ADC _BV(SM0)
@@ -389,9 +425,14 @@
|| defined(__AVR_ATxmega32D4__) \
|| defined(__AVR_ATxmega64A1__) \
|| defined(__AVR_ATxmega64A3__) \
+|| defined(__AVR_ATxmega64D3__) \
|| defined(__AVR_ATxmega128A1__) \
|| defined(__AVR_ATxmega128A3__) \
+|| defined(__AVR_ATxmega128D3__) \
+|| defined(__AVR_ATxmega192A3__) \
+|| defined(__AVR_ATxmega192D3__) \
|| defined(__AVR_ATxmega256A3__) \
+|| defined(__AVR_ATxmega256D3__) \
|| defined(__AVR_ATxmega256A3B__)
#define SLEEP_MODE_IDLE (0)
@@ -524,7 +565,7 @@
#if defined(BODS) && defined(BODSE)
#define sleep_bod_disable() \
-{ \
+do { \
uint8_t tempreg; \
__asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
"ori %[tempreg], %[bods_bodse]" "\n\t" \
@@ -535,7 +576,7 @@
: [mcucr] "I" _SFR_IO_ADDR(MCUCR), \
[bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
[not_bodse] "i" (~_BV(BODSE))); \
-}
+} while (0)
#endif
diff -u rtems/cpukit/score/cpu/avr/avr/version.h:1.1 rtems/cpukit/score/cpu/avr/avr/version.h:1.2
--- rtems/cpukit/score/cpu/avr/avr/version.h:1.1 Thu Aug 6 09:52:06 2009
+++ rtems/cpukit/score/cpu/avr/avr/version.h Mon May 10 11:31:24 2010
@@ -55,7 +55,7 @@
/** \ingroup avr_version
String literal representation of the current library version. */
-#define __AVR_LIBC_VERSION_STRING__ "1.6.6"
+#define __AVR_LIBC_VERSION_STRING__ "1.6.8"
/** \ingroup avr_version
Numerical representation of the current library version.
@@ -65,15 +65,15 @@
added. It is intented to provide a monotonically increasing
numerical value that can easily be used in numerical checks.
*/
-#define __AVR_LIBC_VERSION__ 10606UL
+#define __AVR_LIBC_VERSION__ 10608UL
/** \ingroup avr_version
String literal representation of the release date. */
-#define __AVR_LIBC_DATE_STRING__ "20090309"
+#define __AVR_LIBC_DATE_STRING__ "20100211"
/** \ingroup avr_version
Numerical representation of the release date. */
-#define __AVR_LIBC_DATE_ 20090309UL
+#define __AVR_LIBC_DATE_ 20100211UL
/** \ingroup avr_version
Library major version number. */
@@ -85,6 +85,6 @@
/** \ingroup avr_version
Library revision number. */
-#define __AVR_LIBC_REVISION__ 6
+#define __AVR_LIBC_REVISION__ 8
#endif /* _AVR_VERSION_H_ */
diff -u rtems/cpukit/score/cpu/avr/avr/wdt.h:1.2 rtems/cpukit/score/cpu/avr/avr/wdt.h:1.3
--- rtems/cpukit/score/cpu/avr/avr/wdt.h:1.2 Mon Nov 30 10:01:45 2009
+++ rtems/cpukit/score/cpu/avr/avr/wdt.h Mon May 10 11:31:24 2010
@@ -84,7 +84,7 @@
\endcode
Saving the value of MCUSR in \c mcusr_mirror is only needed if the
- application later wants to examine the reset source, but in particular,
+ application later wants to examine the reset source, but in particular,
clearing the watchdog reset flag before disabling the
watchdog is required, according to the datasheet.
*/
@@ -93,7 +93,7 @@
\ingroup avr_watchdog
Reset the watchdog timer. When the watchdog timer is enabled,
a call to this instruction is required before the timer expires,
- otherwise a watchdog-initiated device reset will occur.
+ otherwise a watchdog-initiated device reset will occur.
*/
#define wdt_reset() __asm__ __volatile__ ("wdr")
@@ -122,8 +122,8 @@
\ingroup avr_watchdog
Enable the watchdog timer, configuring it for expiry after
\c timeout (which is a combination of the \c WDP0 through
- \c WDP2 bits to write into the \c WDTCR register; For those devices
- that have a \c WDTCSR register, it uses the combination of the \c WDP0
+ \c WDP2 bits to write into the \c WDTCR register; For those devices
+ that have a \c WDTCSR register, it uses the combination of the \c WDP0
through \c WDP3 bits).
See also the symbolic constants \c WDTO_15MS et al.
@@ -136,9 +136,14 @@
|| defined(__AVR_ATxmega32D4__) \
|| defined(__AVR_ATxmega64A1__) \
|| defined(__AVR_ATxmega64A3__) \
+|| defined(__AVR_ATxmega64D3__) \
|| defined(__AVR_ATxmega128A1__) \
|| defined(__AVR_ATxmega128A3__) \
+|| defined(__AVR_ATxmega128D3__) \
+|| defined(__AVR_ATxmega192A3__) \
+|| defined(__AVR_ATxmega192D3__) \
|| defined(__AVR_ATxmega256A3__) \
+|| defined(__AVR_ATxmega256D3__) \
|| defined(__AVR_ATxmega256A3B__)
/*
@@ -183,47 +188,75 @@
|| defined(__AVR_ATmega1284P__) \
|| defined(__AVR_ATmega128RFA1__) \
|| defined(__AVR_ATmega164__) \
+|| defined(__AVR_ATmega164A__) \
|| defined(__AVR_ATmega164P__) \
|| defined(__AVR_ATmega165__) \
+|| defined(__AVR_ATmega165A__) \
|| defined(__AVR_ATmega165P__) \
|| defined(__AVR_ATmega168__) \
+|| defined(__AVR_ATmega168A__) \
|| defined(__AVR_ATmega168P__) \
|| defined(__AVR_ATmega169__) \
+|| defined(__AVR_ATmega169A__) \
|| defined(__AVR_ATmega169P__) \
+|| defined(__AVR_ATmega169PA__) \
|| defined(__AVR_ATmega16HVA__) \
+|| defined(__AVR_ATmega16HVA2__) \
+|| defined(__AVR_ATmega16HVB__) \
|| defined(__AVR_ATmega16M1__) \
+|| defined(__AVR_ATmega16U2__) \
|| defined(__AVR_ATmega16U4__) \
|| defined(__AVR_ATmega2560__) \
|| defined(__AVR_ATmega2561__) \
|| defined(__AVR_ATmega324__) \
+|| defined(__AVR_ATmega324A__) \
|| defined(__AVR_ATmega324P__) \
+|| defined(__AVR_ATmega324PA__) \
|| defined(__AVR_ATmega325__) \
|| defined(__AVR_ATmega3250__) \
+|| defined(__AVR_ATmega328__) \
|| defined(__AVR_ATmega328P__) \
|| defined(__AVR_ATmega329__) \
|| defined(__AVR_ATmega329P__) \
+|| defined(__AVR_ATmega329PA__) \
|| defined(__AVR_ATmega3290__) \
|| defined(__AVR_ATmega3290P__) \
|| defined(__AVR_ATmega32C1__) \
|| defined(__AVR_ATmega32HVB__) \
|| defined(__AVR_ATmega32M1__) \
+|| defined(__AVR_ATmega32U2__) \
|| defined(__AVR_ATmega32U4__) \
|| defined(__AVR_ATmega32U6__) \
|| defined(__AVR_ATmega406__) \
|| defined(__AVR_ATmega48__) \
+|| defined(__AVR_ATmega48A__) \
|| defined(__AVR_ATmega48P__) \
|| defined(__AVR_ATmega640__) \
|| defined(__AVR_ATmega644__) \
+|| defined(__AVR_ATmega644A__) \
|| defined(__AVR_ATmega644P__) \
+|| defined(__AVR_ATmega644PA__) \
|| defined(__AVR_ATmega645__) \
+|| defined(__AVR_ATmega645A__) \
+|| defined(__AVR_ATmega645P__) \
|| defined(__AVR_ATmega6450__) \
+|| defined(__AVR_ATmega6450A__) \
+|| defined(__AVR_ATmega6450P__) \
|| defined(__AVR_ATmega649__) \
+|| defined(__AVR_ATmega649A__) \
|| defined(__AVR_ATmega6490__) \
+|| defined(__AVR_ATmega6490A__) \
+|| defined(__AVR_ATmega6490P__) \
+|| defined(__AVR_ATmega649P__) \
|| defined(__AVR_ATmega64C1__) \
+|| defined(__AVR_ATmega64HVE__) \
|| defined(__AVR_ATmega64M1__) \
-|| defined(__AVR_ATmega8HVA__) \
|| defined(__AVR_ATmega88__) \
+|| defined(__AVR_ATmega88A__) \
|| defined(__AVR_ATmega88P__) \
+|| defined(__AVR_ATmega88PA__) \
+|| defined(__AVR_ATmega8HVA__) \
+|| defined(__AVR_ATmega8U2__) \
|| defined(__AVR_ATtiny48__) \
|| defined(__AVR_ATtiny88__) \
|| defined(__AVR_ATtiny87__) \
@@ -232,7 +265,7 @@
|| defined(__AVR_ATA6289__)
/* Use STS instruction. */
-
+
#define wdt_enable(value) \
__asm__ __volatile__ ( \
"in __tmp_reg__,__SREG__" "\n\t" \
@@ -263,8 +296,8 @@
)
-
-#else
+
+#else
/* Use OUT instruction. */
@@ -286,8 +319,8 @@
/**
\ingroup avr_watchdog
- Disable the watchdog timer, if possible. This attempts to turn off the
- Enable bit in the watchdog control register. See the datasheet for
+ Disable the watchdog timer, if possible. This attempts to turn off the
+ Enable bit in the watchdog control register. See the datasheet for
details.
*/
#define wdt_disable() \
@@ -362,11 +395,11 @@
/** \ingroup avr_watchdog
See \c WDT0_15MS
- Note: This is only available on the
- ATtiny2313,
- ATtiny24, ATtiny44, ATtiny84,
- ATtiny25, ATtiny45, ATtiny85,
- ATtiny261, ATtiny461, ATtiny861,
+ Note: This is only available on the
+ ATtiny2313,
+ ATtiny24, ATtiny44, ATtiny84,
+ ATtiny25, ATtiny45, ATtiny85,
+ ATtiny261, ATtiny461, ATtiny861,
ATmega48, ATmega88, ATmega168,
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
ATmega164P, ATmega324P, ATmega644P, ATmega644,
@@ -383,11 +416,11 @@
/** \ingroup avr_watchdog
See \c WDT0_15MS
- Note: This is only available on the
- ATtiny2313,
- ATtiny24, ATtiny44, ATtiny84,
- ATtiny25, ATtiny45, ATtiny85,
- ATtiny261, ATtiny461, ATtiny861,
+ Note: This is only available on the
+ ATtiny2313,
+ ATtiny24, ATtiny44, ATtiny84,
+ ATtiny25, ATtiny45, ATtiny85,
+ ATtiny261, ATtiny461, ATtiny861,
ATmega48, ATmega88, ATmega168,
ATmega48P, ATmega88P, ATmega168P, ATmega328P,
ATmega164P, ATmega324P, ATmega644P, ATmega644,
@@ -403,6 +436,6 @@
#define WDTO_8S 9
#endif /* defined(__DOXYGEN__) || defined(WDP3) */
-
+
#endif /* _AVR_WDT_H_ */
diff -u rtems/cpukit/score/cpu/avr/cpu_asm.S:1.8 rtems/cpukit/score/cpu/avr/cpu_asm.S:1.9
--- rtems/cpukit/score/cpu/avr/cpu_asm.S:1.8 Sat Mar 27 10:01:24 2010
+++ rtems/cpukit/score/cpu/avr/cpu_asm.S Mon May 10 11:31:19 2010
@@ -26,9 +26,8 @@
#include "config.h"
#endif
-#include <avr/io.h>
-#include <avr/sfr_defs.h>
#include <rtems/asm.h>
+#include <avr/sfr_defs.h>
#define jmpb_hi r25
@@ -60,7 +59,6 @@
in ret_lo, AVR_STACK_POINTER_HI_ADDR
st X+, ret_lo
#else
- in ret_lo, __zero_reg__
st X+, ret_lo
#endif
/*save status reg (I flag)*/
diff -u rtems/cpukit/score/cpu/avr/rtems/asm.h:1.7 rtems/cpukit/score/cpu/avr/rtems/asm.h:1.8
--- rtems/cpukit/score/cpu/avr/rtems/asm.h:1.7 Mon Nov 30 10:01:51 2009
+++ rtems/cpukit/score/cpu/avr/rtems/asm.h Mon May 10 11:31:24 2010
@@ -142,7 +142,7 @@
Created by Marek Michalkiewicz <marekm at linux.org.pl>
*/
-#include <avr/io.h>
+#include <avr/common.h>
/* if not defined, assume old version with underscores */
#ifndef __USER_LABEL_PREFIX__
diff -u rtems/cpukit/score/cpu/avr/rtems/score/cpu.h:1.24 rtems/cpukit/score/cpu/avr/rtems/score/cpu.h:1.25
--- rtems/cpukit/score/cpu/avr/rtems/score/cpu.h:1.24 Mon Nov 30 10:01:51 2009
+++ rtems/cpukit/score/cpu/avr/rtems/score/cpu.h Mon May 10 11:31:24 2010
@@ -24,7 +24,7 @@
#endif
#include <rtems/score/avr.h> /* pick up machine definitions */
-#include <avr/io.h>
+#include <avr/common.h>
#ifndef ASM
#include <rtems/score/types.h>
#endif
@@ -639,10 +639,10 @@
*/
#define _CPU_ISR_Disable( _isr_cookie ) \
- { \
- (_isr_cookie) = SREG; /* do something to prevent warnings */ \
- asm volatile ("cli"::); \
-}
+ do { \
+ (_isr_cookie) = SREG; \
+ asm volatile ("cli"::); \
+ } while (0)
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
@@ -655,10 +655,10 @@
*/
#define _CPU_ISR_Enable( _isr_cookie ) \
- { \
+ do { \
SREG = _isr_cookie; \
asm volatile ("sei"::); \
- }
+ } while (0)
/*
* This temporarily restores the interrupt to _level before immediately
@@ -672,12 +672,12 @@
*/
#define _CPU_ISR_Flash( _isr_cookie ) \
- { \
+ do { \
SREG=(_isr_cookie); \
asm volatile("sei"::); \
(_isr_cookie) = SREG; \
asm volatile("cli"::); \
- }
+ } while (0)
/*
* Map interrupt level in task mode onto the hardware that the CPU
--
Generated by Deluxe Loginfo [http://www.codewiz.org/projects/index.html#loginfo] 2.122 by Bernardo Innocenti <bernie at develer.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/vc/attachments/20100510/cc8c138d/attachment-0001.html>
More information about the vc
mailing list