change log for rtems (2011-02-11)
rtems-vc at rtems.org
rtems-vc at rtems.org
Fri Feb 11 10:11:16 UTC 2011
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* avr/power.h: Revert previous patch.
M 1.56 cpukit/score/cpu/avr/ChangeLog
M 1.5 cpukit/score/cpu/avr/avr/power.h
diff -u rtems/cpukit/score/cpu/avr/ChangeLog:1.55 rtems/cpukit/score/cpu/avr/ChangeLog:1.56
--- rtems/cpukit/score/cpu/avr/ChangeLog:1.55 Fri Feb 11 03:09:21 2011
+++ rtems/cpukit/score/cpu/avr/ChangeLog Fri Feb 11 03:11:00 2011
@@ -1,5 +1,9 @@
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+ * avr/power.h: Revert previous patch.
+
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
* cpu.c, avr/interrupt.h, avr/power.h, rtems/score/cpu.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
diff -u rtems/cpukit/score/cpu/avr/avr/power.h:1.4 rtems/cpukit/score/cpu/avr/avr/power.h:1.5
--- rtems/cpukit/score/cpu/avr/avr/power.h:1.4 Fri Feb 11 03:09:21 2011
+++ rtems/cpukit/score/cpu/avr/avr/power.h Fri Feb 11 03:11:00 2011
@@ -1377,7 +1377,7 @@
} clock_div_t;
-static inline void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
+static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__));
/** \addtogroup avr_power
\code clock_prescale_set(x) \endcode
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* rtems/score/cpu.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.42 cpukit/score/cpu/bfin/ChangeLog
M 1.25 cpukit/score/cpu/bfin/rtems/score/cpu.h
diff -u rtems/cpukit/score/cpu/bfin/ChangeLog:1.41 rtems/cpukit/score/cpu/bfin/ChangeLog:1.42
--- rtems/cpukit/score/cpu/bfin/ChangeLog:1.41 Thu Oct 21 17:11:52 2010
+++ rtems/cpukit/score/cpu/bfin/ChangeLog Fri Feb 11 03:11:56 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * rtems/score/cpu.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-10-21 Joel Sherrill <joel.sherrill at oarcorp.com>
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
diff -u rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h:1.24 rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h:1.25
--- rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h:1.24 Thu Oct 21 17:11:52 2010
+++ rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h Fri Feb 11 03:11:57 2011
@@ -710,7 +710,7 @@
*/
#define _CPU_ISR_Disable( _level ) \
{ \
- asm volatile ("cli %0; csync \n" : "=d" (_level) ); \
+ __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \
}
@@ -910,7 +910,7 @@
*/
#define _CPU_Fatal_halt( _error ) \
{ \
- asm volatile ( "cli R1; \
+ __asm__ volatile ( "cli R1; \
R1 = %0; \
_halt: \
idle; \
@@ -1015,7 +1015,7 @@
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
- asm ("bit(1);"):
+ __asm__ ("bit(1);"):
(_output) = 0; /* do something to prevent warnings */ \
}
#endif
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* cpu.c, rtems/asm.h, rtems/score/cpu.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.100 cpukit/score/cpu/h8300/ChangeLog
M 1.12 cpukit/score/cpu/h8300/cpu.c
M 1.10 cpukit/score/cpu/h8300/rtems/asm.h
M 1.45 cpukit/score/cpu/h8300/rtems/score/cpu.h
diff -u rtems/cpukit/score/cpu/h8300/ChangeLog:1.99 rtems/cpukit/score/cpu/h8300/ChangeLog:1.100
--- rtems/cpukit/score/cpu/h8300/ChangeLog:1.99 Thu Oct 21 17:12:08 2010
+++ rtems/cpukit/score/cpu/h8300/ChangeLog Fri Feb 11 03:13:08 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * cpu.c, rtems/asm.h, rtems/score/cpu.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-10-21 Joel Sherrill <joel.sherrill at oarcorp.com>
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
diff -u rtems/cpukit/score/cpu/h8300/cpu.c:1.11 rtems/cpukit/score/cpu/h8300/cpu.c:1.12
--- rtems/cpukit/score/cpu/h8300/cpu.c:1.11 Sat Mar 27 10:01:35 2010
+++ rtems/cpukit/score/cpu/h8300/cpu.c Fri Feb 11 03:13:08 2011
@@ -53,7 +53,7 @@
#if defined(__H8300__)
#warning "How do we get ccr on base CPU models"
#else
- asm volatile ( "stc ccr, %0" : "=m" (_ccr) : );
+ __asm__ volatile ( "stc ccr, %0" : "=m" (_ccr) : );
#endif
if ( _ccr & 0x80 )
@@ -152,7 +152,7 @@
for( ; ; )
IDLE_Monitor();
- /*asm(" sleep \n"); */
+ /* __asm__ (" sleep \n"); */
/* insert your "halt" instruction here */ ;
}
#endif
diff -u rtems/cpukit/score/cpu/h8300/rtems/asm.h:1.9 rtems/cpukit/score/cpu/h8300/rtems/asm.h:1.10
--- rtems/cpukit/score/cpu/h8300/rtems/asm.h:1.9 Mon Jun 28 19:31:09 2010
+++ rtems/cpukit/score/cpu/h8300/rtems/asm.h Fri Feb 11 03:13:08 2011
@@ -98,7 +98,7 @@
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
-#define BEGIN_CODE asm ( ".text
+#define BEGIN_CODE __asm__ ( ".text
#define END_CODE ");
#define BEGIN_DATA
#define END_DATA
diff -u rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h:1.44 rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h:1.45
--- rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h:1.44 Thu Oct 21 17:12:09 2010
+++ rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h Fri Feb 11 03:13:08 2011
@@ -583,7 +583,7 @@
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
- asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \
+ __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \
} while (0)
@@ -596,7 +596,7 @@
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
- asm volatile( "mov.w %0, at -er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \
+ __asm__ volatile( "mov.w %0, at -er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \
} while (0)
@@ -610,7 +610,7 @@
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
- asm volatile( "mov.w %0, at -er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \
+ __asm__ volatile( "mov.w %0, at -er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \
} while (0)
/* end of ISR handler macros */
@@ -630,7 +630,7 @@
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
unsigned char __ccr; \
- asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \
+ __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \
: "=m" (__ccr) /* : "0" (__ccr) */ ); \
(_isr_cookie) = __ccr; \
} while (0)
@@ -653,7 +653,7 @@
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
- asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
+ __asm__ volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Enable( _isr_cookie )
@@ -674,7 +674,7 @@
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
- asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
+ __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Flash( _isr_cookie )
@@ -700,8 +700,8 @@
#define _CPU_ISR_Set_level( _new_level ) \
{ \
- if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \
- else asm volatile ( "andc #0x7f,ccr\n" ); \
+ if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \
+ else __asm__ volatile ( "andc #0x7f,ccr\n" ); \
}
#ifndef ASM
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* cpu.c, sse_test.c, rtems/score/cpu.h, rtems/score/i386.h,
rtems/score/interrupts.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.103 cpukit/score/cpu/i386/ChangeLog
M 1.47 cpukit/score/cpu/i386/cpu.c
M 1.37 cpukit/score/cpu/i386/rtems/score/cpu.h
M 1.18 cpukit/score/cpu/i386/rtems/score/i386.h
M 1.7 cpukit/score/cpu/i386/rtems/score/interrupts.h
M 1.4 cpukit/score/cpu/i386/sse_test.c
diff -u rtems/cpukit/score/cpu/i386/ChangeLog:1.102 rtems/cpukit/score/cpu/i386/ChangeLog:1.103
--- rtems/cpukit/score/cpu/i386/ChangeLog:1.102 Thu Jul 29 12:51:38 2010
+++ rtems/cpukit/score/cpu/i386/ChangeLog Fri Feb 11 03:14:20 2011
@@ -1,3 +1,9 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * cpu.c, sse_test.c, rtems/score/cpu.h, rtems/score/i386.h,
+ rtems/score/interrupts.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-07-29 Gedare Bloom <giddyup44 at yahoo.com>
PR 1635/cpukit
diff -u rtems/cpukit/score/cpu/i386/cpu.c:1.46 rtems/cpukit/score/cpu/i386/cpu.c:1.47
--- rtems/cpukit/score/cpu/i386/cpu.c:1.46 Sat Mar 27 10:01:47 2010
+++ rtems/cpukit/score/cpu/i386/cpu.c Fri Feb 11 03:14:20 2011
@@ -35,7 +35,7 @@
void _CPU_Initialize(void)
{
#if CPU_HARDWARE_FP
- register uint16_t fp_status asm ("ax");
+ register uint16_t fp_status __asm__ ("ax");
register Context_Control_fp *fp_context;
#endif
@@ -53,8 +53,8 @@
#if CPU_HARDWARE_FP
fp_status = 0xa5a5;
- asm volatile( "fninit" );
- asm volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
+ __asm__ volatile( "fninit" );
+ __asm__ volatile( "fnstsw %0" : "=a" (fp_status) : "0" (fp_status) );
if ( fp_status == 0 ) {
@@ -63,7 +63,7 @@
#ifdef __SSE__
asm volatile( "fstcw %0":"=m"(fp_context->fpucw) );
#else
- asm volatile( "fsave (%0)" : "=r" (fp_context)
+ __asm__ volatile( "fsave (%0)" : "=r" (fp_context)
: "0" (fp_context)
);
#endif
@@ -72,7 +72,7 @@
#ifdef __SSE__
- asm volatile("stmxcsr %0":"=m"(fp_context->mxcsr));
+ __asm__ volatile("stmxcsr %0":"=m"(fp_context->mxcsr));
/* The BSP must enable the SSE extensions (early).
* If any SSE instruction was already attempted
@@ -111,7 +111,7 @@
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
while(1){
- asm volatile ("hlt");
+ __asm__ volatile ("hlt");
}
return NULL;
}
diff -u rtems/cpukit/score/cpu/i386/rtems/score/cpu.h:1.36 rtems/cpukit/score/cpu/i386/rtems/score/cpu.h:1.37
--- rtems/cpukit/score/cpu/i386/rtems/score/cpu.h:1.36 Fri Jul 16 03:38:35 2010
+++ rtems/cpukit/score/cpu/i386/rtems/score/cpu.h Fri Feb 11 03:14:20 2011
@@ -354,8 +354,8 @@
#define _CPU_ISR_Set_level( _new_level ) \
{ \
- if ( _new_level ) asm volatile ( "cli" ); \
- else asm volatile ( "sti" ); \
+ if ( _new_level ) __asm__ volatile ( "cli" ); \
+ else __asm__ volatile ( "sti" ); \
}
uint32_t _CPU_ISR_Get_level( void );
@@ -456,7 +456,7 @@
#define _CPU_Fatal_halt( _error ) \
{ \
- asm volatile ( "cli ; \
+ __asm__ volatile ( "cli ; \
movl %0,%%eax ; \
hlt" \
: "=r" ((_error)) : "0" ((_error)) \
@@ -483,7 +483,7 @@
\
_output = 0; \
\
- asm volatile ( "bsfw %0,%1 " \
+ __asm__ volatile ( "bsfw %0,%1 " \
: "=r" (__value_in_register), "=r" (_output) \
: "0" (__value_in_register), "1" (_output) \
); \
diff -u rtems/cpukit/score/cpu/i386/rtems/score/i386.h:1.17 rtems/cpukit/score/cpu/i386/rtems/score/i386.h:1.18
--- rtems/cpukit/score/cpu/i386/rtems/score/i386.h:1.17 Sat Aug 16 00:46:28 2008
+++ rtems/cpukit/score/cpu/i386/rtems/score/i386.h Fri Feb 11 03:14:20 2011
@@ -125,7 +125,7 @@
uint32_t lout;
#if (I386_HAS_BSWAP == 0)
- asm volatile( "rorw $8,%%ax;"
+ __asm__ volatile( "rorw $8,%%ax;"
"rorl $16,%0;"
"rorw $8,%%ax" : "=a" (lout) : "0" (value) );
#else
@@ -153,21 +153,21 @@
{
register unsigned int segment = 0;
- asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
static inline void i386_set_cr0(unsigned int segment)
{
- asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
}
static inline unsigned int i386_get_cr2(void)
{
register unsigned int segment = 0;
- asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
@@ -176,14 +176,14 @@
{
register unsigned int segment = 0;
- asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
static inline void i386_set_cr3(unsigned int segment)
{
- asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
}
/* routines */
diff -u rtems/cpukit/score/cpu/i386/rtems/score/interrupts.h:1.6 rtems/cpukit/score/cpu/i386/rtems/score/interrupts.h:1.7
--- rtems/cpukit/score/cpu/i386/rtems/score/interrupts.h:1.6 Fri Jan 28 09:56:09 2005
+++ rtems/cpukit/score/cpu/i386/rtems/score/interrupts.h Fri Feb 11 03:14:20 2011
@@ -36,7 +36,7 @@
#define i386_disable_interrupts( _level ) \
{ \
- asm volatile ( "pushf ; \
+ __asm__ volatile ( "pushf ; \
cli ; \
pop %0" \
: "=rm" ((_level)) \
@@ -45,7 +45,7 @@
#define i386_enable_interrupts( _level ) \
{ \
- asm volatile ( "push %0 ; \
+ __asm__ volatile ( "push %0 ; \
popf" \
: : "rm" ((_level)) : "cc" \
); \
@@ -53,7 +53,7 @@
#define i386_flash_interrupts( _level ) \
{ \
- asm volatile ( "push %0 ; \
+ __asm__ volatile ( "push %0 ; \
popf ; \
cli" \
: : "rm" ((_level)) : "cc" \
@@ -64,7 +64,7 @@
do { \
register uint32_t _eflags; \
\
- asm volatile ( "pushf ; \
+ __asm__ volatile ( "pushf ; \
pop %0" \
: "=rm" ((_eflags)) \
); \
diff -u rtems/cpukit/score/cpu/i386/sse_test.c:1.3 rtems/cpukit/score/cpu/i386/sse_test.c:1.4
--- rtems/cpukit/score/cpu/i386/sse_test.c:1.3 Sat Mar 27 10:01:47 2010
+++ rtems/cpukit/score/cpu/i386/sse_test.c Fri Feb 11 03:14:20 2011
@@ -255,7 +255,7 @@
void
all_clobber(uint32_t v1, uint32_t v2);
-asm(
+__asm__ (
"all_clobber: \n"
" finit \n"
" movq 0(%esp), %xmm0 \n"
@@ -275,7 +275,7 @@
void
init_ctxt(Context_Control_sse *p_ctxt);
-asm(
+__asm__ (
"init_ctxt: \n"
" finit \n"
" mov 4(%esp), %eax\n"
@@ -398,7 +398,7 @@
#define __INTRAISE(x) " int $32+"#x" \n"
#define INTRAISE(x) __INTRAISE(x)
-asm(
+__asm__ (
"do_raise: \n"
" fwait \n"
" test %eax, %eax \n"
@@ -834,7 +834,7 @@
#define MKCASE(X) case FPE_##X: msg="FPE_"#X; break;
-#define CLRXMM(i) asm volatile("pxor %%xmm"#i", %%xmm"#i:::"xmm"#i)
+#define CLRXMM(i) __asm__ volatile("pxor %%xmm"#i", %%xmm"#i:::"xmm"#i)
static void
fpe_act(int signum, siginfo_t *p_info, void *arg3)
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* context_init.c, cpu.c, varvects.h, rtems/score/cpu.h,
rtems/score/m32c.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.17 cpukit/score/cpu/m32c/ChangeLog
M 1.7 cpukit/score/cpu/m32c/context_init.c
M 1.9 cpukit/score/cpu/m32c/cpu.c
M 1.12 cpukit/score/cpu/m32c/rtems/score/cpu.h
M 1.3 cpukit/score/cpu/m32c/rtems/score/m32c.h
M 1.4 cpukit/score/cpu/m32c/varvects.h
diff -u rtems/cpukit/score/cpu/m32c/ChangeLog:1.16 rtems/cpukit/score/cpu/m32c/ChangeLog:1.17
--- rtems/cpukit/score/cpu/m32c/ChangeLog:1.16 Thu Oct 21 17:12:51 2010
+++ rtems/cpukit/score/cpu/m32c/ChangeLog Fri Feb 11 03:20:50 2011
@@ -1,3 +1,9 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * context_init.c, cpu.c, varvects.h, rtems/score/cpu.h,
+ rtems/score/m32c.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-10-21 Joel Sherrill <joel.sherrill at oarcorp.com>
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
diff -u rtems/cpukit/score/cpu/m32c/context_init.c:1.6 rtems/cpukit/score/cpu/m32c/context_init.c:1.7
--- rtems/cpukit/score/cpu/m32c/context_init.c:1.6 Mon May 10 15:08:50 2010
+++ rtems/cpukit/score/cpu/m32c/context_init.c Fri Feb 11 03:20:50 2011
@@ -36,7 +36,7 @@
#define _get_sb( _sb )
#else
#define _get_sb( _sb ) \
- asm volatile( "stc sb, %0" : "=r" (_sb))
+ __asm__ volatile( "stc sb, %0" : "=r" (_sb))
#endif
void _CPU_Context_Initialize(
diff -u rtems/cpukit/score/cpu/m32c/cpu.c:1.8 rtems/cpukit/score/cpu/m32c/cpu.c:1.9
--- rtems/cpukit/score/cpu/m32c/cpu.c:1.8 Mon May 10 15:08:50 2010
+++ rtems/cpukit/score/cpu/m32c/cpu.c Fri Feb 11 03:20:50 2011
@@ -33,7 +33,7 @@
void _CPU_Initialize(void)
{
#if !defined(__r8c_cpu__)
- asm volatile( "ldc #__var_vects,intb" );
+ __asm__ volatile( "ldc #__var_vects,intb" );
#endif
}
diff -u rtems/cpukit/score/cpu/m32c/rtems/score/cpu.h:1.11 rtems/cpukit/score/cpu/m32c/rtems/score/cpu.h:1.12
--- rtems/cpukit/score/cpu/m32c/rtems/score/cpu.h:1.11 Thu Oct 21 17:12:51 2010
+++ rtems/cpukit/score/cpu/m32c/rtems/score/cpu.h Fri Feb 11 03:20:50 2011
@@ -674,7 +674,7 @@
int _flg; \
m32c_get_flg( _flg ); \
_isr_cookie = _flg; \
- asm volatile( "fclr I" ); \
+ __asm__ volatile( "fclr I" ); \
} while(0)
/**
@@ -712,7 +712,7 @@
do { \
int _flg = (int) (_isr_cookie); \
m32c_set_flg( _flg ); \
- asm volatile( "fclr I" ); \
+ __asm__ volatile( "fclr I" ); \
} while(0)
/**
@@ -734,8 +734,8 @@
*/
#define _CPU_ISR_Set_level( _new_level ) \
do { \
- if (_new_level) asm volatile( "fclr I" ); \
- else asm volatile( "fset I" ); \
+ if (_new_level) __asm__ volatile( "fclr I" ); \
+ else __asm__ volatile( "fset I" ); \
} while(0)
/**
diff -u rtems/cpukit/score/cpu/m32c/rtems/score/m32c.h:1.2 rtems/cpukit/score/cpu/m32c/rtems/score/m32c.h:1.3
--- rtems/cpukit/score/cpu/m32c/rtems/score/m32c.h:1.2 Sun Nov 29 07:51:53 2009
+++ rtems/cpukit/score/cpu/m32c/rtems/score/m32c.h Fri Feb 11 03:20:50 2011
@@ -60,10 +60,10 @@
#define CPU_NAME "m32c"
#define m32c_get_flg( _flg ) \
- asm volatile( "stc flg, %0" : "=r" (_flg))
+ __asm__ volatile( "stc flg, %0" : "=r" (_flg))
#define m32c_set_flg( _flg ) \
- asm volatile( "ldc %1, flg" : "=r" (_flg) : "r" (_flg) )
+ __asm__ volatile( "ldc %1, flg" : "=r" (_flg) : "r" (_flg) )
#ifdef __cplusplus
}
diff -u rtems/cpukit/score/cpu/m32c/varvects.h:1.3 rtems/cpukit/score/cpu/m32c/varvects.h:1.4
--- rtems/cpukit/score/cpu/m32c/varvects.h:1.3 Sun Nov 29 07:51:53 2009
+++ rtems/cpukit/score/cpu/m32c/varvects.h Fri Feb 11 03:20:50 2011
@@ -42,8 +42,8 @@
#if defined(__r8c_cpu__) || defined (__m16c_cpu__)
#define _set_var_vect(f,n) \
- { asm ("mov.w #%%lo16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4)); \
- asm ("mov.w #%%hi16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4+2)); }
+ { __asm__ ("mov.w #%%lo16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4)); \
+ __asm__ ("mov.w #%%hi16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4+2)); }
#else
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* context_init.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.11 cpukit/score/cpu/m32r/ChangeLog
M 1.3 cpukit/score/cpu/m32r/context_init.c
diff -u rtems/cpukit/score/cpu/m32r/ChangeLog:1.10 rtems/cpukit/score/cpu/m32r/ChangeLog:1.11
--- rtems/cpukit/score/cpu/m32r/ChangeLog:1.10 Mon Jan 31 19:14:54 2011
+++ rtems/cpukit/score/cpu/m32r/ChangeLog Fri Feb 11 03:21:33 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * context_init.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-01-31 Joel Sherrill <joel.sherrill at oarcorp.com>
* context_switch.S: Reverse registers.
diff -u rtems/cpukit/score/cpu/m32r/context_init.c:1.2 rtems/cpukit/score/cpu/m32r/context_init.c:1.3
--- rtems/cpukit/score/cpu/m32r/context_init.c:1.2 Sat Mar 27 10:02:02 2010
+++ rtems/cpukit/score/cpu/m32r/context_init.c Fri Feb 11 03:21:33 2011
@@ -21,7 +21,7 @@
} Starting_Frame;
#define _get_r12( _r12 ) \
- asm volatile( "mv r12, %0" : "=r" (_r12))
+ __asm__ volatile( "mv r12, %0" : "=r" (_r12))
void _CPU_Context_Initialize(
Context_Control *the_context,
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* cpu.c, rtems/score/cpu.h, rtems/score/m68k.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.126 cpukit/score/cpu/m68k/ChangeLog
M 1.36 cpukit/score/cpu/m68k/cpu.c
M 1.45 cpukit/score/cpu/m68k/rtems/score/cpu.h
M 1.36 cpukit/score/cpu/m68k/rtems/score/m68k.h
diff -u rtems/cpukit/score/cpu/m68k/ChangeLog:1.125 rtems/cpukit/score/cpu/m68k/ChangeLog:1.126
--- rtems/cpukit/score/cpu/m68k/ChangeLog:1.125 Thu Jul 29 12:51:46 2010
+++ rtems/cpukit/score/cpu/m68k/ChangeLog Fri Feb 11 03:22:30 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * cpu.c, rtems/score/cpu.h, rtems/score/m68k.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-07-29 Gedare Bloom <giddyup44 at yahoo.com>
PR 1635/cpukit
diff -u rtems/cpukit/score/cpu/m68k/cpu.c:1.35 rtems/cpukit/score/cpu/m68k/cpu.c:1.36
--- rtems/cpukit/score/cpu/m68k/cpu.c:1.35 Sat Mar 27 10:02:07 2010
+++ rtems/cpukit/score/cpu/m68k/cpu.c Fri Feb 11 03:22:30 2011
@@ -156,7 +156,7 @@
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
void *isp = _CPU_Interrupt_stack_high;
- asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
+ __asm__ volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
#endif
}
diff -u rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h:1.44 rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h:1.45
--- rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h:1.44 Fri Jul 16 03:40:58 2010
+++ rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h Fri Feb 11 03:22:30 2011
@@ -485,7 +485,7 @@
#if ( defined(__mcoldfire__) )
#define _CPU_Fatal_halt( _error ) \
- { asm volatile( "move.w %%sr,%%d0\n\t" \
+ { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
"or.l %2,%%d0\n\t" \
"move.w %%d0,%%sr\n\t" \
"move.l %1,%%d0\n\t" \
@@ -497,7 +497,7 @@
}
#else
#define _CPU_Fatal_halt( _error ) \
- { asm volatile( "movl %0,%%d0; " \
+ { __asm__ volatile( "movl %0,%%d0; " \
"orw #0x0700,%%sr; " \
"stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
}
@@ -532,12 +532,12 @@
#if ( M68K_HAS_BFFFO == 1 )
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
+ __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
#elif ( __mcfisaaplus__ )
/* This is simplified by the fact that RTEMS never calls it with _value=0 */
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- asm volatile ( \
+ __asm__ volatile ( \
" swap %0\n" \
" ff1.l %0\n" \
: "=d" ((_output)) \
@@ -554,7 +554,7 @@
{ \
register int dumby; \
\
- asm volatile ( \
+ __asm__ volatile ( \
" clr.l %1\n" \
" move.w %2,%1\n" \
" lsr.l #8,%1\n" \
@@ -574,7 +574,7 @@
{ \
register int dumby; \
\
- asm volatile ( " move.w %2,%1\n" \
+ __asm__ volatile ( " move.w %2,%1\n" \
" lsr.w #8,%1\n" \
" beq.s 1f\n" \
" move.b (%3,%1.w),%0\n" \
@@ -592,7 +592,7 @@
{ \
register int dumby; \
\
- asm volatile ( " move.w %2,%1\n" \
+ __asm__ volatile ( " move.w %2,%1\n" \
" lsr.w #8,%1\n" \
" beq.s 1f\n" \
" move.b (%3,%1.w),%0\n" \
diff -u rtems/cpukit/score/cpu/m68k/rtems/score/m68k.h:1.35 rtems/cpukit/score/cpu/m68k/rtems/score/m68k.h:1.36
--- rtems/cpukit/score/cpu/m68k/rtems/score/m68k.h:1.35 Thu Dec 3 23:25:26 2009
+++ rtems/cpukit/score/cpu/m68k/rtems/score/m68k.h Fri Feb 11 03:22:30 2011
@@ -335,7 +335,7 @@
#if ( defined(__mcoldfire__) )
#define m68k_disable_interrupts( _level ) \
do { register uint32_t _tmpsr = 0x0700; \
- asm volatile ( "move.w %%sr,%0\n\t" \
+ __asm__ volatile ( "move.w %%sr,%0\n\t" \
"or.l %0,%1\n\t" \
"move.w %1,%%sr" \
: "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) \
@@ -343,14 +343,14 @@
} while( 0 )
#else
#define m68k_disable_interrupts( _level ) \
- asm volatile ( "move.w %%sr,%0\n\t" \
+ __asm__ volatile ( "move.w %%sr,%0\n\t" \
"or.w #0x0700,%%sr" \
: "=d" (_level) \
: : "cc" )
#endif
#define m68k_enable_interrupts( _level ) \
- asm volatile ( "move.w %0,%%sr " : : "d" (_level) : "cc");
+ __asm__ volatile ( "move.w %0,%%sr " : : "d" (_level) : "cc");
#if ( defined(__mcoldfire__) )
#define m68k_flash_interrupts( _level ) \
@@ -363,7 +363,7 @@
} while( 0 )
#else
#define m68k_flash_interrupts( _level ) \
- asm volatile ( "move.w %0,%%sr\n\t" \
+ __asm__ volatile ( "move.w %0,%%sr\n\t" \
"or.w #0x0700,%%sr" \
: : "d" (_level) \
: "cc" )
@@ -373,7 +373,7 @@
do { \
register uint32_t _tmpsr; \
\
- asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
+ __asm__ volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_level = (_tmpsr & 0x0700) >> 8; \
} while (0)
@@ -381,17 +381,17 @@
do { \
register uint32_t _tmpsr; \
\
- asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
+ __asm__ volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
- asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \
+ __asm__ volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \
} while (0)
#if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) )
#define m68k_get_vbr( vbr ) \
- asm volatile ( "movec %%vbr,%0 " : "=r" (vbr))
+ __asm__ volatile ( "movec %%vbr,%0 " : "=r" (vbr))
#define m68k_set_vbr( vbr ) \
- asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
+ __asm__ volatile ( "movec %0,%%vbr " : : "r" (vbr))
#elif ( defined(__mcoldfire__) )
extern void* _VBR;
@@ -399,7 +399,7 @@
#define m68k_set_vbr( _vbr ) \
do { \
- asm volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \
+ __asm__ volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \
_VBR = (void *)_vbr; \
} while(0)
@@ -411,9 +411,9 @@
/*
* Access Control Registers
*/
-#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
-#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
-#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
+#define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
+#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
+#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
/*
* The following routine swaps the endian format of an unsigned int.
@@ -454,9 +454,9 @@
{
uint32_t swapped = value;
- asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
- asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) );
- asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
+ __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
+ __asm__ volatile( "swap %0" : "=d" (swapped) : "0" (swapped) );
+ __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
return( swapped );
}
@@ -467,7 +467,7 @@
{
uint16_t swapped = value;
- asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
+ __asm__ volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
return( swapped );
}
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* irq.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.27 cpukit/score/cpu/nios2/ChangeLog
M 1.8 cpukit/score/cpu/nios2/irq.c
diff -u rtems/cpukit/score/cpu/nios2/ChangeLog:1.26 rtems/cpukit/score/cpu/nios2/ChangeLog:1.27
--- rtems/cpukit/score/cpu/nios2/ChangeLog:1.26 Thu Oct 21 17:14:01 2010
+++ rtems/cpukit/score/cpu/nios2/ChangeLog Fri Feb 11 03:23:20 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * irq.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-10-21 Joel Sherrill <joel.sherrill at oarcorp.com>
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
diff -u rtems/cpukit/score/cpu/nios2/irq.c:1.7 rtems/cpukit/score/cpu/nios2/irq.c:1.8
--- rtems/cpukit/score/cpu/nios2/irq.c:1.7 Fri Jul 30 13:52:14 2010
+++ rtems/cpukit/score/cpu/nios2/irq.c Fri Feb 11 03:23:20 2011
@@ -32,7 +32,7 @@
unsigned long *_old_stack_ptr;
#endif
-register unsigned long *stack_ptr asm("sp");
+register unsigned long *stack_ptr __asm__ ("sp");
void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
{
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* rtems/powerpc/registers.h, rtems/score/cpu.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.161 cpukit/score/cpu/powerpc/ChangeLog
M 1.35 cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
M 1.45 cpukit/score/cpu/powerpc/rtems/score/cpu.h
diff -u rtems/cpukit/score/cpu/powerpc/ChangeLog:1.160 rtems/cpukit/score/cpu/powerpc/ChangeLog:1.161
--- rtems/cpukit/score/cpu/powerpc/ChangeLog:1.160 Mon Jan 31 09:46:13 2011
+++ rtems/cpukit/score/cpu/powerpc/ChangeLog Fri Feb 11 03:24:09 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * rtems/powerpc/registers.h, rtems/score/cpu.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-01-31 Sebastian Huber <sebastian.huber at embedded-brains.de>
* rtems/powerpc/registers.h: Changed Freescale EIS prefix. More
diff -u rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.34 rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.35
--- rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h:1.34 Mon Jan 31 09:46:13 2011
+++ rtems/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h Fri Feb 11 03:24:09 2011
@@ -424,15 +424,15 @@
#define _CPU_MSR_GET( _msr_value ) \
do { \
_msr_value = 0; \
- asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
+ __asm__ volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
} while (0)
#define _CPU_MSR_SET( _msr_value ) \
-{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
+{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
static inline void ppc_interrupt_set_disable_mask( uint32_t mask )
{
- asm volatile (
+ __asm__ volatile (
"mtspr 272, %0"
:
: "r" (mask)
@@ -443,7 +443,7 @@
{
uint32_t mask;
- asm volatile (
+ __asm__ volatile (
"mfspr %0, 272"
: "=r" (mask)
);
@@ -456,7 +456,7 @@
uint32_t level;
uint32_t mask;
- asm volatile (
+ __asm__ volatile (
"mfmsr %0;"
"mfspr %1, 272;"
"andc %1, %0, %1;"
@@ -469,7 +469,7 @@
static inline void ppc_interrupt_enable( uint32_t level )
{
- asm volatile (
+ __asm__ volatile (
"mtmsr %0"
:
: "r" (level)
@@ -480,7 +480,7 @@
{
uint32_t current_level;
- asm volatile (
+ __asm__ volatile (
"mfmsr %0;"
"mtmsr %1;"
"mtmsr %0"
diff -u rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h:1.44 rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h:1.45
--- rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h:1.44 Thu Oct 21 17:14:44 2010
+++ rtems/cpukit/score/cpu/powerpc/rtems/score/cpu.h Fri Feb 11 03:24:09 2011
@@ -666,7 +666,7 @@
{
uint32_t swapped;
- asm volatile("rlwimi %0,%1,8,24,31;"
+ __asm__ volatile("rlwimi %0,%1,8,24,31;"
"rlwimi %0,%1,24,16,23;"
"rlwimi %0,%1,8,8,15;"
"rlwimi %0,%1,24,0,7;" :
@@ -817,7 +817,7 @@
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
- asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
+ __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
"1" ((_value))); \
}
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* rtems/score/cpu.h, rtems/score/sparc64.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.7 cpukit/score/cpu/sparc64/ChangeLog
M 1.5 cpukit/score/cpu/sparc64/rtems/score/cpu.h
M 1.3 cpukit/score/cpu/sparc64/rtems/score/sparc64.h
diff -u rtems/cpukit/score/cpu/sparc64/ChangeLog:1.6 rtems/cpukit/score/cpu/sparc64/ChangeLog:1.7
--- rtems/cpukit/score/cpu/sparc64/ChangeLog:1.6 Tue Nov 16 17:22:47 2010
+++ rtems/cpukit/score/cpu/sparc64/ChangeLog Fri Feb 11 03:25:21 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * rtems/score/cpu.h, rtems/score/sparc64.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-11-16 Gedare Bloom <giddyup44 at yahoo.com>
* rtems/score/sparc64.h: Fix typo.
diff -u rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h:1.4 rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h:1.5
--- rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h:1.4 Thu Oct 21 17:18:05 2010
+++ rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h Fri Feb 11 03:25:21 2011
@@ -844,7 +844,7 @@
#define _CPU_Context_Initialization_at_thread_begin() \
do { \
- asm volatile ("set _Thread_Handler,%%i7\n"::); \
+ __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
} while (0)
/*
@@ -896,7 +896,7 @@
uint32_t level; \
\
level = sparc_disable_interrupts(); \
- asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \
+ __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \
while (1); /* loop forever */ \
} while (0)
diff -u rtems/cpukit/score/cpu/sparc64/rtems/score/sparc64.h:1.2 rtems/cpukit/score/cpu/sparc64/rtems/score/sparc64.h:1.3
--- rtems/cpukit/score/cpu/sparc64/rtems/score/sparc64.h:1.2 Tue Nov 16 17:22:47 2010
+++ rtems/cpukit/score/cpu/sparc64/rtems/score/sparc64.h Fri Feb 11 03:25:21 2011
@@ -170,7 +170,7 @@
#define nop() \
do { \
- asm volatile ( "nop" ); \
+ __asm__ volatile ( "nop" ); \
} while ( 0 )
/*
@@ -180,12 +180,12 @@
#define sparc64_get_pstate( _pstate ) \
do { \
(_pstate) = 0; \
- asm volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \
+ __asm__ volatile( "rdpr %%pstate, %0" : "=r" (_pstate) : "0" (_pstate) ); \
} while ( 0 )
#define sparc64_set_pstate( _pstate ) \
do { \
- asm volatile ( \
+ __asm__ volatile ( \
"wrpr %%g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \
} while ( 0 )
@@ -196,12 +196,12 @@
#define sparc64_get_pil( _pil ) \
do { \
(_pil) = 0; \
- asm volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \
+ __asm__ volatile( "rdpr %%pil, %0" : "=r" (_pil) : "0" (_pil) ); \
} while ( 0 )
#define sparc64_set_pil( _pil ) \
do { \
- asm volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \
+ __asm__ volatile ( "wrpr %%g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \
} while ( 0 )
@@ -212,12 +212,12 @@
#define sparc64_get_tba( _tba ) \
do { \
(_tba) = 0; /* to avoid unitialized warnings */ \
- asm volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \
+ __asm__ volatile( "rdpr %%tba, %0" : "=r" (_tba) : "0" (_tba) ); \
} while ( 0 )
#define sparc64_set_tba( _tba ) \
do { \
- asm volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \
+ __asm__ volatile( "wrpr %%g0, %0, %%tba" : "=r" (_tba) : "0" (_tba) ); \
} while ( 0 )
/*
@@ -227,12 +227,12 @@
#define sparc64_get_tl( _tl ) \
do { \
(_tl) = 0; /* to avoid unitialized warnings */ \
- asm volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \
+ __asm__ volatile( "rdpr %%tl, %0" : "=r" (_tl) : "0" (_tl) ); \
} while ( 0 )
#define sparc64_set_tl( _tl ) \
do { \
- asm volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \
+ __asm__ volatile( "wrpr %%g0, %0, %%tl" : "=r" (_tl) : "0" (_tl) ); \
} while ( 0 )
@@ -247,7 +247,7 @@
#define sparc64_read_stick( _stick ) \
do { \
(_stick) = 0; \
- asm volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \
+ __asm__ volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) ); \
} while ( 0 )
/*
@@ -260,7 +260,7 @@
*/
#define sparc64_write_stick_cmpr( _stick_cmpr ) \
do { \
- asm volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \
+ __asm__ volatile( "wr %%g0, %0, %%stick_cmpr" : "=r" (_stick_cmpr) \
: "0" (_stick_cmpr) ); \
} while ( 0 )
@@ -270,7 +270,7 @@
#define sparc64_read_tick( _tick ) \
do { \
(_tick) = 0; \
- asm volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \
+ __asm__ volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \
} while ( 0 )
/*
@@ -278,7 +278,7 @@
*/
#define sparc64_write_tick_cmpr( _tick_cmpr ) \
do { \
- asm volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \
+ __asm__ volatile( "wr %%g0, %0, %%tick_cmpr" : "=r" (_tick_cmpr) \
: "0" (_tick_cmpr) ); \
} while ( 0 )
@@ -289,7 +289,7 @@
*/
#define sparc64_clear_interrupt_bits( _bit_mask ) \
do { \
- asm volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \
+ __asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \
: "0" (_bit_mask)); \
} while ( 0 )
@@ -301,12 +301,12 @@
#define sparc_get_y( _y ) \
do { \
- asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
+ __asm__ volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
#define sparc_set_y( _y ) \
do { \
- asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
+ __asm__ volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
/************* /DEPRECATED ****************/
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* score/include/rtems/score/basedefs.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.2707 cpukit/ChangeLog
M 1.2 cpukit/score/include/rtems/score/basedefs.h
diff -u rtems/cpukit/ChangeLog:1.2706 rtems/cpukit/ChangeLog:1.2707
--- rtems/cpukit/ChangeLog:1.2706 Thu Feb 10 18:05:29 2011
+++ rtems/cpukit/ChangeLog Fri Feb 11 03:27:03 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * score/include/rtems/score/basedefs.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-10 Ralf Corsépius <ralf.corsepius at rtems.org>
* libblock/include/rtems/bdpart.h (rtems_bdpart_format):
diff -u rtems/cpukit/score/include/rtems/score/basedefs.h:1.1 rtems/cpukit/score/include/rtems/score/basedefs.h:1.2
--- rtems/cpukit/score/include/rtems/score/basedefs.h:1.1 Fri Jul 16 03:31:33 2010
+++ rtems/cpukit/score/include/rtems/score/basedefs.h Fri Feb 11 03:27:03 2011
@@ -116,7 +116,7 @@
* impact interrupt disable and thread dispatching critical sections.
*/
#ifdef __GNUC__
- #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory")
+ #define RTEMS_COMPILER_MEMORY_BARRIER() __asm__ volatile("" ::: "memory")
#else
#define RTEMS_COMPILER_MEMORY_BARRIER()
#endif
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* pxa255/pmc/pmc.c, shared/include/arm-cp15.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.78 c/src/lib/libcpu/arm/ChangeLog
M 1.3 c/src/lib/libcpu/arm/pxa255/pmc/pmc.c
M 1.3 c/src/lib/libcpu/arm/shared/include/arm-cp15.h
diff -u rtems/c/src/lib/libcpu/arm/ChangeLog:1.77 rtems/c/src/lib/libcpu/arm/ChangeLog:1.78
--- rtems/c/src/lib/libcpu/arm/ChangeLog:1.77 Wed Feb 2 09:00:49 2011
+++ rtems/c/src/lib/libcpu/arm/ChangeLog Fri Feb 11 03:32:25 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * pxa255/pmc/pmc.c, shared/include/arm-cp15.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/arm/pxa255/pmc/pmc.c:1.2 rtems/c/src/lib/libcpu/arm/pxa255/pmc/pmc.c:1.3
--- rtems/c/src/lib/libcpu/arm/pxa255/pmc/pmc.c:1.2 Fri Jul 10 10:34:12 2009
+++ rtems/c/src/lib/libcpu/arm/pxa255/pmc/pmc.c Fri Feb 11 03:32:25 2011
@@ -17,31 +17,31 @@
unsigned int val = 0;
switch(reg){
case PMC_PMNC:
- asm volatile("mrc p14,0,%0,c0,c1,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c0,c1,0\n":"=r"(val):);
break;
case PMC_CCNT:
- asm volatile("mrc p14,0,%0,c1,c1,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c1,c1,0\n":"=r"(val):);
break;
case PMC_INTEN:
- asm volatile("mrc p14,0,%0,c4,c1,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c4,c1,0\n":"=r"(val):);
break;
case PMC_FLAG:
- asm volatile("mrc p14,0,%0,c5,c1,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c5,c1,0\n":"=r"(val):);
break;
case PMC_EVTSEL:
- asm volatile("mrc p14,0,%0,c8,c1,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c8,c1,0\n":"=r"(val):);
break;
case PMC_PMN0:
- asm volatile("mrc p14,0,%0,c0,c2,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c0,c2,0\n":"=r"(val):);
break;
case PMC_PMN1:
- asm volatile("mrc p14,0,%0,c1,c2,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c1,c2,0\n":"=r"(val):);
break;
case PMC_PMN2:
- asm volatile("mrc p14,0,%0,c2,c2,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c2,c2,0\n":"=r"(val):);
break;
case PMC_PMN3:
- asm volatile("mrc p14,0,%0,c3,c2,0\n":"=r"(val):);
+ __asm__ volatile("mrc p14,0,%0,c3,c2,0\n":"=r"(val):);
break;
default:
val = 0;
@@ -54,31 +54,31 @@
{
switch(reg){
case PMC_PMNC:
- asm volatile("mcr p14,0,%0,c0,c1,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c0,c1,0\n"::"r"(val));
break;
case PMC_CCNT:
- asm volatile("mcr p14,0,%0,c1,c1,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c1,c1,0\n"::"r"(val));
break;
case PMC_INTEN:
- asm volatile("mcr p14,0,%0,c4,c1,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c4,c1,0\n"::"r"(val));
break;
case PMC_FLAG:
- asm volatile("mcr p14,0,%0,c5,c1,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c5,c1,0\n"::"r"(val));
break;
case PMC_EVTSEL:
- asm volatile("mcr p14,0,%0,c8,c1,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c8,c1,0\n"::"r"(val));
break;
case PMC_PMN0:
- asm volatile("mcr p14,0,%0,c0,c2,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c0,c2,0\n"::"r"(val));
break;
case PMC_PMN1:
- asm volatile("mcr p14,0,%0,c1,c2,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c1,c2,0\n"::"r"(val));
break;
case PMC_PMN2:
- asm volatile("mcr p14,0,%0,c2,c2,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c2,c2,0\n"::"r"(val));
break;
case PMC_PMN3:
- asm volatile("mcr p14,0,%0,c3,c2,0\n"::"r"(val));
+ __asm__ volatile("mcr p14,0,%0,c3,c2,0\n"::"r"(val));
break;
default:
break;
diff -u rtems/c/src/lib/libcpu/arm/shared/include/arm-cp15.h:1.2 rtems/c/src/lib/libcpu/arm/shared/include/arm-cp15.h:1.3
--- rtems/c/src/lib/libcpu/arm/shared/include/arm-cp15.h:1.2 Fri Apr 9 07:30:39 2010
+++ rtems/c/src/lib/libcpu/arm/shared/include/arm-cp15.h Fri Feb 11 03:32:25 2011
@@ -109,7 +109,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c0, c0, 0\n"
ARM_SWITCH_BACK
@@ -124,7 +124,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c0, c0, 2\n"
ARM_SWITCH_BACK
@@ -139,7 +139,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c1, c0, 0\n"
ARM_SWITCH_BACK
@@ -153,7 +153,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[val], c1, c0, 0\n"
"nop\n"
@@ -176,7 +176,7 @@
ARM_SWITCH_REGISTERS;
uint32_t *base;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[base], c2, c0, 0\n"
ARM_SWITCH_BACK
@@ -190,7 +190,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[base], c2, c0, 0\n"
ARM_SWITCH_BACK
@@ -204,7 +204,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c3, c0, 0\n"
ARM_SWITCH_BACK
@@ -218,7 +218,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[val], c3, c0, 0\n"
ARM_SWITCH_BACK
@@ -232,7 +232,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c5, c0, 0\n"
ARM_SWITCH_BACK
@@ -246,7 +246,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[val], c5, c0, 0\n"
ARM_SWITCH_BACK
@@ -260,7 +260,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c5, c0, 1\n"
ARM_SWITCH_BACK
@@ -274,7 +274,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[val], c5, c0, 1\n"
ARM_SWITCH_BACK
@@ -288,7 +288,7 @@
ARM_SWITCH_REGISTERS;
void *mva;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[mva], c6, c0, 0\n"
ARM_SWITCH_BACK
@@ -302,7 +302,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c6, c0, 0\n"
ARM_SWITCH_BACK
@@ -316,7 +316,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c8, c7, 0\n"
ARM_SWITCH_BACK
@@ -331,7 +331,7 @@
mva = ARM_CP15_TLB_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c8, c7, 1\n"
ARM_SWITCH_BACK
@@ -345,7 +345,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c8, c5, 0\n"
ARM_SWITCH_BACK
@@ -360,7 +360,7 @@
mva = ARM_CP15_TLB_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c8, c5, 1\n"
ARM_SWITCH_BACK
@@ -374,7 +374,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c8, c6, 0\n"
ARM_SWITCH_BACK
@@ -389,7 +389,7 @@
mva = ARM_CP15_TLB_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c8, c6, 1\n"
ARM_SWITCH_BACK
@@ -402,7 +402,7 @@
{
uint32_t arm_switch_reg;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"add %[arm_switch_reg], pc, #16\n"
"mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n"
@@ -433,7 +433,7 @@
ARM_SWITCH_REGISTERS;
uint32_t val;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mrc p15, 0, %[val], c0, c0, 1\n"
ARM_SWITCH_BACK
@@ -448,7 +448,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c7, c7, 0\n"
ARM_SWITCH_BACK
@@ -463,7 +463,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c7, c5, 0\n"
ARM_SWITCH_BACK
@@ -479,7 +479,7 @@
mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c7, c5, 1\n"
ARM_SWITCH_BACK
@@ -493,7 +493,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[set_and_way], c7, c5, 2\n"
ARM_SWITCH_BACK
@@ -509,7 +509,7 @@
mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c7, c13, 1\n"
ARM_SWITCH_BACK
@@ -523,7 +523,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c7, c6, 0\n"
ARM_SWITCH_BACK
@@ -539,7 +539,7 @@
mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c7, c6, 1\n"
ARM_SWITCH_BACK
@@ -553,7 +553,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[set_and_way], c7, c6, 2\n"
ARM_SWITCH_BACK
@@ -569,7 +569,7 @@
mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c7, c10, 1\n"
ARM_SWITCH_BACK
@@ -583,7 +583,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[set_and_way], c7, c10, 2\n"
ARM_SWITCH_BACK
@@ -597,7 +597,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"1:\n"
"mrc p15, 0, r15, c7, c10, 3\n"
@@ -615,7 +615,7 @@
mva = ARM_CP15_CACHE_PREPARE_MVA(mva);
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c7, c14, 1\n"
ARM_SWITCH_BACK
@@ -629,7 +629,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[set_and_way], c7, c14, 2\n"
ARM_SWITCH_BACK
@@ -643,7 +643,7 @@
{
ARM_SWITCH_REGISTERS;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"1:\n"
"mrc p15, 0, r15, c7, c14, 3\n"
@@ -662,7 +662,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c7, c10, 4\n"
ARM_SWITCH_BACK
@@ -677,7 +677,7 @@
ARM_SWITCH_REGISTERS;
uint32_t sbz = 0;
- asm volatile (
+ __asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[sbz], c7, c0, 4\n"
ARM_SWITCH_BACK
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* timer/timer.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.16 c/src/lib/libcpu/bfin/ChangeLog
M 1.6 c/src/lib/libcpu/bfin/timer/timer.c
diff -u rtems/c/src/lib/libcpu/bfin/ChangeLog:1.15 rtems/c/src/lib/libcpu/bfin/ChangeLog:1.16
--- rtems/c/src/lib/libcpu/bfin/ChangeLog:1.15 Wed Feb 2 09:00:51 2011
+++ rtems/c/src/lib/libcpu/bfin/ChangeLog Fri Feb 11 03:33:06 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * timer/timer.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/bfin/timer/timer.c:1.5 rtems/c/src/lib/libcpu/bfin/timer/timer.c:1.6
--- rtems/c/src/lib/libcpu/bfin/timer/timer.c:1.5 Sun Nov 29 23:03:49 2009
+++ rtems/c/src/lib/libcpu/bfin/timer/timer.c Fri Feb 11 03:33:06 2011
@@ -33,13 +33,13 @@
{
/*reset counters*/
- asm ("R2 = 0;");
- asm ("CYCLES = R2;");
- asm ("CYCLES2 = R2;");
+ __asm__ ("R2 = 0;");
+ __asm__ ("CYCLES = R2;");
+ __asm__ ("CYCLES2 = R2;");
/*start counters*/
- asm ("R2 = SYSCFG;");
- asm ("BITSET(R2,1);");
- asm ("SYSCFG = R2");
+ __asm__ ("R2 = SYSCFG;");
+ __asm__ ("BITSET(R2,1);");
+ __asm__ ("SYSCFG = R2");
}
@@ -62,13 +62,13 @@
{
uint32_t clicks;
uint32_t total;
- register uint32_t cycles asm ("R2");
+ register uint32_t cycles __asm__ ("R2");
/* stop counter */
- asm("R2 = SYSCFG;");
- asm("BITCLR(R2,1);");
- asm("SYSCFG = R2;");
- asm("R2 = CYCLES;");
+ __asm__ ("R2 = SYSCFG;");
+ __asm__ ("BITCLR(R2,1);");
+ __asm__ ("SYSCFG = R2;");
+ __asm__ ("R2 = CYCLES;");
clicks = cycles; /* Clock cycles */
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* cache.c, cpu.h, cpuModel.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.69 c/src/lib/libcpu/i386/ChangeLog
M 1.8 c/src/lib/libcpu/i386/cache.c
M 1.16 c/src/lib/libcpu/i386/cpu.h
M 1.9 c/src/lib/libcpu/i386/cpuModel.h
diff -u rtems/c/src/lib/libcpu/i386/ChangeLog:1.68 rtems/c/src/lib/libcpu/i386/ChangeLog:1.69
--- rtems/c/src/lib/libcpu/i386/ChangeLog:1.68 Wed Feb 2 09:00:52 2011
+++ rtems/c/src/lib/libcpu/i386/ChangeLog Fri Feb 11 03:33:50 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * cache.c, cpu.h, cpuModel.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/i386/cache.c:1.7 rtems/c/src/lib/libcpu/i386/cache.c:1.8
--- rtems/c/src/lib/libcpu/i386/cache.c:1.7 Fri May 21 14:03:21 2010
+++ rtems/c/src/lib/libcpu/i386/cache.c Fri Feb 11 03:33:50 2011
@@ -53,11 +53,11 @@
void _CPU_cache_flush_entire_data(void)
{
- asm volatile ("wbinvd");
+ __asm__ volatile ("wbinvd");
}
void _CPU_cache_invalidate_entire_data(void)
{
- asm volatile ("invd");
+ __asm__ volatile ("invd");
}
void _CPU_cache_enable_data(void)
@@ -72,7 +72,7 @@
void _CPU_cache_invalidate_entire_instruction(void)
{
- asm volatile ("invd");
+ __asm__ volatile ("invd");
}
void _CPU_cache_enable_instruction(void)
diff -u rtems/c/src/lib/libcpu/i386/cpu.h:1.15 rtems/c/src/lib/libcpu/i386/cpu.h:1.16
--- rtems/c/src/lib/libcpu/i386/cpu.h:1.15 Fri Jan 28 14:38:09 2011
+++ rtems/c/src/lib/libcpu/i386/cpu.h Fri Feb 11 03:33:50 2011
@@ -37,56 +37,56 @@
* "macro" implementation of the generic code is used.
*/
-static inline unsigned short i386_get_cs()
+static __inline__ unsigned short i386_get_cs(void)
{
register unsigned short segment = 0;
- asm volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movw %%cs,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
-static inline unsigned short i386_get_ds()
+static __inline__ unsigned short i386_get_ds(void)
{
register unsigned short segment = 0;
- asm volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movw %%ds,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
-static inline unsigned short i386_get_es()
+static __inline__ unsigned short i386_get_es(void)
{
register unsigned short segment = 0;
- asm volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movw %%es,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
-static inline unsigned short i386_get_ss()
+static __inline__ unsigned short i386_get_ss(void)
{
register unsigned short segment = 0;
- asm volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movw %%ss,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
-static inline unsigned short i386_get_fs()
+static __inline__ unsigned short i386_get_fs(void)
{
register unsigned short segment = 0;
- asm volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movw %%fs,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
-static inline unsigned short i386_get_gs()
+static __inline__ unsigned short i386_get_gs(void)
{
register unsigned short segment = 0;
- asm volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) );
+ __asm__ volatile ( "movw %%gs,%0" : "=r" (segment) : "0" (segment) );
return segment;
}
@@ -99,28 +99,28 @@
do { register unsigned short __port = _port; \
register unsigned char __value = _value; \
\
- asm volatile ( "outb %0,%1" : : "a" (__value), "d" (__port) ); \
+ __asm__ volatile ( "outb %0,%1" : : "a" (__value), "d" (__port) ); \
} while (0)
#define i386_outport_word( _port, _value ) \
do { register unsigned short __port = _port; \
register unsigned short __value = _value; \
\
- asm volatile ( "outw %0,%1" : : "a" (__value), "d" (__port) ); \
+ __asm__ volatile ( "outw %0,%1" : : "a" (__value), "d" (__port) ); \
} while (0)
#define i386_outport_long( _port, _value ) \
do { register unsigned short __port = _port; \
register unsigned int __value = _value; \
\
- asm volatile ( "outl %0,%1" : : "a" (__value), "d" (__port) ); \
+ __asm__ volatile ( "outl %0,%1" : : "a" (__value), "d" (__port) ); \
} while (0)
#define i386_inport_byte( _port, _value ) \
do { register unsigned short __port = _port; \
register unsigned char __value = 0; \
\
- asm volatile ( "inb %1,%0" : "=a" (__value) \
+ __asm__ volatile ( "inb %1,%0" : "=a" (__value) \
: "d" (__port) \
); \
_value = __value; \
@@ -130,7 +130,7 @@
do { register unsigned short __port = _port; \
register unsigned short __value = 0; \
\
- asm volatile ( "inw %1,%0" : "=a" (__value) \
+ __asm__ volatile ( "inw %1,%0" : "=a" (__value) \
: "d" (__port) \
); \
_value = __value; \
@@ -140,7 +140,7 @@
do { register unsigned short __port = _port; \
register unsigned int __value = 0; \
\
- asm volatile ( "inl %1,%0" : "=a" (__value) \
+ __asm__ volatile ( "inl %1,%0" : "=a" (__value) \
: "d" (__port) \
); \
_value = __value; \
diff -u rtems/c/src/lib/libcpu/i386/cpuModel.h:1.8 rtems/c/src/lib/libcpu/i386/cpuModel.h:1.9
--- rtems/c/src/lib/libcpu/i386/cpuModel.h:1.8 Thu Apr 15 09:09:57 2010
+++ rtems/c/src/lib/libcpu/i386/cpuModel.h Fri Feb 11 03:33:50 2011
@@ -43,7 +43,7 @@
{
/* Return the value of the on-chip cycle counter. */
unsigned long long result;
- asm volatile(".byte 0x0F, 0x31" : "=A" (result));
+ __asm__ volatile(".byte 0x0F, 0x31" : "=A" (result));
return result;
} /* rdtsc */
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* mcf5225x/network/fec.c, mcf5235/cache/cachepd.c,
mcf532x/cache/cachepd.c, shared/cache/cache.c, shared/misc/m68kidle.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.109 c/src/lib/libcpu/m68k/ChangeLog
M 1.2 c/src/lib/libcpu/m68k/mcf5225x/network/fec.c
M 1.3 c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c
M 1.3 c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c
M 1.6 c/src/lib/libcpu/m68k/shared/cache/cache.c
M 1.7 c/src/lib/libcpu/m68k/shared/misc/m68kidle.c
diff -u rtems/c/src/lib/libcpu/m68k/ChangeLog:1.108 rtems/c/src/lib/libcpu/m68k/ChangeLog:1.109
--- rtems/c/src/lib/libcpu/m68k/ChangeLog:1.108 Wed Feb 2 09:00:55 2011
+++ rtems/c/src/lib/libcpu/m68k/ChangeLog Fri Feb 11 03:36:44 2011
@@ -1,3 +1,9 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * mcf5225x/network/fec.c, mcf5235/cache/cachepd.c,
+ mcf532x/cache/cachepd.c, shared/cache/cache.c, shared/misc/m68kidle.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/m68k/mcf5225x/network/fec.c:1.1 rtems/c/src/lib/libcpu/m68k/mcf5225x/network/fec.c:1.2
--- rtems/c/src/lib/libcpu/m68k/mcf5225x/network/fec.c:1.1 Mon Apr 5 12:11:48 2010
+++ rtems/c/src/lib/libcpu/m68k/mcf5225x/network/fec.c Fri Feb 11 03:36:44 2011
@@ -175,7 +175,7 @@
MCF_FEC_ECR |= MCF_FEC_ECR_RESET;
- while (MCF_FEC_ECR&MCF_FEC_ECR_RESET) asm("nop");
+ while (MCF_FEC_ECR&MCF_FEC_ECR_RESET) __asm__ ("nop");
if (if_config->phy_init) if_config->phy_init(); /* call application specific optional extern phy initialization function */
@@ -233,7 +233,7 @@
{
MCF_FEC_MMFR = MCF_FEC_MMFR_ST(0x1) | MCF_FEC_MMFR_OP_WRITE | (MCF_FEC_MMFR_PA(phy_addr)) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | data;
smi_init(bsp_get_CPU_clock_speed()); /* enable MII clock speed after MMFR is written */
- while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) { asm("nop"); }
+ while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) { __asm__ ("nop"); }
smi_init(0); /* MII frame sent, disable clock until next operation */
MCF_FEC_EIR |= MCF_FEC_EIR_MII;
}
@@ -242,7 +242,7 @@
{
MCF_FEC_MMFR = MCF_FEC_MMFR_ST(0x1) | MCF_FEC_MMFR_OP_READ | (MCF_FEC_MMFR_PA(phy_addr)) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10;
smi_init(bsp_get_CPU_clock_speed()); /* enable MII clock speed after MMFR is written */
- while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) { asm("nop"); }
+ while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) { __asm__ ("nop"); }
smi_init(0); /* MII frame sent, disable clock until next operation */
MCF_FEC_EIR |= MCF_FEC_EIR_MII;
diff -u rtems/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c:1.2 rtems/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c:1.3
--- rtems/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c:1.2 Sun Nov 29 23:24:55 2009
+++ rtems/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c Fri Feb 11 03:36:44 2011
@@ -63,7 +63,7 @@
* Top half of cache is I-space
*/
addr = (void *)((int)addr | 0x400);
- asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
}
void _CPU_cache_enable_data(void)
@@ -97,5 +97,5 @@
* Bottom half of cache is D-space
*/
addr = (void *)((int)addr & ~0x400);
- asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
}
diff -u rtems/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c:1.2 rtems/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c:1.3
--- rtems/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c:1.2 Sun Nov 29 23:25:40 2009
+++ rtems/c/src/lib/libcpu/m68k/mcf532x/cache/cachepd.c Fri Feb 11 03:36:44 2011
@@ -7,7 +7,7 @@
#include <rtems.h>
#include <mcf532x/mcf532x.h>
-#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
+#define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
/*
* Read/write copy of common cache
@@ -41,13 +41,13 @@
{
register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
}
void _CPU_cache_flush_entire_data(void)
@@ -56,13 +56,13 @@
for(set = 0; set < 256; ++set) {
adr = (set << 4);
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
}
}
@@ -101,13 +101,13 @@
{
register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
adr += 1;
- asm volatile ("cpushl %%bc,(%0)" :: "a" (adr));
+ __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
}
void _CPU_cache_enable_data(void)
diff -u rtems/c/src/lib/libcpu/m68k/shared/cache/cache.c:1.5 rtems/c/src/lib/libcpu/m68k/shared/cache/cache.c:1.6
--- rtems/c/src/lib/libcpu/m68k/shared/cache/cache.c:1.5 Tue Dec 8 07:36:55 2009
+++ rtems/c/src/lib/libcpu/m68k/shared/cache/cache.c Fri Feb 11 03:36:44 2011
@@ -19,7 +19,7 @@
{ \
register unsigned long _value = mask; \
register unsigned long _ctl = 0; \
- asm volatile ( "movec %%cacr, %0; /* read the cacr */ \
+ __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \
andl %2, %0; /* and with _val */ \
movec %1, %%cacr" /* write the cacr */ \
: "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \
@@ -33,7 +33,7 @@
{ \
register unsigned long _value = mask; \
register unsigned long _ctl = 0; \
- asm volatile ( "movec %%cacr, %0; /* read the cacr */ \
+ __asm__ volatile ( "movec %%cacr, %0; /* read the cacr */ \
orl %2, %0; /* or with _val */ \
movec %1, %%cacr" /* write the cacr */ \
: "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \
@@ -59,7 +59,7 @@
const void * d_addr )
{
void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
- asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
+ __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
_CPU_CACR_OR(0x00000400);
}
@@ -95,7 +95,7 @@
const void * d_addr )
{
void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
- asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
+ __asm__ volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */
_CPU_CACR_OR( 0x00000004 );
}
@@ -137,14 +137,14 @@
const void * d_addr )
{
void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
- asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
+ __asm__ volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
}
void _CPU_cache_invalidate_1_data_line (
const void * d_addr )
{
void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
- asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
+ __asm__ volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
}
void _CPU_cache_flush_entire_data ( void )
@@ -171,7 +171,7 @@
const void * i_addr )
{
void * p_address = (void *) _CPU_virtual_to_physical( i_addr );
- asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
+ __asm__ volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
}
void _CPU_cache_invalidate_entire_instruction ( void )
diff -u rtems/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c:1.6 rtems/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c:1.7
--- rtems/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c:1.6 Sun Nov 29 23:09:41 2009
+++ rtems/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c Fri Feb 11 03:36:44 2011
@@ -33,11 +33,11 @@
{
#if defined(mcf5272)
for( ; ; ) {
- asm volatile( "nop" );
- asm volatile( "nop" );
+ __asm__ volatile( "nop" );
+ __asm__ volatile( "nop" );
}
#else
for( ; ; )
- asm volatile( "stop #0x3000":::"cc" ); /* supervisor mode, all interrupts on */
+ __asm__ volatile( "stop #0x3000":::"cc" ); /* supervisor mode, all interrupts on */
#endif
}
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* au1x00/vectorisrs/vectorisrs.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.102 c/src/lib/libcpu/mips/ChangeLog
M 1.6 c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c
diff -u rtems/c/src/lib/libcpu/mips/ChangeLog:1.101 rtems/c/src/lib/libcpu/mips/ChangeLog:1.102
--- rtems/c/src/lib/libcpu/mips/ChangeLog:1.101 Wed Feb 2 09:00:56 2011
+++ rtems/c/src/lib/libcpu/mips/ChangeLog Fri Feb 11 03:37:38 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * au1x00/vectorisrs/vectorisrs.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c:1.5 rtems/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c:1.6
--- rtems/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c:1.5 Fri May 28 01:09:35 2010
+++ rtems/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c Fri Feb 11 03:37:38 2011
@@ -46,7 +46,7 @@
* I don't see a good way to disable the compare
* interrupt, so let's just ignore it.
*/
- asm volatile ("mtc0 %0, $11\n" :: "r" (zero));
+ __asm__ volatile ("mtc0 %0, $11\n" :: "r" (zero));
/* CALL_ISR( AU1X00_IRQ_CNT, frame ); */
}
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c,
mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c,
new-exceptions/bspsupport/ppc_exc_initialize.c,
ppc403/clock/clock.c, ppc403/console/console.c,
ppc403/console/console.c.polled, ppc403/console/console405.c,
ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c,
rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.374 c/src/lib/libcpu/powerpc/ChangeLog
M 1.5 c/src/lib/libcpu/powerpc/e500/mmu/mmu.c
M 1.3 c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c
M 1.7 c/src/lib/libcpu/powerpc/mpc505/timer/timer.c
M 1.3 c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c
M 1.10 c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c
M 1.3 c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
M 1.25 c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
M 1.12 c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
M 1.21 c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
M 1.20 c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
M 1.11 c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c
M 1.14 c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
M 1.8 c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
M 1.28 c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
M 1.32 c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
M 1.21 c/src/lib/libcpu/powerpc/ppc403/console/console.c
M 1.9 c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled
M 1.12 c/src/lib/libcpu/powerpc/ppc403/console/console405.c
M 1.5 c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
M 1.11 c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c
M 1.7 c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h
M 1.14 c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h
M 1.13 c/src/lib/libcpu/powerpc/shared/src/cache.c
diff -u rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.373 rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.374
--- rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.373 Wed Feb 2 09:01:00 2011
+++ rtems/c/src/lib/libcpu/powerpc/ChangeLog Fri Feb 11 03:46:52 2011
@@ -1,3 +1,17 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
+ mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
+ mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
+ mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c,
+ mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c,
+ new-exceptions/bspsupport/ppc_exc_initialize.c,
+ ppc403/clock/clock.c, ppc403/console/console.c,
+ ppc403/console/console.c.polled, ppc403/console/console405.c,
+ ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c,
+ rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c:1.4 rtems/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c:1.5
--- rtems/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c:1.4 Mon Jan 31 09:48:22 2011
+++ rtems/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c Fri Feb 11 03:46:52 2011
@@ -99,9 +99,9 @@
/* Factory to generate inline macros for accessing the MAS registers */
#define __RDWRMAS(mas,rmas) \
static inline uint32_t _read_MAS##mas(void) \
- { uint32_t x; asm volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
+ { uint32_t x; __asm__ volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
static inline void _write_MAS##mas(uint32_t x) \
- { asm volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
+ { __asm__ volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
__RDWRMAS(0,FSL_EIS_MAS0)
__RDWRMAS(1,FSL_EIS_MAS1)
diff -u rtems/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c:1.2 rtems/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c:1.3
--- rtems/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c:1.2 Tue Apr 13 05:03:32 2004
+++ rtems/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c Fri Feb 11 03:46:52 2011
@@ -36,7 +36,7 @@
static rtems_isr extIsr_( rtems_vector_number i )
{
#define BIT_NUMBER(val, bit) \
- asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
+ __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
int bit;
(void)i;
diff -u rtems/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c:1.6 rtems/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c:1.7
--- rtems/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c:1.6 Fri Sep 5 07:11:47 2008
+++ rtems/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c Fri Feb 11 03:46:52 2011
@@ -22,7 +22,7 @@
void benchmark_timer_initialize( void )
{
- asm volatile( " mftb %0": "=r" (lastInitValue) );
+ __asm__ volatile( " mftb %0": "=r" (lastInitValue) );
}
/*
@@ -43,7 +43,7 @@
int benchmark_timer_read( void )
{
uint32_t value;
- asm volatile ( " mftb %0": "=r" (value) );
+ __asm__ volatile ( " mftb %0": "=r" (value) );
return value - lastInitValue;
}
diff -u rtems/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c:1.2 rtems/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c:1.3
--- rtems/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c:1.2 Tue Apr 13 05:03:32 2004
+++ rtems/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c Fri Feb 11 03:46:52 2011
@@ -36,7 +36,7 @@
static rtems_isr extIsr_( rtems_vector_number i )
{
#define BIT_NUMBER(val, bit) \
- asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
+ __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
int bit;
(void)i;
diff -u rtems/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c:1.9 rtems/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c:1.10
--- rtems/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c:1.9 Wed Apr 28 12:17:59 2010
+++ rtems/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c Fri Feb 11 03:46:52 2011
@@ -64,7 +64,7 @@
{
uint32_t ret;
- asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+ __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
return ret;
}
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c:1.2 rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c:1.3
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c:1.2 Tue Dec 1 19:57:45 2009
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c Fri Feb 11 03:46:53 2011
@@ -141,8 +141,8 @@
*/
static void dummy(void) __attribute__((noinline));
-/* add (empty) asm statement to make sure this isn't optimized away */
-static void dummy(void) { asm volatile(""); }
+/* add (empty) __asm__ statement to make sure this isn't optimized away */
+static void dummy(void) { __asm__ volatile(""); }
static unsigned probe_r1(void) __attribute__((noinline));
static unsigned probe_r1(void)
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c:1.24 rtems/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c:1.25
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c:1.24 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c Fri Feb 11 03:46:53 2011
@@ -133,7 +133,7 @@
do {
register uint32_t flags;
rtems_interrupt_disable(flags);
- asm volatile (
+ __asm__ volatile (
"mfdec %0; add %0, %0, %1; mtdec %0"
: "=&r"(decr)
: "r"(Clock_Decrementer_value));
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h:1.11 rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h:1.12
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h:1.11 Fri Jan 28 14:38:12 2011
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h Fri Feb 11 03:46:53 2011
@@ -65,7 +65,7 @@
/* Same as getdbat but reads IBAT */
extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl);
-/* Do not use the asm routines; they are obsolete; use setdbat() instead */
+/* Do not use the __asm__ routines; they are obsolete; use setdbat() instead */
extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart);
extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart);
extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart);
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c:1.20 rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c:1.21
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c:1.20 Fri Jan 28 14:38:12 2011
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c Fri Feb 11 03:46:53 2011
@@ -124,7 +124,7 @@
static void
set_hid0_sync (unsigned long val)
{
- asm volatile (
+ __asm__ volatile (
" sync \n"
" isync \n"
" mtspr %0, %1 \n"
@@ -221,7 +221,7 @@
* rely on consistent compiler flags).
*/
#define DSSALL 0x7e00066c /* dssall opcode */
- asm volatile (" .long %0"::"i" (DSSALL));
+ __asm__ volatile (" .long %0"::"i" (DSSALL));
#undef DSSALL
}
}
@@ -287,7 +287,7 @@
if (0xffffffff == size) {
bit = 32;
} else {
- asm volatile (" cntlzw %0, %1":"=r" (bit):"r" (size));
+ __asm__ volatile (" cntlzw %0, %1":"=r" (bit):"r" (size));
bit = 31 - bit;
if (1 << bit != size)
return -1;
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c:1.19 rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c:1.20
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c:1.19 Tue Dec 1 18:22:42 2009
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c Fri Feb 11 03:46:53 2011
@@ -157,7 +157,7 @@
static uint32_t
seg2vsid (uint32_t ea)
{
- asm volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
+ __asm__ volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
return ea & ((1 << LD_VSID_SIZE) - 1);
}
#else
@@ -539,9 +539,9 @@
uint32_t flags;
rtems_interrupt_disable (flags);
/* order setting 'v' after writing everything else */
- asm volatile ("eieio":::"memory");
+ __asm__ volatile ("eieio":::"memory");
pte->v = 1;
- asm volatile ("sync":::"memory");
+ __asm__ volatile ("sync":::"memory");
rtems_interrupt_enable (flags);
} else {
pte->v = 1;
@@ -869,7 +869,7 @@
rtems_interrupt_disable (flags);
pte->v = 0;
do_dssall ();
- asm volatile (" sync \n\t"
+ __asm__ volatile (" sync \n\t"
" tlbie %0 \n\t"
" eieio \n\t"
" tlbsync \n\t"
@@ -916,7 +916,7 @@
* rely on consistent compiler flags).
*/
#define DSSALL 0x7e00066c /* dssall opcode */
- asm volatile (" .long %0"::"i" (DSSALL));
+ __asm__ volatile (" .long %0"::"i" (DSSALL));
#undef DSSALL
}
}
@@ -946,21 +946,21 @@
if (wimg < 0 && pp < 0)
return pte;
- asm volatile ("mfmsr %0":"=r" (msr));
+ __asm__ volatile ("mfmsr %0":"=r" (msr));
/* switch MMU and IRQs off */
SYNC_LONGJMP (msr & ~(MSR_EE | MSR_DR | MSR_IR));
pte->v = 0;
do_dssall ();
- asm volatile ("sync":::"memory");
+ __asm__ volatile ("sync":::"memory");
if (wimg >= 0)
pte->wimg = wimg;
if (pp >= 0)
pte->pp = pp;
- asm volatile ("tlbie %0; eieio"::"r" (ea):"memory");
+ __asm__ volatile ("tlbie %0; eieio"::"r" (ea):"memory");
pte->v = 1;
- asm volatile ("tlbsync; sync":::"memory");
+ __asm__ volatile ("tlbsync; sync":::"memory");
/* restore, i.e., switch MMU and IRQs back on */
SYNC_LONGJMP (msr);
diff -u rtems/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c:1.10 rtems/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c:1.11
--- rtems/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c:1.10 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c Fri Feb 11 03:46:53 2011
@@ -60,7 +60,7 @@
{
uint32_t ret;
- asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+ __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
return ret;
}
diff -u rtems/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c:1.13 rtems/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c:1.14
--- rtems/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c:1.13 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c Fri Feb 11 03:46:53 2011
@@ -57,7 +57,7 @@
{
uint32_t ret;
- asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+ __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
return ret;
}
diff -u rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c:1.7 rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c:1.8
--- rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c:1.7 Fri Jan 28 14:38:13 2011
+++ rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c Fri Feb 11 03:46:53 2011
@@ -30,8 +30,8 @@
uint32_t ppc_exc_cache_wb_check = 1;
-#define MTIVPR(prefix) asm volatile ("mtivpr %0" : : "r" (prefix))
-#define MTIVOR(x, vec) asm volatile ("mtivor"#x" %0" : : "r" (vec))
+#define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
+#define MTIVOR(x, vec) __asm__ volatile ("mtivor"#x" %0" : : "r" (vec))
static void ppc_exc_initialize_booke(void)
{
@@ -94,7 +94,7 @@
/* Assembly code needs SDA_BASE in r13 (SVR4 or EABI). Make sure
* early init code put it there.
*/
- asm volatile (
+ __asm__ volatile (
"lis %0, _SDA_BASE_ at h\n"
"ori %0, %0, _SDA_BASE_ at l\n"
"mr %1, 13\n"
@@ -174,7 +174,7 @@
* ATM.
*/
p = (p + 31U) & ~31U;
- asm volatile ("dcbz 0, %0"::"b" (p));
+ __asm__ volatile ("dcbz 0, %0"::"b" (p));
/* If we make it thru here then things seem to be OK */
}
diff -u rtems/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c:1.27 rtems/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c:1.28
--- rtems/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c:1.27 Tue Dec 1 19:41:57 2009
+++ rtems/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c Fri Feb 11 03:46:53 2011
@@ -132,7 +132,7 @@
*/
{ uint32_t r2 = 0;
unsigned r13 = 0;
- asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
+ __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
the_context->gpr2 = r2;
the_context->gpr13 = r13;
@@ -140,7 +140,7 @@
#elif (PPC_ABI == PPC_ABI_EABI)
{ uint32_t r2 = 0;
unsigned r13 = 0;
- asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
+ __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
the_context->gpr2 = r2;
the_context->gpr13 = r13;
diff -u rtems/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c:1.31 rtems/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c:1.32
--- rtems/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c:1.31 Sun Apr 25 11:10:35 2010
+++ rtems/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c Fri Feb 11 03:46:53 2011
@@ -73,9 +73,9 @@
register uint32_t rc;
#ifndef ppc405 /* this is a ppc403 */
- asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
+ __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
#else /* ppc405 */
- asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
+ __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
#endif /* ppc405 */
return rc;
@@ -135,11 +135,11 @@
/* XXX: count these! this should never happen :-) */
}
- asm volatile ("mtspr 0x3db, %0" :: "r"
+ __asm__ volatile ("mtspr 0x3db, %0" :: "r"
(clicks_til_next_interrupt)); /* PIT */
}
- asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
+ __asm__ volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
Clock_driver_ticks++;
@@ -160,7 +160,7 @@
{
register uint32_t tcr;
- asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+ __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
return (tcr & 0x04000000) != 0;
}
@@ -171,11 +171,11 @@
{
register uint32_t tcr;
- asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+ __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
tcr &= ~ 0x04400000;
- asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+ __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
}
void ClockOn(
@@ -191,16 +191,16 @@
Clock_driver_ticks = 0;
#ifndef ppc405 /* this is a ppc403 */
- asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
+ __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
if (bsp_timer_internal_clock) {
iocr &= ~4; /* timer clocked from system clock */
}
else {
iocr |= 4; /* select external timer clock */
}
- asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
+ __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
- asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
+ __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
if (((pvr & 0xffff0000) >> 16) != 0x0020)
return; /* Not a ppc403 */
@@ -215,14 +215,14 @@
auto_restart = true;
#else /* ppc405 */
- asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */
+ __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */
if (bsp_timer_internal_clock) {
iocr &=~0x800000 ;/* timer clocked from system clock CETE*/
}
else {
iocr |= 0x800000; /* select external timer clock CETE*/
}
- asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
+ __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
/*
* Enable auto restart
@@ -238,7 +238,7 @@
* Set PIT value
*/
- asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
+ __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
/*
* Set timer to autoreload, bit TCR->ARE = 1 0x0400000
@@ -246,10 +246,10 @@
*/
tick_time = get_itimer() + pit_value;
- asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+ __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
#if 1
- asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+ __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
#endif
}
diff -u rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c:1.20 rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c:1.21
--- rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c:1.20 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c Fri Feb 11 03:46:53 2011
@@ -351,12 +351,12 @@
* select RTS/CTS hardware handshake lines,
* select clock source
*/
- asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
+ __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
tmp &= ~3;
tmp |= (bsp_serial_external_clock ? 2 : 0) | 1;
- asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
+ __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
/* clear any receive (error) status */
port->SPLS = (LSRDataReady | LSRFramingError | LSROverrunError |
diff -u rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled:1.8 rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled:1.9
--- rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled:1.8 Sat Sep 6 12:36:55 2008
+++ rtems/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled Fri Feb 11 03:46:53 2011
@@ -146,11 +146,11 @@
extern uint32_t bsp_serial_rate;
/* Initialise the serial port */
- asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
+ __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
tmp &= ~3;
tmp |= (bsp_serial_external_clock ? 2 : 0) |
(bsp_serial_cts_rts ? 1 : 0);
- asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
+ __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
port->SPLS = (LSRDataReady | LSRFramingError | LSROverrunError |
LSRParityError | LSRBreakInterrupt);
tmp = bsp_serial_per_sec / bsp_get_serial_rate;
diff -u rtems/c/src/lib/libcpu/powerpc/ppc403/console/console405.c:1.11 rtems/c/src/lib/libcpu/powerpc/ppc403/console/console405.c:1.12
--- rtems/c/src/lib/libcpu/powerpc/ppc403/console/console405.c:1.11 Sun Apr 25 11:10:36 2010
+++ rtems/c/src/lib/libcpu/powerpc/ppc403/console/console405.c Fri Feb 11 03:46:53 2011
@@ -367,14 +367,14 @@
* Select clock source and set uart internal clock divisor
*/
- asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
+ __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
/* UART0 bit 24 0x80, UART1 bit 25 0x40 */
tmp |= (bsp_serial_external_clock ? (USE_UART ? 0x40 : 0x80) : 0);
tmp |= (bsp_serial_external_clock ? 0: ((UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
- asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
+ __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
/* Disable port interrupts while changing hardware */
_ier = port->IER;
diff -u rtems/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c:1.4 rtems/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c:1.5
--- rtems/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c:1.4 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c Fri Feb 11 03:46:53 2011
@@ -47,7 +47,7 @@
RTEMS_INLINE_ROUTINE void
clr_exisr(uint32_t mask)
{
- asm volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
+ __asm__ volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
}
/*
@@ -58,7 +58,7 @@
{
uint32_t val;
- asm volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
+ __asm__ volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
return val;
}
@@ -69,7 +69,7 @@
get_exier(void)
{
uint32_t val;
- asm volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
+ __asm__ volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
return val;
}
@@ -79,7 +79,7 @@
RTEMS_INLINE_ROUTINE void
set_exier(uint32_t val)
{
- asm volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
+ __asm__ volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
}
#else /* not ppc405 */
@@ -87,7 +87,7 @@
RTEMS_INLINE_ROUTINE void
clr_exisr(uint32_t mask)
{
- asm volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
+ __asm__ volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
}
/*
@@ -98,7 +98,7 @@
{
uint32_t val;
- asm volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
+ __asm__ volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
return val;
}
@@ -109,7 +109,7 @@
get_exier(void)
{
uint32_t val;
- asm volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
+ __asm__ volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
return val;
}
@@ -119,7 +119,7 @@
RTEMS_INLINE_ROUTINE void
set_exier(uint32_t val)
{
- asm volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
+ __asm__ volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
}
#endif /* ppc405 */
/*
diff -u rtems/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c:1.10 rtems/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c:1.11
--- rtems/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c:1.10 Sun Apr 25 11:10:36 2010
+++ rtems/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c Fri Feb 11 03:46:53 2011
@@ -359,14 +359,14 @@
* Select clock source and set uart internal clock divisor
*/
- asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
+ __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
/* UART0 bit 24 0x80, UART1 bit 25 0x40 */
tmp |= (bsp_serial_external_clock ? (TTY0_USE_UART ? 0x40 : 0x80) : 0);
tmp |= (bsp_serial_external_clock ? 0: ((TTY0_UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
- asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
+ __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
/* Disable tty0port interrupts while changing hardware */
_ier = tty0port->IER;
diff -u rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h:1.6 rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h:1.7
--- rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h:1.6 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h Fri Feb 11 03:46:53 2011
@@ -13,7 +13,7 @@
#define _CPU_Data_Cache_Block_Flush( _address ) \
do { register void *__address = (_address); \
register uint32_t _zero = 0; \
- asm volatile ( "dcbf %0,%1" : \
+ __asm__ volatile ( "dcbf %0,%1" : \
"=r" (_zero), "=r" (__address) : \
"0" (_zero), "1" (__address) \
); \
@@ -29,7 +29,7 @@
#define _CPU_Data_Cache_Block_Invalidate( _address ) \
do { register void *__address = (_address); \
register uint32_t _zero = 0; \
- asm volatile ( "dcbi %0,%1" : \
+ __asm__ volatile ( "dcbi %0,%1" : \
"=r" (_zero), "=r" (__address) : \
"0" (_zero), "1" (__address) \
); \
diff -u rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h:1.13 rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h:1.14
--- rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h:1.13 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h Fri Feb 11 03:46:53 2011
@@ -57,7 +57,7 @@
{
uint8_t value;
- asm volatile (
+ __asm__ volatile (
"lbz %0, 0(%1)"
: "=r" (value)
: "b" (src)
@@ -73,7 +73,7 @@
{
uint16_t value;
- asm volatile (
+ __asm__ volatile (
"lhz %0, 0(%1)"
: "=r" (value)
: "b" (src)
@@ -89,7 +89,7 @@
{
uint32_t value;
- asm volatile (
+ __asm__ volatile (
"lwz %0, 0(%1)"
: "=r" (value)
: "b" (src)
@@ -103,7 +103,7 @@
*/
static inline void ppc_write_byte(uint8_t value, volatile void *dest)
{
- asm volatile (
+ __asm__ volatile (
"stb %0, 0(%1)"
:
: "r" (value), "b" (dest)
@@ -115,7 +115,7 @@
*/
static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
{
- asm volatile (
+ __asm__ volatile (
"sth %0, 0(%1)"
:
: "r" (value), "b" (dest)
@@ -127,7 +127,7 @@
*/
static inline void ppc_write_word(uint32_t value, volatile void *dest)
{
- asm volatile (
+ __asm__ volatile (
"stw %0, 0(%1)" :
: "r" (value), "b" (dest)
);
@@ -138,7 +138,7 @@
{
void *sp;
- asm volatile (
+ __asm__ volatile (
"mr %0, 1"
: "=r" (sp)
);
@@ -148,7 +148,7 @@
static inline void ppc_set_stack_pointer(void *sp)
{
- asm volatile (
+ __asm__ volatile (
"mr 1, %0"
:
: "r" (sp)
@@ -159,7 +159,7 @@
{
void *lr;
- asm volatile (
+ __asm__ volatile (
"mflr %0"
: "=r" (lr)
);
@@ -169,7 +169,7 @@
static inline void ppc_set_link_register(void *lr)
{
- asm volatile (
+ __asm__ volatile (
"mtlr %0"
:
: "r" (lr)
@@ -180,7 +180,7 @@
{
uint32_t msr;
- asm volatile (
+ __asm__ volatile (
"mfmsr %0"
: "=r" (msr)
);
@@ -190,7 +190,7 @@
static inline void ppc_set_machine_state_register(uint32_t msr)
{
- asm volatile (
+ __asm__ volatile (
"mtmsr %0"
:
: "r" (msr)
@@ -201,14 +201,14 @@
{
RTEMS_COMPILER_MEMORY_BARRIER();
- asm volatile ("sync");
+ __asm__ volatile ("sync");
}
static inline void ppc_synchronize_instructions(void)
{
RTEMS_COMPILER_MEMORY_BARRIER();
- asm volatile ("isync");
+ __asm__ volatile ("isync");
}
/**
@@ -224,7 +224,7 @@
RTEMS_COMPILER_MEMORY_BARRIER();
- asm volatile (
+ __asm__ volatile (
"mfmsr %0;"
"ori %1, %0, 0x8000;"
"mtmsr %1"
@@ -266,10 +266,10 @@
* 2009/10/30 Th. D.
*/
#define CPU_Get_timebase_low( _value ) \
- asm volatile( "mftb %0" : "=r" (_value) )
+ __asm__ volatile( "mftb %0" : "=r" (_value) )
#else
#define CPU_Get_timebase_low( _value ) \
- asm volatile( "mfspr %0,268" : "=r" (_value) )
+ __asm__ volatile( "mfspr %0,268" : "=r" (_value) )
#endif
/* Must be provided for rtems_bsp_delay to work */
@@ -300,11 +300,11 @@
#define PPC_Set_decrementer( _clicks ) \
do { \
- asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
+ __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \
} while (0)
#define PPC_Get_decrementer( _clicks ) \
- asm volatile( "mfdec %0" : "=r" (_clicks) )
+ __asm__ volatile( "mfdec %0" : "=r" (_clicks) )
/*
* Routines to access the time base register
@@ -320,13 +320,13 @@
do {
#if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
/* See comment above (CPU_Get_timebase_low) */
- asm volatile( "mftbu %0" : "=r" (tbr_high_old));
- asm volatile( "mftb %0" : "=r" (tbr_low));
- asm volatile( "mftbu %0" : "=r" (tbr_high));
+ __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old));
+ __asm__ volatile( "mftb %0" : "=r" (tbr_low));
+ __asm__ volatile( "mftbu %0" : "=r" (tbr_high));
#else
- asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
- asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
- asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
+ __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
+ __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low));
+ __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high));
#endif
} while ( tbr_high_old != tbr_high );
@@ -343,8 +343,8 @@
tbr_low = (uint32_t) tbr;
tbr_high = (uint32_t) (tbr >> 32);
- asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
- asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
+ __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low));
+ __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high));
}
@@ -375,7 +375,7 @@
#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
({ \
uint32_t val; \
- asm volatile (\
+ __asm__ volatile (\
"mfspr %0, " PPC_STRINGOF(spr) \
: "=r" (val) \
); \
@@ -388,7 +388,7 @@
*/
#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \
do { \
- asm volatile (\
+ __asm__ volatile (\
"mtspr " PPC_STRINGOF(spr) ", %0" \
: \
: "r" (val) \
@@ -462,7 +462,7 @@
#define PPC_DEVICE_CONTROL_REGISTER(dcr) \
({ \
uint32_t val; \
- asm volatile (\
+ __asm__ volatile (\
"mfdcr %0, " PPC_STRINGOF(dcr) \
: "=r" (val) \
); \
@@ -477,7 +477,7 @@
*/
#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \
do { \
- asm volatile (\
+ __asm__ volatile (\
"mtdcr " PPC_STRINGOF(dcr) ", %0" \
: \
: "r" (val) \
diff -u rtems/c/src/lib/libcpu/powerpc/shared/src/cache.c:1.12 rtems/c/src/lib/libcpu/powerpc/shared/src/cache.c:1.13
--- rtems/c/src/lib/libcpu/powerpc/shared/src/cache.c:1.12 Sun Nov 29 23:07:54 2009
+++ rtems/c/src/lib/libcpu/powerpc/shared/src/cache.c Fri Feb 11 03:46:53 2011
@@ -33,7 +33,7 @@
#define PPC_Get_HID0( _value ) \
do { \
_value = 0; /* to avoid warnings */ \
- asm volatile( \
+ __asm__ volatile( \
"mfspr %0, 0x3f0;" /* get HID0 */ \
"isync" \
: "=r" (_value) \
@@ -43,7 +43,7 @@
#define PPC_Set_HID0( _value ) \
do { \
- asm volatile( \
+ __asm__ volatile( \
"isync;" \
"mtspr 0x3f0, %0;" /* load HID0 */ \
"isync" \
@@ -269,14 +269,14 @@
const void * _address )
{
register const void *__address = _address;
- asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
+ __asm__ volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
}
void _CPU_cache_flush_1_data_line(
const void * _address )
{
register const void *__address = _address;
- asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
+ __asm__ volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
}
@@ -284,7 +284,7 @@
const void * _address )
{
register const void *__address = _address;
- asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
+ __asm__ volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
}
/* end of file */
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* mpc6xx/altivec/vec_sup.c, mpc6xx/mmu/bat.h:
Fix up comments having been broken in previous commit.
M 1.375 c/src/lib/libcpu/powerpc/ChangeLog
M 1.4 c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
M 1.13 c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
diff -u rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.374 rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.375
--- rtems/c/src/lib/libcpu/powerpc/ChangeLog:1.374 Fri Feb 11 03:46:52 2011
+++ rtems/c/src/lib/libcpu/powerpc/ChangeLog Fri Feb 11 03:55:48 2011
@@ -1,5 +1,10 @@
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+ * mpc6xx/altivec/vec_sup.c, mpc6xx/mmu/bat.h:
+ Fix up comments having been broken in previous commit.
+
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
* e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c:1.3 rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c:1.4
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c:1.3 Fri Feb 11 03:46:53 2011
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c Fri Feb 11 03:55:48 2011
@@ -141,7 +141,7 @@
*/
static void dummy(void) __attribute__((noinline));
-/* add (empty) __asm__ statement to make sure this isn't optimized away */
+/* add (empty) asm-statement to make sure this isn't optimized away */
static void dummy(void) { __asm__ volatile(""); }
static unsigned probe_r1(void) __attribute__((noinline));
diff -u rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h:1.12 rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h:1.13
--- rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h:1.12 Fri Feb 11 03:46:53 2011
+++ rtems/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h Fri Feb 11 03:55:48 2011
@@ -65,7 +65,7 @@
/* Same as getdbat but reads IBAT */
extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl);
-/* Do not use the __asm__ routines; they are obsolete; use setdbat() instead */
+/* Do not use the asm-routines; they are obsolete; use setdbat() instead */
extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart);
extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart);
extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart);
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* sh7032/delay/delay.c, sh7032/score/cpu_asm.c,
sh7032/score/ispsh7032.c, sh7045/sci/sci.c,
sh7045/sci/sci_termios.c, sh7045/score/cpu_asm.c,
sh7045/score/ispsh7045.c, sh7750/sci/sh4uart.c,
sh7750/score/cpu_asm.c, sh7750/score/ispsh7750.c,
shgdb/score/cpu_asm.c, shgdb/score/ispshgdb.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.65 c/src/lib/libcpu/sh/ChangeLog
M 1.8 c/src/lib/libcpu/sh/sh7032/delay/delay.c
M 1.18 c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
M 1.10 c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
M 1.17 c/src/lib/libcpu/sh/sh7045/sci/sci.c
M 1.8 c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c
M 1.20 c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
M 1.11 c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
M 1.13 c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
M 1.16 c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
M 1.11 c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
M 1.5 c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
M 1.4 c/src/lib/libcpu/sh/shgdb/score/ispshgdb.c
diff -u rtems/c/src/lib/libcpu/sh/ChangeLog:1.64 rtems/c/src/lib/libcpu/sh/ChangeLog:1.65
--- rtems/c/src/lib/libcpu/sh/ChangeLog:1.64 Wed Feb 2 09:01:01 2011
+++ rtems/c/src/lib/libcpu/sh/ChangeLog Fri Feb 11 03:57:25 2011
@@ -1,3 +1,13 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * sh7032/delay/delay.c, sh7032/score/cpu_asm.c,
+ sh7032/score/ispsh7032.c, sh7045/sci/sci.c,
+ sh7045/sci/sci_termios.c, sh7045/score/cpu_asm.c,
+ sh7045/score/ispsh7045.c, sh7750/sci/sh4uart.c,
+ sh7750/score/cpu_asm.c, sh7750/score/ispsh7750.c,
+ shgdb/score/cpu_asm.c, shgdb/score/ispshgdb.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/sh/sh7032/delay/delay.c:1.7 rtems/c/src/lib/libcpu/sh/sh7032/delay/delay.c:1.8
--- rtems/c/src/lib/libcpu/sh/sh7032/delay/delay.c:1.7 Mon Nov 26 17:02:03 2007
+++ rtems/c/src/lib/libcpu/sh/sh7032/delay/delay.c Fri Feb 11 03:57:25 2011
@@ -43,7 +43,7 @@
register uint32_t clicks_per_usec = bsp_clicks_per_second / 1000000;
register uint32_t _delay = (microseconds) * (clicks_per_usec);
- asm volatile (
+ __asm__ volatile (
"0: add #-4,%0\n\
nop\n\
cmp/pl %0\n\
diff -u rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c:1.17 rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c:1.18
--- rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c:1.17 Fri Jul 30 13:51:48 2010
+++ rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c Fri Feb 11 03:57:25 2011
@@ -49,7 +49,7 @@
unsigned long *_old_stack_ptr;
#endif
-register unsigned long *stack_ptr asm("r15");
+register unsigned long *stack_ptr __asm__ ("r15");
/*
* sh_set_irq_priority
diff -u rtems/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c:1.9 rtems/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c:1.10
--- rtems/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c:1.9 Fri Apr 16 16:29:43 2004
+++ rtems/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c Fri Feb 11 03:57:25 2011
@@ -122,7 +122,7 @@
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
-asm(" .section .text\n\
+__asm__ (" .section .text\n\
.global __dummy_isp\n\
__dummy_isp:\n\
mov.l r14, at -r15\n\
diff -u rtems/c/src/lib/libcpu/sh/sh7045/sci/sci.c:1.16 rtems/c/src/lib/libcpu/sh/sh7045/sci/sci.c:1.17
--- rtems/c/src/lib/libcpu/sh/sh7045/sci/sci.c:1.16 Thu Apr 15 03:39:26 2010
+++ rtems/c/src/lib/libcpu/sh/sh7045/sci/sci.c Fri Feb 11 03:57:25 2011
@@ -379,7 +379,7 @@
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
for (a=0; a < 10000L; a++) { /* Delay */
- asm volatile ("nop");
+ __asm__ volatile ("nop");
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
diff -u rtems/c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c:1.7 rtems/c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c:1.8
--- rtems/c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c:1.7 Thu Apr 15 03:39:26 2010
+++ rtems/c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c Fri Feb 11 03:57:25 2011
@@ -113,7 +113,7 @@
SH_SCI_REG_DATA(brr, minor, SCI_BRR);
for (a=0; a < 10000L; a++) { /* Delay one bit */
- asm volatile ("nop");
+ __asm__ volatile ("nop");
}
SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR);
@@ -295,7 +295,7 @@
sh_sci_set_attributes(minor, Console_Port_Tbl[minor].pDeviceParams);
for (a=0; a < 10000L; a++) { /* Delay */
- asm volatile ("nop");
+ __asm__ volatile ("nop");
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
diff -u rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c:1.19 rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c:1.20
--- rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c:1.19 Fri Jul 30 13:51:48 2010
+++ rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c Fri Feb 11 03:57:25 2011
@@ -48,7 +48,7 @@
unsigned long *_old_stack_ptr;
#endif
-register unsigned long *stack_ptr asm("r15");
+register unsigned long *stack_ptr __asm__ ("r15");
/*
* sh_set_irq_priority
diff -u rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c:1.10 rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c:1.11
--- rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c:1.10 Fri Apr 16 16:29:43 2004
+++ rtems/c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c Fri Feb 11 03:57:25 2011
@@ -151,7 +151,7 @@
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
-asm(" .section .text\n\
+__asm__ (" .section .text\n\
.global __dummy_isp\n\
__dummy_isp:\n\
mov.l r14, at -r15\n\
diff -u rtems/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c:1.12 rtems/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c:1.13
--- rtems/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c:1.12 Sun Nov 29 23:09:01 2009
+++ rtems/c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c Fri Feb 11 03:57:25 2011
@@ -842,7 +842,7 @@
* Says gdb that program finished to get out from it.
*/
extern void ipl_finish(void);
-asm(
+__asm__ (
" .global _ipl_finish\n"
"_ipl_finish:\n"
" mov.l __ipl_finish_value, r0\n"
@@ -856,7 +856,7 @@
);
extern int ipl_serial_input(int poll_count);
-asm(
+__asm__ (
" .global _ipl_serial_input\n"
"_ipl_serial_input:\n"
" mov #1,r0\n"
diff -u rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c:1.15 rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c:1.16
--- rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c:1.15 Fri Jul 30 13:51:48 2010
+++ rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c Fri Feb 11 03:57:25 2011
@@ -48,7 +48,7 @@
unsigned long *_old_stack_ptr;
#endif
-register unsigned long *stack_ptr asm("r15");
+register unsigned long *stack_ptr __asm__ ("r15");
/*
* This routine provides the RTEMS interrupt management.
diff -u rtems/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c:1.10 rtems/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c:1.11
--- rtems/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c:1.10 Tue Sep 30 11:23:46 2008
+++ rtems/c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c Fri Feb 11 03:57:25 2011
@@ -309,7 +309,7 @@
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 2
************************************************/
-asm(" .section .text\n\
+__asm__ (" .section .text\n\
.global __dummy_isp\n\
__dummy_isp:\n\
mov.l r14, at -r15\n\
diff -u rtems/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c:1.4 rtems/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c:1.5
--- rtems/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c:1.4 Fri Jul 30 13:51:49 2010
+++ rtems/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c Fri Feb 11 03:57:25 2011
@@ -21,7 +21,7 @@
unsigned long *_old_stack_ptr;
#endif
-register unsigned long *stack_ptr asm("r15");
+register unsigned long *stack_ptr __asm__ ("r15");
/*
* This routine provides the RTEMS interrupt management.
diff -u rtems/c/src/lib/libcpu/sh/shgdb/score/ispshgdb.c:1.3 rtems/c/src/lib/libcpu/sh/shgdb/score/ispshgdb.c:1.4
--- rtems/c/src/lib/libcpu/sh/shgdb/score/ispshgdb.c:1.3 Tue Sep 30 11:23:46 2008
+++ rtems/c/src/lib/libcpu/sh/shgdb/score/ispshgdb.c Fri Feb 11 03:57:25 2011
@@ -137,7 +137,7 @@
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
-asm(" .section .text\n\
+__asm__ (" .section .text\n\
.global __dummy_isp\n\
__dummy_isp:\n\
mov.l r14, at -r15\n\
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* shared/cache/cache.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.6 c/src/lib/libcpu/sparc64/ChangeLog
M 1.2 c/src/lib/libcpu/sparc64/shared/cache/cache.c
diff -u rtems/c/src/lib/libcpu/sparc64/ChangeLog:1.5 rtems/c/src/lib/libcpu/sparc64/ChangeLog:1.6
--- rtems/c/src/lib/libcpu/sparc64/ChangeLog:1.5 Wed Feb 2 09:01:04 2011
+++ rtems/c/src/lib/libcpu/sparc64/ChangeLog Fri Feb 11 03:58:12 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * shared/cache/cache.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/sparc64/shared/cache/cache.c:1.1 rtems/c/src/lib/libcpu/sparc64/shared/cache/cache.c:1.2
--- rtems/c/src/lib/libcpu/sparc64/shared/cache/cache.c:1.1 Thu Jun 17 11:16:25 2010
+++ rtems/c/src/lib/libcpu/sparc64/shared/cache/cache.c Fri Feb 11 03:58:12 2011
@@ -12,7 +12,7 @@
void _CPU_cache_invalidate_entire_instruction ( void )
{
- asm volatile ("flush");
+ __asm__ volatile ("flush");
}
/* XXX these need to be addressed */
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* cache/cache.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.55 c/src/lib/libcpu/sparc/ChangeLog
M 1.3 c/src/lib/libcpu/sparc/cache/cache.c
diff -u rtems/c/src/lib/libcpu/sparc/ChangeLog:1.54 rtems/c/src/lib/libcpu/sparc/ChangeLog:1.55
--- rtems/c/src/lib/libcpu/sparc/ChangeLog:1.54 Wed Feb 2 09:01:03 2011
+++ rtems/c/src/lib/libcpu/sparc/ChangeLog Fri Feb 11 03:58:54 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * cache/cache.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libcpu/sparc/cache/cache.c:1.2 rtems/c/src/lib/libcpu/sparc/cache/cache.c:1.3
--- rtems/c/src/lib/libcpu/sparc/cache/cache.c:1.2 Mon Nov 27 11:02:39 2000
+++ rtems/c/src/lib/libcpu/sparc/cache/cache.c Fri Feb 11 03:58:54 2011
@@ -12,7 +12,7 @@
void _CPU_cache_invalidate_entire_instruction ( void )
{
- asm volatile ("flush");
+ __asm__ volatile ("flush");
}
/* XXX these need to be addressed */
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* include/tm27.h, startup/spurious.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.161 c/src/lib/libbsp/sparc/erc32/ChangeLog
M 1.3 c/src/lib/libbsp/sparc/erc32/include/tm27.h
M 1.12 c/src/lib/libbsp/sparc/erc32/startup/spurious.c
diff -u rtems/c/src/lib/libbsp/sparc/erc32/ChangeLog:1.160 rtems/c/src/lib/libbsp/sparc/erc32/ChangeLog:1.161
--- rtems/c/src/lib/libbsp/sparc/erc32/ChangeLog:1.160 Wed Feb 9 00:33:58 2011
+++ rtems/c/src/lib/libbsp/sparc/erc32/ChangeLog Fri Feb 11 04:06:48 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * include/tm27.h, startup/spurious.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-09 Ralf Corsépius <ralf.corsepius at rtems.org>
* timer/timer.c: Include <rtems/btimer.h>.
diff -u rtems/c/src/lib/libbsp/sparc/erc32/include/tm27.h:1.2 rtems/c/src/lib/libbsp/sparc/erc32/include/tm27.h:1.3
--- rtems/c/src/lib/libbsp/sparc/erc32/include/tm27.h:1.2 Thu Apr 22 23:47:38 2004
+++ rtems/c/src/lib/libbsp/sparc/erc32/include/tm27.h Fri Feb 11 04:06:48 2011
@@ -39,7 +39,7 @@
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
- asm volatile( "ta 0x10; nop " );
+ __asm__ volatile( "ta 0x10; nop " );
#define Clear_tm27_intr() /* empty */
diff -u rtems/c/src/lib/libbsp/sparc/erc32/startup/spurious.c:1.11 rtems/c/src/lib/libbsp/sparc/erc32/startup/spurious.c:1.12
--- rtems/c/src/lib/libbsp/sparc/erc32/startup/spurious.c:1.11 Sun Nov 29 09:33:26 2009
+++ rtems/c/src/lib/libbsp/sparc/erc32/startup/spurious.c Fri Feb 11 04:06:48 2011
@@ -128,7 +128,7 @@
* What else can we do but stop ...
*/
- asm volatile( "mov 1, %g1; ta 0x0" );
+ __asm__ volatile( "mov 1, %g1; ta 0x0" );
}
/*
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* cchip/cchip.c, include/tm27.h, startup/spurious.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.79 c/src/lib/libbsp/sparc/leon2/ChangeLog
M 1.5 c/src/lib/libbsp/sparc/leon2/cchip/cchip.c
M 1.2 c/src/lib/libbsp/sparc/leon2/include/tm27.h
M 1.7 c/src/lib/libbsp/sparc/leon2/startup/spurious.c
diff -u rtems/c/src/lib/libbsp/sparc/leon2/ChangeLog:1.78 rtems/c/src/lib/libbsp/sparc/leon2/ChangeLog:1.79
--- rtems/c/src/lib/libbsp/sparc/leon2/ChangeLog:1.78 Wed Feb 9 00:33:58 2011
+++ rtems/c/src/lib/libbsp/sparc/leon2/ChangeLog Fri Feb 11 04:06:49 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * cchip/cchip.c, include/tm27.h, startup/spurious.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-09 Ralf Corsépius <ralf.corsepius at rtems.org>
* timer/timer.c: Include <rtems/btimer.h>.
diff -u rtems/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c:1.4 rtems/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c:1.5
--- rtems/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c:1.4 Sun Nov 29 09:33:26 2009
+++ rtems/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c Fri Feb 11 04:06:49 2011
@@ -38,7 +38,7 @@
#define READ_REG(address) _READ_REG((unsigned int)address)
static __inline__ unsigned int _READ_REG(unsigned int addr) {
unsigned int tmp;
- asm("lda [%1]1, %0 "
+ __asm__ ("lda [%1]1, %0 "
: "=r"(tmp)
: "r"(addr)
);
diff -u rtems/c/src/lib/libbsp/sparc/leon2/include/tm27.h:1.1 rtems/c/src/lib/libbsp/sparc/leon2/include/tm27.h:1.2
--- rtems/c/src/lib/libbsp/sparc/leon2/include/tm27.h:1.1 Mon Jan 9 04:36:06 2006
+++ rtems/c/src/lib/libbsp/sparc/leon2/include/tm27.h Fri Feb 11 04:06:49 2011
@@ -39,7 +39,7 @@
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
- asm volatile( "ta 0x10; nop " );
+ __asm__ volatile( "ta 0x10; nop " );
#define Clear_tm27_intr() /* empty */
diff -u rtems/c/src/lib/libbsp/sparc/leon2/startup/spurious.c:1.6 rtems/c/src/lib/libbsp/sparc/leon2/startup/spurious.c:1.7
--- rtems/c/src/lib/libbsp/sparc/leon2/startup/spurious.c:1.6 Sun Nov 29 09:33:26 2009
+++ rtems/c/src/lib/libbsp/sparc/leon2/startup/spurious.c Fri Feb 11 04:06:49 2011
@@ -109,7 +109,7 @@
* What else can we do but stop ...
*/
- asm volatile( "mov 1, %g1; ta 0x0" );
+ __asm__ volatile( "mov 1, %g1; ta 0x0" );
}
/*
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* amba/amba.c, include/tm27.h, shmsupp/lock.c, startup/bspstart.c,
startup/spurious.c:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.101 c/src/lib/libbsp/sparc/leon3/ChangeLog
M 1.13 c/src/lib/libbsp/sparc/leon3/amba/amba.c
M 1.2 c/src/lib/libbsp/sparc/leon3/include/tm27.h
M 1.5 c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c
M 1.19 c/src/lib/libbsp/sparc/leon3/startup/bspstart.c
M 1.8 c/src/lib/libbsp/sparc/leon3/startup/spurious.c
diff -u rtems/c/src/lib/libbsp/sparc/leon3/ChangeLog:1.100 rtems/c/src/lib/libbsp/sparc/leon3/ChangeLog:1.101
--- rtems/c/src/lib/libbsp/sparc/leon3/ChangeLog:1.100 Wed Feb 9 00:33:58 2011
+++ rtems/c/src/lib/libbsp/sparc/leon3/ChangeLog Fri Feb 11 04:06:51 2011
@@ -1,3 +1,9 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * amba/amba.c, include/tm27.h, shmsupp/lock.c, startup/bspstart.c,
+ startup/spurious.c:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-09 Ralf Corsépius <ralf.corsepius at rtems.org>
* timer/timer.c: Include <rtems/btimer.h>.
diff -u rtems/c/src/lib/libbsp/sparc/leon3/amba/amba.c:1.12 rtems/c/src/lib/libbsp/sparc/leon3/amba/amba.c:1.13
--- rtems/c/src/lib/libbsp/sparc/leon3/amba/amba.c:1.12 Mon May 24 10:05:19 2010
+++ rtems/c/src/lib/libbsp/sparc/leon3/amba/amba.c Fri Feb 11 04:06:51 2011
@@ -35,7 +35,7 @@
unsigned int getasr17(void);
-asm(" .text \n"
+__asm__ (" .text \n"
"getasr17: \n"
"retl \n"
"mov %asr17, %o0\n"
diff -u rtems/c/src/lib/libbsp/sparc/leon3/include/tm27.h:1.1 rtems/c/src/lib/libbsp/sparc/leon3/include/tm27.h:1.2
--- rtems/c/src/lib/libbsp/sparc/leon3/include/tm27.h:1.1 Mon Jan 9 04:41:21 2006
+++ rtems/c/src/lib/libbsp/sparc/leon3/include/tm27.h Fri Feb 11 04:06:51 2011
@@ -39,7 +39,7 @@
set_vector( (handler), TEST_VECTOR, 1 );
#define Cause_tm27_intr() \
- asm volatile( "ta 0x10; nop " );
+ __asm__ volatile( "ta 0x10; nop " );
#define Clear_tm27_intr() /* empty */
diff -u rtems/c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c:1.4 rtems/c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c:1.5
--- rtems/c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c:1.4 Sun Nov 29 09:33:27 2009
+++ rtems/c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c Fri Feb 11 04:06:52 2011
@@ -41,7 +41,7 @@
* a deadlock condition.
*/
-asm(
+__asm__ (
".text\n"
".align 4\n"
"LEON3_Atomic_Swap:\n"
@@ -65,7 +65,7 @@
Shm_isrstat = isr_level;
while ( lock_value ) {
lock_value = LEON3_Atomic_Swap(lock_value, lockptr);
-/* asm volatile( "" */
+/* __asm__ volatile( "" */
/* : "=r" (lockptr), "=r" (lock_value) */
/* : "0" (lockptr), "1" (lock_value) */
/* ); */
diff -u rtems/c/src/lib/libbsp/sparc/leon3/startup/bspstart.c:1.18 rtems/c/src/lib/libbsp/sparc/leon3/startup/bspstart.c:1.19
--- rtems/c/src/lib/libbsp/sparc/leon3/startup/bspstart.c:1.18 Mon May 24 10:05:19 2010
+++ rtems/c/src/lib/libbsp/sparc/leon3/startup/bspstart.c Fri Feb 11 04:06:52 2011
@@ -41,7 +41,7 @@
static inline int set_snooping(void)
{
int tmp;
- asm(" lda [%1] 2, %0 "
+ __asm__ (" lda [%1] 2, %0 "
: "=r"(tmp)
: "r"(0xC)
);
diff -u rtems/c/src/lib/libbsp/sparc/leon3/startup/spurious.c:1.7 rtems/c/src/lib/libbsp/sparc/leon3/startup/spurious.c:1.8
--- rtems/c/src/lib/libbsp/sparc/leon3/startup/spurious.c:1.7 Sun Nov 29 09:33:27 2009
+++ rtems/c/src/lib/libbsp/sparc/leon3/startup/spurious.c Fri Feb 11 04:06:52 2011
@@ -120,7 +120,7 @@
* What else can we do but stop ...
*/
- asm volatile( "mov 1, %g1; ta 0x0" );
+ __asm__ volatile( "mov 1, %g1; ta 0x0" );
}
/*
*ralf*:
2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
* include/bsp.h:
Use "__asm__" instead of "asm" for improved c99-compliance.
M 1.5 c/src/lib/libbsp/sparc64/niagara/ChangeLog
M 1.2 c/src/lib/libbsp/sparc64/niagara/include/bsp.h
M 1.5 c/src/lib/libbsp/sparc64/usiii/ChangeLog
M 1.2 c/src/lib/libbsp/sparc64/usiii/include/bsp.h
diff -u rtems/c/src/lib/libbsp/sparc64/niagara/ChangeLog:1.4 rtems/c/src/lib/libbsp/sparc64/niagara/ChangeLog:1.5
--- rtems/c/src/lib/libbsp/sparc64/niagara/ChangeLog:1.4 Wed Feb 2 09:00:47 2011
+++ rtems/c/src/lib/libbsp/sparc64/niagara/ChangeLog Fri Feb 11 04:08:45 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * include/bsp.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libbsp/sparc64/niagara/include/bsp.h:1.1 rtems/c/src/lib/libbsp/sparc64/niagara/include/bsp.h:1.2
--- rtems/c/src/lib/libbsp/sparc64/niagara/include/bsp.h:1.1 Thu Jun 17 11:20:34 2010
+++ rtems/c/src/lib/libbsp/sparc64/niagara/include/bsp.h Fri Feb 11 04:08:45 2011
@@ -53,7 +53,7 @@
#define rtems_bsp_delay( microseconds ) \
{ register uint32_t _delay=(microseconds); \
register uint32_t _tmp = 0; /* initialized to avoid warning */ \
- asm volatile( "0: \
+ __asm__ volatile( "0: \
remo 3,31,%0 ; \
cmpo 0,%0 ; \
subo 1,%1,%1 ; \
diff -u rtems/c/src/lib/libbsp/sparc64/usiii/ChangeLog:1.4 rtems/c/src/lib/libbsp/sparc64/usiii/ChangeLog:1.5
--- rtems/c/src/lib/libbsp/sparc64/usiii/ChangeLog:1.4 Wed Feb 2 09:00:48 2011
+++ rtems/c/src/lib/libbsp/sparc64/usiii/ChangeLog Fri Feb 11 04:08:47 2011
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Corsépius <ralf.corsepius at rtems.org>
+
+ * include/bsp.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2011-02-02 Ralf Corsépius <ralf.corsepius at rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff -u rtems/c/src/lib/libbsp/sparc64/usiii/include/bsp.h:1.1 rtems/c/src/lib/libbsp/sparc64/usiii/include/bsp.h:1.2
--- rtems/c/src/lib/libbsp/sparc64/usiii/include/bsp.h:1.1 Thu Jun 17 11:20:39 2010
+++ rtems/c/src/lib/libbsp/sparc64/usiii/include/bsp.h Fri Feb 11 04:08:47 2011
@@ -55,7 +55,7 @@
#define rtems_bsp_delay( microseconds ) \
{ register uint32_t _delay=(microseconds); \
register uint32_t _tmp = 0; /* initialized to avoid warning */ \
- asm volatile( "0: \
+ __asm__ volatile( "0: \
remo 3,31,%0 ; \
cmpo 0,%0 ; \
subo 1,%1,%1 ; \
--
Generated by Deluxe Loginfo [http://www.codewiz.org/projects/index.html#loginfo] 2.122 by Bernardo Innocenti <bernie at develer.com>
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