[rtems commit] bsp/gen83xx: Fix CSB clock calculation for MPC8309

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    566c05c896f4431f10d6cb7575eb693924bde975
Changeset: http://git.rtems.org/rtems/commit/?id=566c05c896f4431f10d6cb7575eb693924bde975

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Wed Dec 19 13:41:27 2012 +0100

bsp/gen83xx: Fix CSB clock calculation for MPC8309

---

 .../libbsp/powerpc/gen83xx/include/hwreg_vals.h    |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
index c7c3d2a..49ababb 100644
--- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
+++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
@@ -361,7 +361,12 @@
  * derived values for all boards
  */
 /* value of input clock divider (derived from pll mode reg) */
-#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
+#if MPC83XX_CHIP_TYPE != 8309
+  #define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
+#else
+  /* On the MPC8309 this bit is reserved */
+  #define BSP_SYSPLL_CKID 1
+#endif
 /* value of system pll (derived from pll mode reg) */
 #define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f)
 /* value of system pll (derived from pll mode reg) */