[rtems commit] bsp/qoriq: Flush and invalidate L2 cache

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    f966d608e22ba2b92fb39504200ba9cd300d732c
Changeset: http://git.rtems.org/rtems/commit/?id=f966d608e22ba2b92fb39504200ba9cd300d732c

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Oct 27 10:43:27 2015 +0100

bsp/qoriq: Flush and invalidate L2 cache

---

 c/src/lib/libbsp/powerpc/qoriq/configure.ac  |  4 ++++
 c/src/lib/libbsp/powerpc/qoriq/start/start.S | 23 +++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/c/src/lib/libbsp/powerpc/qoriq/configure.ac b/c/src/lib/libbsp/powerpc/qoriq/configure.ac
index 466ddaf..a02f209 100644
--- a/c/src/lib/libbsp/powerpc/qoriq/configure.ac
+++ b/c/src/lib/libbsp/powerpc/qoriq/configure.ac
@@ -164,6 +164,10 @@ RTEMS_BSPOPTS_SET([QORIQ_MMU_DEVICE_MAS7],[qoriq_t*],[0xf])
 RTEMS_BSPOPTS_SET([QORIQ_MMU_DEVICE_MAS7],[*],[0x0])
 RTEMS_BSPOPTS_HELP([QORIQ_MMU_DEVICE_MAS7],[MAS7 value for device TLB1 entries])
 
+RTEMS_BSPOPTS_SET([QORIQ_L2CSR0],[qoriq_t*],[0xfec20000])
+RTEMS_BSPOPTS_SET([QORIQ_L2CSR0],[*],[])
+RTEMS_BSPOPTS_HELP([QORIQ_L2CSR0],[address of L2CSR0 register])
+
 RTEMS_BSPOPTS_SET([QORIQ_CLOCK_TIMER],[qoriq_core_1],[4])
 RTEMS_BSPOPTS_SET([QORIQ_CLOCK_TIMER],[*],[0])
 RTEMS_BSPOPTS_HELP([QORIQ_CLOCK_TIMER],[global timer used for system clock, 0..3 maps to A0..A3, and 4..7 maps to B0..B3])
diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S
index 10daf32..5d2a09d 100644
--- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S
+++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S
@@ -80,6 +80,29 @@ _start:
 	bne	1b
 	isync
 
+#ifdef QORIQ_L2CSR0
+	/* Flush L2 cache of first cluster */
+	LWI	r4, QORIQ_L2CSR0
+	lwz	r3, 0(r4)
+	oris	r3, r3, FSL_EIS_L2CSR0_L2FL >> 16
+	stw	r3, 0(r4)
+1:
+	lwz	r3, 0(r4)
+	andis.	r3, r3, FSL_EIS_L2CSR0_L2FL >> 16
+	bne	1b
+	isync
+
+	/* Invalidate L2 cache of first cluster */
+	lwz	r3, 0(r4)
+	oris	r3, r3, FSL_EIS_L2CSR0_L2FI >> 16
+	stw	r3, 0(r4)
+1:
+	lwz	r3, 0(r4)
+	andis.	r3, r3, FSL_EIS_L2CSR0_L2FI >> 16
+	bne	1b
+	isync
+#endif
+
 	/* Get start stack */
 	LWI	START_STACK, start_stack_end