[rtems commit] bsp/qoriq: Invalidate L1 cache on boot processor

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    ac4f1718db41ef0550c9faf3188f3c7a54c9f024
Changeset: http://git.rtems.org/rtems/commit/?id=ac4f1718db41ef0550c9faf3188f3c7a54c9f024

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Tue Oct 27 10:18:45 2015 +0100

bsp/qoriq: Invalidate L1 cache on boot processor

---

 c/src/lib/libbsp/powerpc/qoriq/start/start.S | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S
index 4499850..10daf32 100644
--- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S
+++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S
@@ -60,6 +60,26 @@ _start:
 	bl	bsp_fdt_copy
 #endif /* U_BOOT_USE_FDT */
 
+	/* Invalidate L1 data cache */
+	mfspr	r3, FSL_EIS_L1CSR0
+	ori	r3, r3, FSL_EIS_L1CSR0_CFI
+	mtspr	FSL_EIS_L1CSR0, r3
+1:
+	mfspr	r3, FSL_EIS_L1CSR0
+	andi.	r3, r3, FSL_EIS_L1CSR0_CFI
+	bne	1b
+	isync
+
+	/* Invalidate L1 instruction cache */
+	mfspr	r3, FSL_EIS_L1CSR1
+	ori	r3, r3, FSL_EIS_L1CSR1_ICFI
+	mtspr	FSL_EIS_L1CSR1, r3
+1:
+	mfspr	r3, FSL_EIS_L1CSR1
+	andi.	r3, r3, FSL_EIS_L1CSR1_ICFI
+	bne	1b
+	isync
+
 	/* Get start stack */
 	LWI	START_STACK, start_stack_end