[rtems commit] arm: Optimize arm_interrupt_disable()

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    a299c4feef70318c5098cb1d15557b37ac253d17
Changeset: http://git.rtems.org/rtems/commit/?id=a299c4feef70318c5098cb1d15557b37ac253d17

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Thu Dec 10 07:52:03 2020 +0100

arm: Optimize arm_interrupt_disable()

Update #4202.

---

 cpukit/score/cpu/arm/include/rtems/score/cpu.h | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
index 8a8e8cc..e5b23e7 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h
@@ -276,8 +276,6 @@ static inline uint32_t arm_interrupt_disable( void )
   uint32_t level;
 
 #if defined(ARM_MULTILIB_ARCH_V4)
-  uint32_t arm_switch_reg;
-
   /*
    * Disable only normal interrupts (IRQ).
    *
@@ -292,6 +290,16 @@ static inline uint32_t arm_interrupt_disable( void )
    * operating system support for a FIQ, she can trigger a software interrupt and
    * service the request in a two-step process.
    */
+#if __ARM_ARCH >= 7
+  __asm__ volatile (
+    "mrs %0, cpsr\n"
+    "cpsid i\n"
+    "isb"
+    : "=&r" (level)
+  );
+#else
+  uint32_t arm_switch_reg;
+
   __asm__ volatile (
     ARM_SWITCH_TO_ARM
     "mrs %[level], cpsr\n"
@@ -300,6 +308,7 @@ static inline uint32_t arm_interrupt_disable( void )
     ARM_SWITCH_BACK
     : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
   );
+#endif
 #elif defined(ARM_MULTILIB_ARCH_V7M)
   uint32_t basepri = 0x80;