[rtems commit] riscv: Use zicsr architecture extension
Sebastian Huber
sebh at rtems.org
Sat Feb 26 06:03:49 UTC 2022
Module: rtems
Branch: master
Commit: faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2
Changeset: http://git.rtems.org/rtems/commit/?id=faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Fri Feb 25 17:45:06 2022 +0100
riscv: Use zicsr architecture extension
This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
---
bsps/riscv/griscv/clock/clockdrv.c | 8 +++++-
bsps/riscv/shared/start/start.S | 1 +
cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 32 ++++++++++++++++++----
.../score/cpu/riscv/include/rtems/score/cpuimpl.h | 8 +++++-
.../cpu/riscv/include/rtems/score/riscv-utility.h | 15 ++++++----
cpukit/score/cpu/riscv/riscv-context-switch.S | 1 +
cpukit/score/cpu/riscv/riscv-exception-handler.S | 1 +
7 files changed, 54 insertions(+), 12 deletions(-)
diff --git a/bsps/riscv/griscv/clock/clockdrv.c b/bsps/riscv/griscv/clock/clockdrv.c
index 4cf15fe..a5b7b15 100644
--- a/bsps/riscv/griscv/clock/clockdrv.c
+++ b/bsps/riscv/griscv/clock/clockdrv.c
@@ -187,7 +187,13 @@ CPU_Counter_ticks _CPU_Counter_read( void )
{
unsigned long timec;
- __asm__ volatile ( "csrr %0, time" : "=&r" ( timec ) );
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrr %0, time\n"
+ ".option pop" :
+ "=&r" ( timec )
+ );
return timec;
}
diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S
index 04a62a2..3702f8a 100644
--- a/bsps/riscv/shared/start/start.S
+++ b/bsps/riscv/shared/start/start.S
@@ -39,6 +39,7 @@ PUBLIC(_start)
.section .bsp_start_text, "wax", @progbits
.align 2
+ .option arch, +zicsr
TYPE_FUNC(_start)
SYM(_start):
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index 3f3c8de..05ef270 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -152,7 +152,10 @@ static inline uint32_t riscv_interrupt_disable( void )
unsigned long mstatus;
__asm__ volatile (
- "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) :
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrc %0, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+ ".option pop" :
"=&r" ( mstatus )
);
@@ -161,7 +164,14 @@ static inline uint32_t riscv_interrupt_disable( void )
static inline void riscv_interrupt_enable( uint32_t level )
{
- __asm__ volatile ( "csrrs zero, mstatus, %0" : : "r" ( level ) );
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrs zero, mstatus, %0\n"
+ ".option pop" :
+ :
+ "r" ( level )
+ );
}
#define _CPU_ISR_Disable( _level ) \
@@ -185,11 +195,17 @@ RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level( uint32_t level )
{
if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
__asm__ volatile (
- "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+ ".option pop"
);
} else {
__asm__ volatile (
- "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE )
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
+ ".option pop"
);
}
}
@@ -465,7 +481,13 @@ static inline uint32_t _CPU_SMP_Get_current_processor( void )
{
unsigned long mhartid;
- __asm__ volatile ( "csrr %0, mhartid" : "=&r" ( mhartid ) );
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrr %0, mhartid\n"
+ ".option pop" :
+ "=&r" ( mhartid )
+ );
return (uint32_t) mhartid;
}
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
index eee6ad7..5162cbb 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
@@ -399,7 +399,13 @@ static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void )
{
struct Per_CPU_Control *cpu_self;
- __asm__ volatile ( "csrr %0, mscratch" : "=r" ( cpu_self ) );
+ __asm__ volatile (
+ ".option push\n"
+ ".option arch, +zicsr\n"
+ "csrr %0, mscratch\n"
+ ".option pop" :
+ "=r" ( cpu_self )
+ );
return cpu_self;
}
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h
index dc4836b..1cfcf8d 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h
@@ -247,22 +247,27 @@ typedef enum {
#ifdef __GNUC__
#define read_csr(reg) ({ unsigned long __tmp; \
- asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ asm volatile (".option push\n.option arch, +zicsr\n" \
+ "csrr %0, " #reg "\n.option pop ": "=r"(__tmp)); \
__tmp; })
#define write_csr(reg, val) ({ \
- asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+ asm volatile (".option push\n.option arch, +zicsr\n" \
+ "csrw " #reg ", %0\n.option pop" :: "rK"(val)); })
#define swap_csr(reg, val) ({ unsigned long __tmp; \
- asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+ asm volatile (".option push\n.option arch, +zicsr\n" \
+ "csrrw %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(val)); \
__tmp; })
#define set_csr(reg, bit) ({ unsigned long __tmp; \
- asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ asm volatile (".option push\n.option arch, +zicsr\nc" \
+ "srrs %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
- asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ asm volatile (".option push\n.option arch, +zicsr\n" \
+ "csrrc %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define rdtime() read_csr(time)
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S
index 830f862..3c03688 100644
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -35,6 +35,7 @@
.section .text, "ax", @progbits
.align 2
+ .option arch, +zicsr
PUBLIC(_CPU_Context_switch)
PUBLIC(_CPU_Context_switch_no_return)
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S
index 9330f24..87a6965 100644
--- a/cpukit/score/cpu/riscv/riscv-exception-handler.S
+++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S
@@ -45,6 +45,7 @@ PUBLIC(_RISCV_Exception_handler)
.section .text, "ax", @progbits
.align 2
+ .option arch, +zicsr
TYPE_FUNC(_RISCV_Exception_handler)
SYM(_RISCV_Exception_handler):
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