[rtems commit] powerpc: Use .machine any for some inline asm
Sebastian Huber
sebh at rtems.org
Sat Feb 26 06:32:08 UTC 2022
Module: rtems
Branch: master
Commit: a286d28695d312971400c6b25f43d0794f5e9be8
Changeset: http://git.rtems.org/rtems/commit/?id=a286d28695d312971400c6b25f43d0794f5e9be8
Author: Sebastian Huber <sebastian.huber at embedded-brains.de>
Date: Fri Feb 25 21:11:00 2022 +0100
powerpc: Use .machine any for some inline asm
---
bsps/powerpc/include/libcpu/powerpc-utility.h | 7 ++++++-
bsps/powerpc/include/libcpu/spr.h | 18 ++++++++++++++++--
bsps/powerpc/mpc55xxevb/include/mpc55xx/mpc55xx.h | 7 ++++++-
bsps/powerpc/mvme3100/start/bspstart.c | 16 ++++++++++++++--
bsps/powerpc/shared/clock/clock-ppc403.c | 17 +++++++++++++++--
bsps/powerpc/shared/mmu/pte121.c | 12 +++++++++++-
bsps/powerpc/virtex/start/bspstart.c | 8 +++++++-
bsps/powerpc/virtex4/start/mmu.c | 20 ++++++++++++++++----
8 files changed, 91 insertions(+), 14 deletions(-)
diff --git a/bsps/powerpc/include/libcpu/powerpc-utility.h b/bsps/powerpc/include/libcpu/powerpc-utility.h
index 2827430..d1cfe23 100644
--- a/bsps/powerpc/include/libcpu/powerpc-utility.h
+++ b/bsps/powerpc/include/libcpu/powerpc-utility.h
@@ -229,7 +229,12 @@ static inline void ppc_enforce_in_order_execution_of_io(void)
{
RTEMS_COMPILER_MEMORY_BARRIER();
- __asm__ volatile ("eieio");
+ __asm__ volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "eieio\n"
+ ".machine \"pop\""
+ );
}
static inline void ppc_data_cache_block_flush(void *addr)
diff --git a/bsps/powerpc/include/libcpu/spr.h b/bsps/powerpc/include/libcpu/spr.h
index 6c81d0e..dea0cde 100644
--- a/bsps/powerpc/include/libcpu/spr.h
+++ b/bsps/powerpc/include/libcpu/spr.h
@@ -64,13 +64,27 @@ static inline void _write_MSR(unsigned long val)
static inline unsigned long _read_SR(void * va)
{
unsigned long val;
- asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va));
+ asm volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mfsrin %0,%1\n"
+ ".machine \"pop\"" :
+ "=r" (val) :
+ "r" (va)
+ );
return val;
}
static inline void _write_SR(unsigned long val, void * va)
{
- asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory");
+ asm volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mtsrin %0,%1\n"
+ ".machine \"pop\"" : :
+ "r" (val) , "r" (va) :
+ "memory"
+ );
return;
}
diff --git a/bsps/powerpc/mpc55xxevb/include/mpc55xx/mpc55xx.h b/bsps/powerpc/mpc55xxevb/include/mpc55xx/mpc55xx.h
index 61d70ee..508e3f2 100644
--- a/bsps/powerpc/mpc55xxevb/include/mpc55xx/mpc55xx.h
+++ b/bsps/powerpc/mpc55xxevb/include/mpc55xx/mpc55xx.h
@@ -129,7 +129,12 @@ static inline uint32_t mpc55xx_count_leading_zeros( uint32_t value)
static inline void mpc55xx_wait_for_interrupt(void)
{
#ifdef MPC55XX_HAS_WAIT_INSTRUCTION
- __asm__ volatile ("wait");
+ __asm__ volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "wait\n"
+ ".machine \"pop\""
+ );
#else
__asm__ volatile ("");
#endif
diff --git a/bsps/powerpc/mvme3100/start/bspstart.c b/bsps/powerpc/mvme3100/start/bspstart.c
index 0ec215e..f27304c 100644
--- a/bsps/powerpc/mvme3100/start/bspstart.c
+++ b/bsps/powerpc/mvme3100/start/bspstart.c
@@ -364,9 +364,21 @@ VpdBufRec vpdData [] = {
int i;
unsigned msr,tcr;
asm volatile("mfmsr %0":"=r"(msr));
- asm volatile("mftcr %0":"=r"(tcr));
+ asm volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mftcr %0\n"
+ ".machine \"pop\"" :
+ "=r"(tcr)
+ );
printk("MSR is 0x%08x, TCR 0x%08x\n",msr,tcr);
- asm volatile("mttcr %0"::"r"(0));
+ asm volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mttcr %0\n"
+ ".machine \"pop\"" : :
+ "r"(0)
+ );
if (0) {
asm volatile("mtmsr %0"::"r"(msr|0x8000));
for (i=0; i<12; i++)
diff --git a/bsps/powerpc/shared/clock/clock-ppc403.c b/bsps/powerpc/shared/clock/clock-ppc403.c
index 170c17e..bc74445 100644
--- a/bsps/powerpc/shared/clock/clock-ppc403.c
+++ b/bsps/powerpc/shared/clock/clock-ppc403.c
@@ -188,9 +188,22 @@ static void ClockOn(const rtems_irq_connect_data* unused)
auto_restart = true;
#else /* ppc405 */
- __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */
+ __asm__ volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mfdcr %0, 0x0b2\n"
+ ".machine \"pop\"" :
+ "=r" (iocr)
+ ); /*405GP CPC0_CR1 */
iocr &=~0x800000; /* timer clocked from system clock CETE*/
- __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
+ __asm__ volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mtdcr 0x0b2, %0\n"
+ ".machine \"pop\"" :
+ "=r" (iocr) :
+ "0" (iocr)
+ ); /* 405GP CPC0_CR1 */
/*
* Enable auto restart
diff --git a/bsps/powerpc/shared/mmu/pte121.c b/bsps/powerpc/shared/mmu/pte121.c
index 778d635..e97c86b 100644
--- a/bsps/powerpc/shared/mmu/pte121.c
+++ b/bsps/powerpc/shared/mmu/pte121.c
@@ -158,7 +158,14 @@
static uint32_t
seg2vsid (uint32_t ea)
{
- __asm__ volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
+ __asm__ volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mfsrin %0, %0\n"
+ ".machine \"pop\"" :
+ "=r" (ea) :
+ "0" (ea)
+ );
return ea & ((1 << LD_VSID_SIZE) - 1);
}
#else
@@ -620,6 +627,8 @@ triv121PgTblActivate (Triv121PgTbl pt)
* - restore original MSR
*/
__asm__ __volatile (
+ " .machine \"push\"\n"
+ " .machine \"any\"\n"
" mtctr %[tmp0]\n"
/* Get MSR and switch interrupts off - just in case.
* Also switch the MMU off; the book
@@ -651,6 +660,7 @@ triv121PgTblActivate (Triv121PgTbl pt)
/* restore original MSR */
" mtmsr %[tmp0]\n"
" isync \n"
+ " .machine \"pop\"\n"
:[tmp0]"+r&"(tmp0), [tmp1]"+b&"(tmp1), [tmp2]"+b&"(tmp2)
:[ea_range]"i"(FLUSH_EA_RANGE), [pg_sz]"i" (1 << LD_PG_SIZE),
[sdr1]"i"(SDR1), [sdr1val]"r" (sdr1)
diff --git a/bsps/powerpc/virtex/start/bspstart.c b/bsps/powerpc/virtex/start/bspstart.c
index a4054f1..11eb57c 100644
--- a/bsps/powerpc/virtex/start/bspstart.c
+++ b/bsps/powerpc/virtex/start/bspstart.c
@@ -98,7 +98,13 @@ void bsp_start( void )
(uintptr_t) _ISR_Stack_area_begin,
virtex_exc_vector_base
);
- __asm__ volatile ("mtevpr %0" : : "r" (virtex_exc_vector_base));
+ __asm__ volatile (
+ ".machine \"push\"\n"
+ ".machine \"any\"\n"
+ "mtevpr %0\n"
+ ".machine \"pop\"" : :
+ "r" (virtex_exc_vector_base)
+ );
bsp_interrupt_initialize();
}
diff --git a/bsps/powerpc/virtex4/start/mmu.c b/bsps/powerpc/virtex4/start/mmu.c
index 906ac70..8013f9c 100644
--- a/bsps/powerpc/virtex4/start/mmu.c
+++ b/bsps/powerpc/virtex4/start/mmu.c
@@ -133,13 +133,16 @@ static void
fetch(bsp_tlb_idx_t key, bsp_tlb_entry_t* tlb)
{
register uint32_t tmp;
- __asm__ volatile ("mfpid %[tmp] \n\t"
+ __asm__ volatile (".machine \"push\" \n\t"
+ ".machine \"any\" \n\t"
+ "mfpid %[tmp] \n\t"
"stw %[tmp],0(%[tlb]) \n\t"
"tlbrehi %[tmp],%[key] \n\t"
"stw %[tmp],4(%[tlb]) \n\t"
"tlbrelo %[tmp],%[key] \n\t"
"stw %[tmp],8(%[tlb]) \n\t"
"sync \n\t"
+ ".machine \"pop\" \n\t"
: [tmp]"=&r"(tmp)
: [key]"r"(key),
[tlb]"b"(tlb)
@@ -151,12 +154,15 @@ static void
store(bsp_tlb_idx_t key, bsp_tlb_entry_t* tlb)
{
register uint32_t tmp;
- __asm__ volatile ("lwz %[tmp],0(%[tlb]) \n\t"
+ __asm__ volatile (".machine \"push\" \n\t"
+ ".machine \"any\" \n\t"
+ "lwz %[tmp],0(%[tlb]) \n\t"
"mtpid %[tmp] \n\t"
"lwz %[tmp],4(%[tlb]) \n\t"
"tlbwehi %[tmp],%[key] \n\t"
"lwz %[tmp],8(%[tlb]) \n\t"
"tlbwelo %[tmp],%[key] \n\t"
+ ".machine \"pop\" \n\t"
: [tmp]"=&r"(tmp)
: [tlb]"b"(tlb),
[key]"r"(key)
@@ -290,9 +296,12 @@ bsp_mmu_find_first_free()
for (idx=0; idx<NTLBS; idx++) {
register uint32_t tmp;
- __asm__ volatile ("tlbrehi %[tmp],%[idx] \n\t"
+ __asm__ volatile (".machine \"push\" \n\t"
+ ".machine \"any\" \n\t"
+ "tlbrehi %[tmp],%[idx] \n\t"
"stw %[tmp],4(%[tlb]) \n\t" /* entry.hi */
"sync \n\t"
+ ".machine \"pop\" \n\t"
: [tmp]"=&r"(tmp)
: [idx]"r"(idx),
[tlb]"b"(&entry)
@@ -489,11 +498,14 @@ bsp_mmu_find(uint32_t ea, uint32_t tid)
rtems_interrupt_disable(lvl);
- __asm__ volatile ("mfpid %[pid] \n\t" /* Save PID */
+ __asm__ volatile (".machine \"push\"\n\t"
+ ".machine \"any\"\n\t"
+ "mfpid %[pid] \n\t" /* Save PID */
"mtpid %[tid] \n\t"
"tlbsx. %[idx],0,%[ea] \n\t" /* Failure changes the index reg randomly. */
"mfcr %[failure] \n\t"
"mtpid %[pid] \n\t" /* Restore PID */
+ ".machine \"pop\"\n\t"
: [pid]"=r"(pid),
[idx]"=&r"(idx),
[failure]"=&r"(failure)
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